| eASIC Corporation Patent applications |
| Patent application number | Title | Published |
|---|
| 20120243285 | MULTIPLE WRITE DURING SIMULTANEOUS MEMORY ACCESS OF A MULTI-PORT MEMORY DEVICE - A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously. | 09-27-2012 |
| 20120161093 | Via-Configurable High-Performance Logic Block Architecture - A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block. | 06-28-2012 |
| 20110067982 | MEMS-BASED SWITCHING - A MEMS-based switching device may be used to implement an interconnect switch in a programmable integrated circuit device. Such a MEMS-based device may include a deformable cantilever that may form a closed or open circuit to thereby implement switching functionality. | 03-24-2011 |
| 20100195419 | Configurable Write Policy in a Memory System - A configurable memory system may be able to support at least three different write policies, namely, no-read-on-write, read-before-write, and read-after-write. Such a system may include configurable write signal timing, configurable read signal timing, and/or configurable wordline enable signal timing. Static and/or dynamic configuration of the system may be used. | 08-05-2010 |
| 20100182044 | PROGRAMMING AND CIRCUIT TOPOLOGIES FOR PROGRAMMABLE VIAS - A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state. | 07-22-2010 |
| 20090109765 | Single via structured IC device - A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable register files, customizable RAM blocks; a ROM block with customizable contents; or test logic With customizable test options and configurations to separately test logic and the PLLs. | 04-30-2009 |
| 20080263381 | DYNAMIC PHASE ALIGNMENT - A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal. | 10-23-2008 |
| 20080224260 | Programmable Vias for Structured ASICs - A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state. | 09-18-2008 |
