| DSEM HOLDINGS SDN. BHD. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110176301 | METHOD TO PRODUCE HOMOGENEOUS LIGHT OUTPUT BY SHAPING THE LIGHT CONVERSION MATERIAL IN MULTICHIP MODULE - A multichip module includes a series of light sources arranged in a planar array, separated by a distance d | 07-21-2011 |
| 20110122630 | Solid State Lamp Having Vapor Chamber - A solid state lamp has a form that replaces a standard screw-in or plug-in type light bulb. One or more LEDs are mounted on a thermally conductive submount, which is mounted on the top surface of a substantially round and flat vapor chamber. The vapor chamber efficiently spreads the heat and also conducts heat vertically. The vapor chamber is affixed to a substantially round mounting base of a metal housing. In this way, the very small LED dies appear to the mounting base as much larger heat sources producing less heat per unit area, and the thermal resistance of the heat path is greatly reduced. The housing has ventilation openings for cooling a bottom surface of the mounting base. The top of the vapor chamber is highly reflective, and the housing has a high emissivity coating. A standard base is attached to the housing for connection to an AC mains voltage. | 05-26-2011 |
| 20110121326 | Submount Having Reflective Cu-Ni-Ag Pads Formed Using Electroless Deposition - A submount for an LED has relatively large copper pads formed on its top surface using an electroless process so that no electrical bias circuitry is required for the submount. The copper pads are then coated with nickel using an electroless process. The nickel layer is then coated with silver using an electroless process, such as an immersion silver process. In one embodiment, the silver layer is less than one micron thick. The Ni layer prevents a reduction in reflectivity of the Ag after long periods of use while conducting the high current (300 mA to >1 amp) needed for high power LEDs. The silver layer surrounds at least 75% of the periphery of the LED die and extends at least 1 mm around the periphery of the die to reflect the LED light. | 05-26-2011 |
| 20110108245 | Circuit Board Forming Diffusion Bonded Wall of Vapor Chamber - A method for providing a high in-plane and through-plane thermal conductivity path between a heat producing electronic device and a heat sink is described. A vapor chamber is formed of a bottom metal shell and a top plate which are diffusion bonded together at their edges. The top plate is itself a circuit board that may be a metal core type, a ceramic type, or any bondable composite material. The metal core circuit board is preferably aluminum, and the dielectric regions on its top surface are aluminum oxide regions. A metal circuit layer is formed on the dielectric regions for interconnecting electronic devices mounted on the circuit board. Since the back surface of the circuit board is directly in contact with the working fluid in the vapor chamber, there is the ultimate in thermal coupling between the circuit board and a heat sink connected to the back of the vapor chamber. | 05-12-2011 |
| 20100071936 | Thermally-Efficient Metal Core Printed Circuit Board With Selective Electrical And Thermal Connectivity - Methods for controlling thermal conductivity paths in a metal core circuit board, as well as methods to provide selective electrical isolation, are described. In one embodiment, grooves are formed in an aluminum substrate surrounding areas where electrical components are to be mounted on the substrate. The grooves are oxidized along with the opposing surface of the substrate to create a vertical oxide ring around the area for electrical and lateral thermal isolation. This also allows the substrate to be made relatively thick for mechanical strength. Other features include forming copper around oxidized sides of the substrate for connection between top and bottom copper layers; plating up copper to be co-planar with a raised dielectric layer; forming indentions in the substrate for containing a dielectric so the dielectric is co-planar with the remaining surface; forming copper vias through the substrate; and planarizing the substrate surface so that conductors and dielectric layers are co-planar. | 03-25-2010 |
