| Dongbu HiTek Co., Ltd. Patent applications |
| Patent application number | Title | Published |
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| 20130134526 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench. | 05-30-2013 |
| 20130093017 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An LDMOS device includes a second conduction type buried layer, a first conduction type drain extension region configured to be formed on and/or over a region of the second conduction type buried layer, a second conduction type drain extension region configured to be formed in a partial region of the first conduction type drain extension region, a first conduction type body, a first guard ring configured to be formed around the second conduction type drain extension region and configured to include a second conduction type impurity layer, and a second guard ring configured to be formed around the first guard ring and configured to include a high-voltage second conduction type well and a second conduction type impurity layer. Further, the second conduction type impurity layer of the first guard ring and the second conduction type impurity layer of the second guard ring operate as an isolation. | 04-18-2013 |
| 20130093016 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer. | 04-18-2013 |
| 20130093014 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a laterally double diffused metal oxide semiconductor (LDMOS) transistor formed on a partial region of a epitaxial layer of a first conductive type, a bipolar transistor formed on another partial region of the epitaxial layer of the first conductive type, and a guard ring formed between the partial region and the another partial region. The guard ring serves to restrain electrons generated by a forward bias operation of the LDMOS transistor from being introduced into the bipolar transistor. | 04-18-2013 |
| 20130093013 | HIGH VOLTAGE TRANSISTOR AND MANUFACTURING METHOD THEREFOR - A high-voltage transistor may include a semiconductor substrate, and a gate electrode formed on and/or over the semiconductor substrate. Further, the high-voltage transistor may include source/drain regions formed on and/or over the semiconductor substrate at one side of the gate electrode, and impurity layers having a super junction structure and formed on and/or over a boundary of a drift region disposed below the gate electrode. | 04-18-2013 |
| 20130092939 | BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film. | 04-18-2013 |
| 20130075816 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an LDMOS device and a method for manufacturing the same capable of decreasing the concentration of a drift region between a source finger tip and a drain, thereby increasing a breakdown voltage. An LDMOS device includes a gate which is formed on a substrate, a source and a drain which are separately arranged on both sides of the substrate with the gate interposed therebetween, a field oxide film which is formed to have a step between the gate and the drain, a drift region which is formed of first condition type impurity ions between the gate and the drain on the substrate, and at least one internal field ring which is formed inside the drift region and formed by selectively ion-implanting second conduction type impurity ions in accordance with the step of the field oxide film. | 03-28-2013 |
| 20130063039 | ISOLATED FLYBACK CONVERTER FOR LIGHT EMITTING DIODE DRIVER - An isolated flyback converter for an LED driver may include: (1) A snubber circuit configured to be connected to the primary side of a transformer. (2) A switching unit configured to have a source terminal and a drain terminal and configured to be turned on or off. (3) A control unit configured to detect a first input signal proportional to a fluctuation in the power supply voltage, detect a second input signal when the switching unit is turned off, generate a signal inversely proportional to the maximum value of the first input signal and multiply the generated signal to the second input signal, and control a peak current of the switching unit to be proportional to the multiplication result of the signal inversely proportional to the maximum value of the first input signal and the second input signal such that a secondary-side current of the transformer is maintained constant. | 03-14-2013 |
| 20130037861 | IMAGE SENSOR FOR SEMICONDUCTOR LIGHT-SENSITIVE DEVICE, MANUFACTURING METHOD THEREOF, IMAGE PROCESSING APPARATUS USING THE SAME, AND METHOD FOR DETECTING COLOR SIGNAL - An image sensor for a semiconductor light-sensitive device including a semiconductor substrate and a light receiving device configured to receive light and generate a signal from the light. The image sensor may include an electron collecting device formed in the semiconductor substrate to receive at least a portion of the electrons generated by the light in the light receiving device. The image sensor may include a first type device isolation film configured to isolate the light receiving device from the electron collecting device. The image sensor may include a shielding film formed over the semiconductor substrate and configured to shield the first electron collecting device from the light. | 02-14-2013 |
| 20130033197 | ISOLATED FLYBACK CONVERTER FOR LIGHT EMITTING DIODE DRIVER - An isolated flyback converter for an LED driver includes a snubber circuit unit connected to the primary side of a transformer; and a snubber voltage detection unit which detects a snubber voltage of the snubber circuit unit and generates a reference voltage proportional to the detected snubber voltage. Further, the isolated flyback converter includes a switching unit with a source terminal and a drain terminal, and may be turned on or off in response to an arbitrary logic signal. Furthermore, the isolated flyback converter includes a control unit which compares a voltage supplied through the switching current sensing resistor with the reference voltage, and supplies a logic signal at relatively high level or relatively low level to the switching unit to control the switching unit such that a secondary-side current of the transformer is maintained relatively constant. | 02-07-2013 |
| 20130032918 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor may include a semiconductor substrate, a plurality of light receiving devices formed within the semiconductor substrate, and a plurality of device isolation films for isolating the light receiving devices from each other. When an arrangement direction of a pixel array may be formed by arranging the light receiving devices is a horizontal direction, the pixel array may be formed by alternately arranging a first type light receiving device and a second type light receiving device having different horizontal lengths. | 02-07-2013 |
| 20110224083 | URACIL COMPOUNDS AND A HERBICIDE COMPRISING THE SAME - Disclosed are uracil compounds represented by Formula 1, a method for preparing the compounds, and a herbicide including the same as an active ingredient: | 09-15-2011 |
| 20110157979 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, a method of manufacturing the same, and a cell array of a semiconductor memory device are provided. The semiconductor memory device includes: a first gate insulation layer and a second gate insulation layer, being spaced a predetermined distance from each other, on a portion of a semiconductor substrate; a select gate on the first gate insulation layer; a floating gate on the second gate insulation layer; a third gate insulation layer on the floating gate; a control gate on the third gate insulation layer; a first ion implantation region in the semiconductor substrate between the select gate and the floating gate; a second ion implantation region in the semiconductor substrate at a side of the select gate opposite the first ion implantation region; and a third ion implantation region in the semiconductor substrate at a side of the floating gate opposite the first ion implantation region. | 06-30-2011 |
| 20110141806 | Flash Memory Device and Method for Manufacturing Flash Memory Device - A method of manufacturing a flash memory device is provided. First and second gates are formed on first and second dielectrics and spaced apart from each other on a cell area of a substrate. A third gate is formed on a third dielectric that is formed on first opposing sidewalls of the first gate and extending on a portion of the substrate from the first opposing sidewalls. A fourth gate is formed on a fourth dielectric that is formed on second opposing sidewalls of the second gate and extending on a portion of the substrate from the second opposing sidewalls. The third gate and third dielectric on one of the first opposing sidewalls facing the second gate and the fourth gate and fourth dielectric on one of the second opposing sidewalls facing the first gate are removed. Drain areas are formed at outer sides of the third and fourth gates, and a common source area is formed between the first and second gates. | 06-16-2011 |
| 20110140186 | CAPACITOR FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF CAPACITOR FOR SEMICONDUCTOR DEVICE - Disclosed are a capacitor for a semiconductor device and a manufacturing method thereof. The capacitor includes a second oxide layer filling a first trench in a semiconductor substrate; second and third trenches in an active region at opposing sides of the second oxide layer in the first trench; a third oxide layer on the semiconductor substrate and on inner surfaces of the second and third trenches; and a polysilicon layer on the third oxide layer to fill the second and third trenches. | 06-16-2011 |
| 20100110064 | SOURCE DRIVER AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME - A source driver and a liquid crystal display (LCD) device having the same. A source driver may carry a clock in a data current, and may recover a clock signal and/or a data signal without being substantially affected by external frequencies and/or resistance. A source driver may include a trans-impedance amplifier which may receive data currents, convert data currents into voltages, and/or output voltages as data voltages and/or clock voltages. A source driver may include a comparator electrically coupled to a trans-impedance amplifier, which may change levels of data and/or clock voltages applied from a trans-impedance amplifier, and/or may output level-changed voltages as data signals and/or a clock signal. | 05-06-2010 |
| 20100044820 | CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - A CMOS image sensor is disclosed. The image sensor includes a plurality of polysilicon patterns provided on a silicon epitaxial layer which correspond to the location of a plurality of photodiodes provided in a dummy pixel area, a silicide layer of metal with a high melting point provided on the plurality of the polysilicon patterns, a device protecting layer and a planarization layer provided on the silicon epitaxial layer and silicide layer, and a plurality of microlenses on the planarization layer which correspond to the location of the silicide layer. | 02-25-2010 |
| 20100019396 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed. | 01-28-2010 |
| 20090170308 | METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE - A method for forming metal lines of a semiconductor device is disclosed. The metal line forming method includes forming plugs by perforating via-holes in an interlayer dielectric layer formed on a semiconductor substrate and burying a conductive material in the via-holes, sequentially forming at least two metal layers on the interlayer dielectric layer formed with the plugs, the metal layers having a difference in the size of metal grains of each metal layer, etching an uppermost first metal layer of the at least two metal layers using a photoresist pattern formed on the first metal layer as an etching mask using a first etching gas, and etching the partially etched first metal layer using a second etching gas. | 07-02-2009 |
| 20090170303 | METHODS FOR FORMING QUANTUM DOTS AND FORMING GATE USING THE QUANTUM DOTS - Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device comprising a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device. | 07-02-2009 |
| 20090170299 | FORMING A METAL CONTACT IN A SEMICONDUCTOR DEVICE - Methods for forming a metal contact in a semiconductor device. In one example embodiment, a method for forming a metal contact in a semiconductor device includes various steps. First, an interlayer insulating film is formed over a silicon substrate. Next, an insulating film is formed over the interlayer insulating film. Then, a photoresist pattern is formed on the insulating film. Next, the insulating film, the interlayer insulating film, and the silicon substrate are selectively etched using the photoresist pattern as an etch mask in order to form a contact trench. Then, the photoresist pattern is removed. Next, impurity ions are implanted into a region beneath the contact trench using the selectively-etched insulating film as a mask. Then, the selectively-etched insulating film and the contact trench are isotropically etched. Next, the contact trench is filled with a metal material. | 07-02-2009 |
| 20090170266 | METHOD FOR SIMULTANEOUSLY MANUFACTURING SEMICONDUCTOR DEVICES - Methods for manufacturing semiconductor devices simultaneously to implement low-voltage and high-voltage devices in a single chip. In one example embodiment, a method includes various acts. An isolation layer is formed on a wafer. A gate oxide layer and a lower gate poly are sequentially formed on a first low-voltage transistor region. A first poly oxide layer is formed. A nitride layer is formed on the first poly oxide layer. The nitride layer and the first poly oxide layer are etched. A field oxide layer is formed by selectively oxidizing portions exposed by the etching. A second poly oxide layer is formed. Gate patterns of each transistor region are completed by vapor-depositing an upper gate poly on a high-voltage transistor region, the first low-voltage transistor region and a second low-voltage transistor region. A source and drain region are formed. | 07-02-2009 |
| 20090167387 | DELAY-LOCKED LOOP FOR TIMING CONTROL AND DELAY METHOD THEREOF - A delay-locked loop for timing control, includes a voltage-controlled delay line that delays a reference clock to generate a multi-phase clock comprising a plurality of delayed phase clocks; and an up/down controller that receives one of the delayed phase clocks as a feedback clock and generates a frequency up/down control signal based on whether a rising edge of the feedback clock coincides with a falling edge of the reference clock. The delay-locked loop further includes a charge pump that charges or discharges a loop filter connected to the voltage-controlled delay line according to a frequency up/down control signal from the up/down controller; and a harmonic lock detector that compares phases of multiple ones of the delayed phase clocks with a phase of the reference clock, and operates such that the multi-phase clock is locked within a first cycle of the reference clock. | 07-02-2009 |
| 20090167340 | SEMICONDUCTOR CHIP TEST APPARATUS AND TESTING METHOD - A semiconductor chip test apparatus includes a plurality of power supply units, each supplying power to a semiconductor chip having a power input terminal, and a tester configured to measure an output current of at least one of the plurality of power supply units, and to generate a switching control signal when the measured output current is greater than a predetermined current. The semiconductor chip test apparatus also includes a plurality of relays each arranged between a common ground of the tester and a different ground of the semiconductor chip. Further, the semiconductor chip test apparatus includes a relay controller, such as a control bit generator, configured to selectively close one or more of the plurality of relays in response to the switching control signal from the tester. | 07-02-2009 |
| 20090167338 | TEST PATTERN FOR ANALYZING CAPACITANCE OF INTERCONNECTION LINE - Disclosed is a test pattern for analyzing capacitances of interconnection lines that accounts for parasitic capacitance components. The test pattern includes a first metal line having a comb-type structure including a plurality of tines, a second metal line having a comb-type structure including a plurality of tines engaged with the tines of the first metal line, a first probe pad switchably connected to the first metal line, and a second probe pad switchably connected to the second metal line. Switchable connections between the first metal line and the first probe pad and between the second metal line and the second probe pad may be provided by first and second switch terminals, respectively. The test pattern enables a capacitance measurement that accounts for parasitic capacitance components of pads and portions of interconnection lines leading from the pads, which otherwise interfere with accurate measurement of capacitances of the interconnection lines. | 07-02-2009 |
| 20090166869 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL INTERCONNECTION LAYER THEREOF - Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced. | 07-02-2009 |
| 20090166692 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A CMOS image sensor may include a dielectric layer formed on a semiconductor substrate, first and second passivation layers sequentially formed on the whole surface of the dielectric layer, a planarization layer, a color filter layer, and an overcoating layer and a microlens sequentially formed on the second passivation layer. The CMOS image sensor may further include a plurality of metal pads arranged on the dielectric layer to surround the microlens, a water barrier formed on the dielectric layer between the microlens and the metal pads, and first and second open parts exposing the metal pads and the water barrier. | 07-02-2009 |
| 20090166619 | TEST PATTERN OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a test pattern for a semiconductor device includes the steps of forming, on a semiconductor substrate, a moat mask pattern including plural moat lines patterned in a comb-shape and etching a portion of the semiconductor substrate exposed by the moat mask pattern, to form a trench. The method further includes gap-filling the trench with an insulation material to form a field separator, planarizing the semiconductor substrate having the field separator formed thereon, and forming a poly comb pattern on the planarized semiconductor substrate. The poly comb pattern is formed such that the moat lines are arranged between lines of the poly comb pattern. | 07-02-2009 |
| 20090166535 | TRANSMISSION ELECTRON MICROSCOPY ANALYSIS METHOD USING FOCUSED ION BEAM AND TRANSMISSION ELECTRON MICROSCOPY SAMPLE STRUCTURE - A TEM (transmission electron microscopy) analysis method using FIB (focused ion beam) includes dividing a TEM sample into a plurality of analysis regions; determining an FIB beam current for each of the analysis regions; and performing FIB milling on each of the analysis regions by using the determined FIB beam current. Further, the method includes loading the TEM sample onto a TEM sample grid and transmitting a TEM electron beam on the TEM sample to perform the TEM analysis. | 07-02-2009 |
| 20090160070 | METAL LINE IN A SEMICONDUCTOR DEVICE - A semiconductor having a metal line and a method of manufacturing a metal line in a semiconductor device is disclosed. In one example embodiment, a method of manufacturing a metal line in a semiconductor device includes various acts. A metal film for a metal line is formed on an interlayer dielectric layer of a semiconductor substrate. A silicon oxide hard mask film is formed on the metal film. A bottom anti-reflection (BARC) layer is formed on the hard mask film. The BARC layer, the hard mask film, and the metal film are selectively dry etched to form a metal line. | 06-25-2009 |
| 20090159941 | CMOS IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A complementary metal oxide silicon (CMOS) image sensor and a method for fabricating the same. In one example embodiment, a CMOS image sensor includes a substrate, a first dielectric film, a plurality of metal patterns, a second dielectric film, a plurality of via holes, a plurality of metal wires, a plurality of silicon oxide films, a plurality of trenches, and a plurality of photo diodes. The first dielectric film is formed on the substrate. The metal patterns are formed on the first dielectric film. The second dielectric film is formed on the first dielectric film and on the metal patterns. The via holes are formed through the second dielectric film. The metal wires are each formed in one of the via holes. The silicon oxide films are formed on the second dielectric film. The trenches are formed between the silicon oxide films. The photo diodes are formed in the trenches. | 06-25-2009 |
| 20090155975 | METHOD FOR MANUFACTURING METAL-INSULATOR-METAL CAPACITOR OF SEMICONDUCTOR DEVICE - A method for manufacturing a metal-insulator-metal capacitor of a semiconductor device method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a logic metal and a capacitor lower metal is formed on a first insulating film that is formed on a semiconductor substrate. Next, a portion of the capacitor lower metal is selectively etched to a predetermined depth. Then, a second insulating film is formed over an entire upper surface of the logic metal, the first insulating film, and the capacitor lower metal. Next, a capacitor upper metal is formed on the second insulating film in a region corresponding to the etched portion of the capacitor lower metal. Finally, a third insulating film is formed on an entire upper surface of the second insulating film and the capacitor upper metal. | 06-18-2009 |
| 20090142922 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a dielectric layer is formed on the whole surface of a semiconductor substrate that includes an upper surface of a transistor. Next, a trench and a contact hole are formed by etching the dielectric layer so that the upper surface of the transistor is exposed. Then, a contact is formed by embedding a first conductive layer in the contact hole. Next, an etching stop layer is selectively forming on an upper part of the contact. Then, the semiconductor device is blanket-etched such that the first conductive layer remains in the trench. Next, the etching stop layer is removed. Finally, a metal line is formed by embedding a second conductive layer in the trench. | 06-04-2009 |
| 20090142917 | METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE - Methods for fabricating a metal line of a semiconductor device are disclosed. In a disclosed example, the method includes a first step of forming a passivation film on a semiconductor substrate having a semiconductor device, a second step of forming contact holes in the passivation film to form a first contact plug, a third step of sequentially forming at least two metal layers on an entire surface of the substrate including the first contact plug, a fourth step of selectively etching one of the at least two metal layers to form a second contact plug, a fifth step of selectively etching the other of the at least two metal layers to form a metal line, and a sixth step of exposing an upper surface of the second contact plug. | 06-04-2009 |
| 20090142675 | RETICLE FOR OPTICAL PROXIMITY CORRECTION TEST PATTERN AND METHOD OF MANUFACTURING THE SAME - A reticle for an Optical Proximity Correction (OPC) test pattern and a method of manufacturing the same. In one example embodiment of the present invention, a reticle for an OPC test pattern includes test patterns formed apart from each other at regular intervals and dummy patterns for controlling a light transmission amount formed between the test patterns. The dummy patterns are formed apart from the test patterns at a predetermined interval. | 06-04-2009 |
| 20090140714 | START-UP CIRCUIT FOR GENERATING BANDGAP REFERENCE VOLTAGE - Disclosed is a start-up circuit that can stably and rapidly start up a bandgap reference voltage generating circuit when the bandgap reference voltage generating circuit is switched from a sleep mode to an operation mode, even if a difference in electrical characteristic, such as DC offset or the like, occurs due to, e.g, a physical difference between input transistors of an operational amplifier. | 06-04-2009 |
| 20090115023 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A capacitor of a semiconductor device and a method for manufacturing the same. In one example embodiment, a capacitor of a semiconductor device includes a first electrode, first dielectric layer, second electrode, second dielectric layer, and third electrode sequentially formed on a semiconductor substrate. The capacitor also includes a first contact coupled to the first electrode and to the third electrode. The capacitor further includes a second contact coupled to the second electrode. | 05-07-2009 |
| 20090101950 | CMOS IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A CMOS image sensor and a method for fabricating the same. In one example embodiment, a method for fabricating a CMOS image sensor includes various steps. First, an interlayer dielectric that includes a plurality of metal lines is formed on a semiconductor substrate that includes a photodiode. Next, a trench is formed in the interlayer dielectric. Then, a passivation layer is formed in the trench. Next, the trench is filled by vapor-depositing an additional dielectric layer on the passivation layer. Then, a color filter is formed on the additional dielectric layer. Next, a planarization layer is formed on the color filter. Finally, a micro lens is formed on the planarization layer. | 04-23-2009 |
| 20090098699 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device. In one example embodiment of the present invention, a method for manufacturing a semiconductor device includes various steps. First, a gate pattern is formed on a substrate. Next, a first oxide layer is formed on the gate pattern. Then, a second oxide layer, a first silicon nitride layer, and a second silicon nitride layer are sequentially formed over the substrate and the first oxide layer. Next, a first etching process is performed to remove horizontal portions of the first and second silicon nitride layers. Then, source/drain regions are formed in the substrate. Next, the vertical portions first and second silicon nitride layers are removed. Then, a third silicon nitride layer is formed over the second oxide layer. Finally, a second etching process is performed to remove horizontal portions of the third silicon nitride layer and the second oxide layer. | 04-16-2009 |
| 20090085218 | FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF - A flash memory device may include a first insulating layer on a base insulating layer on a substrate, a lower wire layer that fills a trench in the first insulating layer, a first insulating interlayer and a second insulating layer stacked in sequence on the first insulating layer and the lower wire layer, a middle wire layer that fills a trench in the second insulating layer, and a second insulating interlayer and an upper wire layer stacked in sequence on the middle wire layer, wherein the lower wire layer. The middle wire layer and the upper wire layer may be electrically connected to each other and the first insulating layer may include a low-k layer in contact with the base insulating layer. In addition, each of the first insulating interlayer, the second insulating layer, and the second insulating interlayer may include an FSG layer. | 04-02-2009 |
| 20090085078 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a pixel array including a photodiode, a peripheral region including a logic circuit, and an isolation region formed between the pixel array and the peripheral region and formed under the peripheral region to electrically isolate the pixel array from the peripheral region. | 04-02-2009 |
| 20090079013 | MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE TRANSISTOR - A MOS transistor and a method for manufacturing the transistor are disclosed. The method for manufacturing the MOS transistor may include successively stacking a pad oxide layer and a mask layer on a semiconductor substrate, patterning the pad oxide layer and the mask layer, to expose a trench forming region of the semiconductor substrate, forming a trench in the semiconductor substrate by etching the exposed trench forming region, and forming an anti-diffusion layer and an oxide layer over the entire surface of the semiconductor substrate including the trench. This method can reduce leakage current, among other things, resulting in improved characteristics of transistor products. | 03-26-2009 |
| 20090077509 | METHOD FOR CONTROLLING SHEET RESISTANCE OF POLY IN FABRICATION OF SEMICONDUCTOR DEVICE - A method for controlling the sheet resistance of poly in the fabrication of a semiconductor device. In one example embodiment, a method for controlling the sheet resistance of a poly in the fabrication of a semiconductor device includes various steps. First, detection is made whether or not an N-ion implantation area and a resistance area overlap with each other within the layout of a cell to be formed on a semiconductor wafer. Next, an LDD dummy area is generated in the area on the layout where the N-ion implantation area exists if such overlap is found. Then, detection is made whether or not a P-ion implantation area and a resistance area overlap with each other within the layout. Finally, an LDD dummy area is generated in the area on the layout where the P-ion implantation area exists if such overlap is found. | 03-19-2009 |
| 20090072299 | SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE MOS TRANSISTOR AND FABRICATION METHOD THEREOF - A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an opening in a high voltage region. An oxide layer is deposited over the substrate and anisotropically etched to remain only on sidewalls of the opening. A first gate oxide layer is formed on the substrate in the opening, and the nitride layer is removed. Then a second gate oxide layer is formed over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer. Gate electrodes are then formed in the high voltage region and the low voltage region. | 03-19-2009 |
| 20090066386 | MTCMOS FLIP-FLOP WITH RETENTION FUNCTION - There is provided a MTCMOS flip-flop configured to operate at high speed and to reduce leakage current while realizing a retention function in a sleep mode. The MTCMOS flip-flop may include a signal generator adapted to output an internal clock signal or a sleep mode control signal based on changes in a retention signal and an external clock signal, a master latch adapted to latch an input signal and to output a master latch output signal based on the internal clock signal, and a slave latch connected to an actual ground and adapted to latch the master latch signal, to output a slave latch output signal under control of the internal clock signal, and to maintain the latched signal under control of the sleep mode control signal in the sleep mode. | 03-12-2009 |
| 20090065863 | LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - In one example embodiment, an LDMOS device includes a first n-type well formed on a p-type substrate, a plurality of isolation layers formed in the first n-type well, a p-type ion implantation region formed on a surface of each of the isolation layers, and a gate selectively formed on the first n-type well and the isolation layers. | 03-12-2009 |
| 20090065858 | DMOS TRANSISTOR AND FABRICATION METHOD THEREOF - In one example embodiment, a method of fabricating a DMOS transistor includes various steps. First, a P-type well or an N-type well is formed on a semiconductor substrate by an impurity injection. Next, a drift region is formed on the portion of the semiconductor substrate in which the well region is formed by injecting conductive impurities reverse to those of the well region. Then, a trench for forming a gate on the semiconductor substrate is formed within the drift region. Next, a gate oxide and a gate electrode are formed in the trench. Finally, source/drain regions are formed by injecting the same conductive impurities as those of the drift region at both sides of the gate electrode. | 03-12-2009 |
| 20090065836 | SEMICONDUCTOR DEVICE HAVING MIM CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having an MIM capacitor and a method of manufacturing the same. In one example embodiment, a semiconductor device having an MIM capacitor includes a lower electrode including a pair of metal patterns spaced apart from each other, a dielectric formed so as to cover the surfaces of the spaced-apart metal patterns of the lower electrode, a metal plug formed on the dielectric, and an upper electrode made of a metal and formed on the metal plug. | 03-12-2009 |
| 20090061625 | LCD DRIVER IC AND METHOD FOR MANUFACTURING THE SAME - An LCD driver IC and a method for manufacturing the same. In one example embodiment, an LCD driver IC includes first and second main poly patterns formed separately from each other, a connection poly pattern connecting the main poly patterns, and a salicide blocking (SAB) pattern formed on the main poly patterns to block the main poly patterns. | 03-05-2009 |
| 20090057904 | COPPER METAL LINE IN SEMICONDCUTOR DEVICE AND METHOD OF FORMING SAME - A Cu line in a semiconductor device and method of forming same are disclosed. The method may include forming an insulating interlayer on a semiconductor substrate, forming a contact hole and a trench in the insulating interlayer in sequence, forming a short-circuit preventing layer on the insulating interlayer including the contact hole and the trench, forming a spacer on a sidewall of the trench by etching the short-circuit preventing layer, forming a Cu line layer over the semiconductor substrate including the contact hole and the trench, planarizing the Cu line layer by CMP, and forming a Cu-diffusion preventing capping layer over the semiconductor substrate including the Cu line layer. | 03-05-2009 |
| 20090029546 | METHOD FOR FORMING METAL LINES OF SEMICONDUCTOR DEVICE - Methods are disclosed for forming metal lines of a semiconductor device that can reduce interconnection or contact resistance, and can reduce defects in a barrier metal layer having a column structure. The method can include forming a first metal line on a semiconductor substrate, forming an insulating film on the first metal line, forming a contact hole in the insulating film, sequentially forming a barrier metal layer and a capping layer for protecting the barrier metal layer on an entire upper surface of the resultant substrate, oxidizing the capping layer to form a capping oxide film, depositing a contact metal material on the resultant substrate, planarizing the contact metal material to expose the insulating film, and forming a second metal line on the insulating film. | 01-29-2009 |
| 20090026617 | SEMICONDUCTOR DEVICE HAVING A COPPER METAL LINE AND METHOD OF FORMING THE SAME - A semiconductor device having a copper line and a method of forming the same so as to prevent a bridge phenomenon between neighboring upper lines are described. The method may include the steps of forming a capping layer and an intermetal dielectric layer in a stacked configuration over a substrate in which lower lines are formed, forming trenches defining an upper metal line region on the intermetal dielectric layer, and forming a spacer on inner sidewalls of the trenches. A via may then be formed under the exposed first trench using a photolithography process and the spacer for alignment. After removing the spacer, a barrier metal film may be formed on inner walls of the trenches and the via, a copper metal line film may be gap-filled within the trenches and the via, and a surface of the semiconductor device may be polished. | 01-29-2009 |
| 20090023273 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device comprising forming a transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate to cover the transistor, forming a passivation film on the interlayer insulating film, and annealing the semiconductor substrate having the passivation film in a gas atmosphere comprising at least one gas selected from the group of boron, silicon and hydrogen. | 01-22-2009 |
| 20090020881 | SEMICONDUCTOR DEVICE PACKAGE AND FABRICATING METHOD THEREOF - A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench. | 01-22-2009 |
| 20090020807 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a semiconductor device and a method for fabrication of the same. The fabrication method may include selectively forming an oxide layer pattern on a semiconductor substrate, forming an insulation layer pattern on the same substrate to cover edge portions of the oxide layer pattern, etching the oxide layer pattern and the substrate to form a recess as well as first and second oxide layer patterns corresponding to the edge portions of the oxide layer pattern, forming a third oxide layer pattern on the substrate in the recess to produce a gate insulation layer comprising the first, second, and third oxide layer patterns, and forming a gate pattern in the recess. The fabricated semiconductor device minimizes occurrence of current leakage such as gate induction drain leakage, among other things, thereby improving transistor performance. | 01-22-2009 |
| 20090020804 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same. The semiconductor device includes a gate pattern formed on a semiconductor substrate, a first impurity-doped region formed in the substrate on one side of the gate pattern and a second impurity-doped region formed in the substrate on the other side of the gate pattern, a salicide shielding film pattern partially covering either the first impurity-doped region or the second impurity-doped region, an insulating film formed on the semiconductor substrate, the insulating film including a first hole which exposes the salicide shielding film pattern, and a second hole which partially exposes the first impurity-doped region or the second impurity-doped region that is not covered by the salicide shielding film pattern, and a first line coming in contact with the salicide shielding film pattern through the first hole. | 01-22-2009 |
| 20090004770 | METHOD FOR MANUFACTURING VERTICAL CMOS IMAGE SENSOR - A method for manufacturing a vertical CMOS image sensor related to a semiconductor device is disclosed. A high-temperature double annealing process and/or an additional passivation nitride film are selectively applied in order to improve dark leakage characteristics and also to prevent or reduce an incidence of circular defects, thereby enhancing the quality and reliability of the vertical CMOS image sensor. | 01-01-2009 |
| 20090004769 | METHOD FOR MANUFACTURING IMAGE SENSOR - A method for manufacturing an image sensor is disclosed. The manufacturing method includes forming a unit pixel including a photodiode and a gate on a semiconductor substrate, forming an interlayer insulating layer on the semiconductor substrate including the unit pixel, planarizing the interlayer insulating layer, forming a protection layer with SiH | 01-01-2009 |
| 20090001446 | FLASH MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A method of fabricating a flash memory device includes forming a stack electrode on a semiconductor substrate; forming a side spacer on a side wall of the stack electrode; forming a photo-resist film pattern with a predetermined thickness on the side wall of the side spacer; and forming a source/drain junction on the semiconductor substrate through ion implant using the photo-resist film as a mask for ion implant. | 01-01-2009 |
| 20080316607 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor and a method of manufacturing the same. In one example embodiment, an image sensor includes an interlayer insulation layer formed on a substrate of a pixel area, a plurality of first microlenses spaced apart from each other on the interlayer insulation layer, and a plurality of second microlenses formed beside the plurality of first microlenses. The plurality of second microlenses each has a diameter different from a diameter of each of the plurality of first microlenses. | 12-25-2008 |
| 20080315314 | SEMICONDUCTOR DEVICE HAVING A DUAL GATE ELECTRODE AND METHODS OF MAKING THE SAME - Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by making the two gate electrodes have a different thickness and material state in a manner that one of the two gate electrodes has a single-layer structure and the other one has a two-layer structure. | 12-25-2008 |
| 20080315271 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - Disclosed are an image sensor and a method for fabricating the same. The method may include forming a gate, a photo diode, and a floating diffusion region on a pixel region of a semiconductor substrate; forming an oxide film on the pixel region and on an edge region of the semiconductor substrate; forming a sacrificial oxide layer by etching the oxide film using a photoresist pattern as a mask; forming a metal layer on the photoresist pattern, the gate, and the floating diffusion region; forming a salicide layer on the gate and the floating diffusion region; etching a remaining non-salicided portion of the metal layer, the photoresist pattern, and at least a portion of the sacrificial oxide layer; and forming an interlayer insulating film on the semiconductor substrate and planarizing the interlayer insulating film. | 12-25-2008 |
| 20080311731 | LOW PRESSURE CHEMICAL VAPOR DEPOSITION OF POLYSILICON ON A WAFER - Low pressure chemical vapor deposition (LPCVD) of polysilicon on a wafer in a manner that reduces the generation of particles during the deposition process. In one example embodiment, a method of LPCVD of polysilicon on a wafer positioned in a process tube includes various steps. First, introducing a particle inhibitor is introduced into the process tube. Next, a silicon source gas is introduced into the process tube. Finally, a doping gas is introduced into the process tube, resulting in the formation of a polysilicon film of a uniform thickness on the wafer. | 12-18-2008 |
| 20080308905 | SEMI-CONDUCTOR DEVICE, AND METHOD OF MAKING THE SAME - A semiconductor device and a method for manufacturing the device are disclosed. The device, and the method for making the device, includes the steps of forming a gate oxide film on a semiconductor substrate; forming a gate poly silicon layer on the gate oxide film; and implanting deuterium ions over the semiconductor substrate including the gate poly silicon layer. | 12-18-2008 |
| 20080299682 | METHOD FOR REMOVING POLY SILICON - Methods for removing poly silicon. In one example embodiment, a method for removing poly silicon that is formed on a silicon wafer includes the steps of growing the poly silicon as a silicon oxide through a thermal oxidation process and removing the silicon oxide using an etching solution. | 12-04-2008 |
| 20080293227 | METHOD FOR FORMING GATE ELECTRODE OF SEMICONDUCTOR DEVICE - Provided is a method for forming a gate electrode of a semiconductor device which can form a gate electrode having a fine line width. Disclosed method steps include forming a gate oxide film, a polysilicon film for a gate electrode, and a first sacrificial layer on the entire surface of a semiconductor substrate and then forming an opening within the first sacrificial layer. The effective width of the hole is reduced, and an ion implantation layer is formed on the top surface of the polysilicon film in the region exposed through the hole. A gate electrode is formed under the ion implantation layer by using the ion implantation layer as a mask. | 11-27-2008 |
| 20080290447 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A method of making a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) device by a process of growing Meta-stable poly silicon (MPS) regions is provided. Meta-stable poly silicon (MPS) regions are formed in the active region of a semiconductor substrate, dielectric materials are formed on the MPS regions, and control gates are formed on parts of the dielectric materials. | 11-27-2008 |
| 20080286962 | METHOD FOR FABRICATING METAL PAD - A method for fabricating a metal pad is disclosed. The fabrication method includes the step of selectively etching a wire insulation film formed on a semiconductor substrate to form a pattern, such as a dual damascene pattern, having plural vias in one trench. A metal film is deposited to fill the pattern and an insulation film is formed on the metal film. Further, the method includes removing the insulation film and the metal film to expose a surface of the wire insulation film to thereby form a metal pad and via contacts. | 11-20-2008 |
| 20080286923 | METHOD FOR FABRICATING FLASH MEMORY - A method for fabricating a flash memory device is disclosed that can improve the reliability of the device by counteracting against the generation of charge traps induced by interfacial damage of an oxide film during the formation of spacers. The method may comprise forming spacers comprised of an oxide film and a nitride film, nitriding an interface of the oxide film after removal of the nitride film; and forming a salicide film after formation of an insulating film on a sidewall of the nitrided oxide film. | 11-20-2008 |
| 20080286922 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one example embodiment, a method of fabricating a semiconductor device includes various steps. First, an isolation film is formed on a semiconductor substrate to define a field region and an active region. Then, a stack gate structure is formed. Next, a first photoresist and a second photoresist are sequentially formed on the stack gate structure. Then, a patterning process is performed to remove the second photoresist in a source line region. Next, a patterning process is performed to remove the first photoresist in the source line region, to thereby expose the isolation film. Then, the exposed isolation film is removed to expose the semiconductor substrate in the source line region. Finally, a cell source ion implantation process is performed using the patterned second photoresist as an ion injection mask to form a source line having impurity ions implanted thereto in the semiconductor substrate of the source line region. | 11-20-2008 |
| 20080285204 | ELECTROSTATIC CHUCK STRUCTURE FOR SEMICONDUCTOR MANUFACTURING APPARATUS - An electrostatic chuck structure according to example embodiments of the present invention may include at least one specific region of a conductor having a thickness relatively smaller than those of other regions, at least one specific region of a dielectric having a thickness relatively larger than those of other regions, or at least one specific region of a conductor having a thickness relatively smaller than those of other regions and at least one specific region of a dielectric having a thickness relatively larger than those of other regions. Therefore, etching rate and CD uniformity can be improved during a semiconductor manufacturing process. | 11-20-2008 |
| 20080278829 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same. The method includes setting a pattern region, forming a series of virtual mesh lines on the pattern region, forming a plurality of patterns in the pattern region, and substituting each of the patterns with either a red (R), green (G), or blue (B) patterns in accordance with a contact rule between the virtual mesh lines. Accordingly, it is possible to enhance the pattern uniformity between a main pattern region and a dummy pattern region, and thus to secure a uniform critical dimension (CD) of each pattern. Also, the patterning process for the color filter can be automatized to minimize the amount of data required to design a pattern. Also, the designing and manufacturing processes can be simplified, meaning that they can be more rapidly and precisely achieved. | 11-13-2008 |
| 20080206567 | Plastic Conductive Particles and Manufacturing Method Thereof - Plastic conductive particles having an outer diameter of 2.5 μm˜1 mm obtained by sequentially plating a 0.1˜10 μm thick metal plating layer and a 1˜100 μm thick Pb solder layer or a Pb-free solder layer on plastic core beads having a high elastic modulus of compression, and a method of manufacturing thereof. The method of manufacturing the plastic conductive particles includes preparing plastic core beads having excellent thermal properties and a high elastic modulus of compression, etching surfaces of the plastic core beads for surface treatment thereof, forming a metal plating layer via electroless plating to improve adhesion between the bead surface and the metal plating layer, and then forming a solder layer such that a sealed hexagonal barrel is immersed in an electroplating solution and then an electroplating process is conducted using a mesh barrel rotating 360° at 6˜10 rpm or a mesh barrel having a structure in which one surface of a conventional sealed hexagonal barrel is open, and rotating 200° in right and left directions at 1˜5 rpm, to manufacture plastic conductive particles having a size of 1 mm or less. The plastic conductive particles of this invention enable the maintenance of packaging gaps, and thus can be applied to IC packaging, LCD packaging and other conductive materials. | 08-28-2008 |
