DENSBITS TECHNOLOGIES LTD.
|DENSBITS TECHNOLOGIES LTD. Patent applications|
|Patent application number||Title||Published|
|20130339586||METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME - A method for programming data into a first plurality of rows within a second plurality of erase sectors of a flash memory device using a programming process having at least one selectable parameter, the method includes characterizing each of at least one row subsets, each row subset comprising at least one row from among said first plurality of rows, thereby to generate at least one row subset characteristic value; and programming data into at least a portion of at least one individual row belonging to at least one row subset, using a programming process having at least one selectable parameter, said at least one selectable parameter being set at least partly in accordance with the row subset characteristic value characterizing a row subset to which said individual row belongs; wherein at least two row subsets of an array of flash memory cells differ from each other by their row subset characteristic values.||12-19-2013|
|20130227207||ADVANCED MANAGEMENT OF A NON-VOLATILE MEMORY - A method of managing a non-volatile memory device, the method comprising: receiving data sectors; writing each data sector into a data block that is allocated to a memory space subset that is associated with the data sector; wherein the data block belongs to a buffer of the non-volatile memory device; maintaining a management data structure that comprises location metadata about a location of each data sector in the buffer; and merging, if a criterion is fulfilled and before the buffer becomes full, data sectors stored at different data blocks and belong to a same set of logical memory blocks into a sequential portion of the non-volatile memory device, wherein the sequential portion differs from the buffer.||08-29-2013|
|20130212316||CONFIGURABLE FLASH INTERFACE - A flash memory controller, a non-transitory computer readable medium and a method for performing operations with a flash memory device, the method may include receiving, by a flash memory controller, a request to perform a requested operation with the flash memory device; selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation.||08-15-2013|
|20130212315||STATE RESPONSIVEOPERATIONS RELATING TO FLASH MEMORY CELLS - A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state.||08-15-2013|
|20120311233||SYSTEM AND METHOD FOR MANAGING A NON-VOLATILE MEMORY - A method, computer readable medium storing instructions and system for managing flash memory. Data sector are received and each is written into a data block of a buffer of a non-volatile memory device. Pointers in a data management structure are created for each data sector corresponding to an associated logical block and a storage location of the data sector in the buffer. When a predefined criterion is fulfilled before the buffer becomes full, a number of logical blocks to be merged is determined and data sectors corresponding to the number of logical blocks to be merged are written from the buffer to a primary non-volatile data storage memory of the non-volatile memory device.||12-06-2012|
|20120236638||OBTAINING SOFT INFORMATION USING A HARD INTERFACE - A flash memory controller, a computer readable medium and a method for generating reliability information using a hard information interface, the method may include performing multiple read attempts, while using the hard information interface, of a plurality of flash memory cells to provide multiple read results; wherein each flash memory cell is read by providing a reference voltage to the flash memory cell; wherein a same reference voltage is provided during the multiple read attempts; and generating, for each flash memory cell, reliability information based upon multiple read results of the flash memory cell.||09-20-2012|
|20120216085||DEVICES AND METHOD FOR WEAR ESTIMATION BASED MEMORY MANAGEMENT - A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process.||08-23-2012|
|20120144093||INTERLEAVING CODEWORD PORTIONS BETWEEN MULTIPLE PLANES AND/OR DIES OF A FLASH MEMORY DEVICE - A system, a method and non-transitory computer readable medium storing instructions for interleaving at least two portions of a first codeword of the group between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule and interleaving different portions of other codewords of the group between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule.||06-07-2012|
|20120110250||MEETHOD, SYSTEM AND COMPUTER READABLE MEDIUM FOR COPY BACK - Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device.||05-03-2012|
|20120066441||SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS - A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.||03-15-2012|
|20100131580||APPARATUS AND METHODS FOR HARDWARE-EFFICIENT UNBIASED ROUNDING - A system and method for unbiased rounding away from, or toward, zero comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M−N bit number, and apparatus for adding the equivalent value of ‘½’ to the M−N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½.||05-27-2010|
Patent applications by DENSBITS TECHNOLOGIES LTD.