| Custom One Design, Inc Patent applications |
| Patent application number | Title | Published |
|---|
| 20090273392 | METHODS AND APPARATUS FOR REDUCING NON-IDEAL EFFECTS IN CORRELATED DOUBLE SAMPLING COMPENSATED CIRCUITS - Embodiments of the present invention address kT/C noise, sampled high frequency operational amplifier noise, and charge injection errors sampled on switching capacitors and introduced due to internal switching. Correlated double sampling compensates for DC offset and low frequency operational amplifier noise, and the use of fake integration and a capacitor divider eliminate or significantly reduce kT/C noise, sampled high frequency operational amplifier noise, and charge injection errors. | 11-05-2009 |
| 20090273386 | APPARATUS FOR CURRENT-TO-VOLTAGE INTEGRATION FOR CURRENT-TO-DIGITAL CONVERTER - Methods and apparatus for improved current-to-voltage integrators reducing charge injection and kT/C errors from capacitor switching and intrinsic operational amplifier noise (i.e., offset, 1/f noise, thermal noise) during the reset cycle of the integrator, simultaneously reducing demands on the reference voltage source, using correlated double sampling to compensate for DC offset and low frequency op-amp noises, and “fake” integration and a capacitor divider to eliminate or significantly reduce kT/C noise and charge injection. | 11-05-2009 |
