CSMC TECHNOLOGIES FAB1 CO., LTD.
|CSMC TECHNOLOGIES FAB1 CO., LTD. Patent applications|
|Patent application number||Title||Published|
|20140329385||METHOD FOR MANUFACTURING SEMICONDUCTOR THICK METAL STRUCTURE - A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N||11-06-2014|
|20140231893||CAPACITOR AND PREPARATION METHOD THEREOF - A capacitor and a method of fabricating thereof are provided. A structure of low pressure tetraethyl orthosilicate-low pressure silicon nitride-low pressure tetraethyl orthosilicate is used in the capacitor to replace the oxide-nitride-oxide structure of the existing capacitor; the capacitor has a relatively high unit capacitance value. Furthermore, the structure of low pressure tetraethyl orthosilicate—low pressure silicon nitride—low pressure tetraethyl orthosilicate is fabricaited by low pressure chemical vapor deposition method at relatively low temperature; thus the heat produced in the whole process is relatively low, which is insufficient to make the semiconductor device shift or make the gate metal layer or the metallized silicon layer peel off. Accordingly, the capacitor and the method of fabricating the capacitor of the present invention can be well applied in the process of the 0.5 μm PIP capacitor or below 0.5 μm.||08-21-2014|
|20140167045||TEST PATTERN FOR TRENCH POLY OVER-ETCHED STEP AND FORMATION METHOD THEREOF - A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (||06-19-2014|
|20140147980||METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to the technical field of semiconductor manufacturing. A method for manufacturing a semiconductor device is disclosed, which solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The embodiment of the present invention is applicable to a BCD process and the like.||05-29-2014|
|20140145290||HIGH-VOLTAGE SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF - A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.||05-29-2014|
|20130196489||METHOD FOR MANUFACTURING DEEP-TRENCH SUPER PN JUNCTIONS - The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.||08-01-2013|
|20130113052||METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel. The gate region is formed on the channel and the gate oxide layer; the source region is formed in the first shallow channel region and vertically extends into the well region under the first shallow channel region; and the drain region is formed in the second shallow channel region and vertically extends into the well region under the second shallow channel region.||05-09-2013|
|20130099755||LITHIUM BATTERY PROTECTION CIRCUITRY - A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit. The logic circuit has a first logic output and a second logic output. The lithium battery protection circuit also includes a level shift circuit coupled to the logic circuit through the first logic output and the second logic output, and the level shift circuit is configured to convert the first logic output and the second logic output to high voltage levels in an over-charge protection state. Further, the lithium battery protection circuit includes a substrate switching circuit coupled to the level shift circuit and a power transistor coupled between a negative end of the lithium battery and an external circuit negative electrode. The level shift circuit includes a first inverter coupled to the second logic output, a plurality of PMOS transistors, at least one of which has high source-drain voltage and low gate-source voltage, and a plurality of NMOS transistors, at least one of which is a low-voltage NMOS transistor.||04-25-2013|
|20130037878||VDMOS DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating VDMOS devices includes providing a semiconductor substrate; forming a first N-type epitaxial layer on the semiconductor substrate; forming a hard mask layer with an opening on the first N-type epitaxial layer; etching the first N-type epitaxial layer along the opening until the semiconductor substrate is exposed, to form P-type barrier figures; forming a P-type barrier layer in the P-type barrier figures, the P-type barrier layer having a same thickness as that of the first N-type epitaxial layer; removing the hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate on the second N-type epitaxial layer; forming a source in the second N-type epitaxial layer on both side of the gate; and forming a drain on the back of the semiconductor substrate relative to the gate and the source.||02-14-2013|
|20120178230||METHOD FOR FABRICATING TRENCH DMOS TRANSISTOR - A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and forming a metal silicide layer on the diffusion layer and the trench gate. Effective result of the present invention is achieved with lower cost and improved efficiency of fabrication.||07-12-2012|
Patent applications by CSMC TECHNOLOGIES FAB1 CO., LTD.