Cryptography Research, Inc. Patent applications |
Patent application number | Title | Published |
20160140274 | ENERGY ANALYSIS FOR DIFFERENTIAL POWER ANALYSIS RESISTANCE - A first and second set of simulation information of a circuit design may be received. Energy consumption values associated with signals may be calculated for each of the first and second sets of simulation information of the circuit design. The energy consumption values associated with the transitions of the plurality of signals for each time point of a plurality of time points may be aggregated based on when each of the transitions of the signals occurs for each of the first and second sets of simulation information. Furthermore, a possible Differential Power Analysis (DPA) leak may be identified at one of the time points based on a difference in aggregated energy consumption values between the first and second sets of simulation information. | 05-19-2016 |
20150178478 | PROTECTING MEDIA ITEMS USING A MEDIA SECURITY CONTROLLER - A media storage device includes a media security controller and a memory to store data that relates to a media item to be rendered by a rendering device. The media security controller sends a message in response to the rendering device reading an authorization file. The message being for the rendering device to read a portion of data from the memory and to provide the portion of data to the media security controller. The media security controller receives the portion of the data from the rendering device, trans forms the portion of the data, and sends the transformed portion of the data to the rendering device. | 06-25-2015 |
20150052368 | DIFFERENTIAL POWER ANALYSIS - RESISTANT CRYPTOGRAPHIC PROCESSING - Information leaked from smart cards and other tamper resistant cryptographic devices can be statistically analyzed to determine keys or other secret data. A data collection and analysis system is configured with an analog-to-digital converter connected to measure the device's consumption of electrical power, or some other property of the target device, that varies during the device's processing. As the target device performs cryptographic operations, data from the A/D converter are recorded for each cryptographic operation. The stored data are then processed using statistical analysis, yielding the entire key, or partial information about the key that can be used to accelerate a brute force search or other attack. | 02-19-2015 |
20140359755 | CONFIGURATOR FOR SECURE FEATURE AND KEY MANAGER - A computing device receives a feature name or key name for an integrated circuit comprising a security manager core and an additional component. At least one of a) the additional component is associated with the key name or b) a feature provided by the additional component is associated with the feature name. The computing device receives a specified number of bits associated with the feature name or the key name, and maps the feature name to a feature address space or the key name to a key interface of the security manager core based at on the specified number of bits. The computing device generates at least one hardware description logic (HDL) module based on the mapping, wherein the at least one HDL module is usable to configure the security manager core for delivery of payloads associated with the feature name or the key name to the additional component. | 12-04-2014 |
20140247944 | CRYPTOGRAPHIC DEVICE WITH RESISTANCE TO DIFFERENTIAL POWER ANALYSIS AND OTHER EXTERNAL MONITORING ATTACKS - Techniques usable by devices to encrypt and decrypt sensitive data to in a manner that provides security from external monitoring attacks. The encrypting device has access to a base secret cryptographic value (key) that is also known to the decrypting device. The sensitive data are decomposed into segments, and each segment is encrypted with a separate encryption key derived from the base key and a message identifier to create a set of encrypted segments. The encrypting device uses the base secret cryptographic value to create validators that prove that the encrypted segments for this message identifier were created by a device with access to the base key. The decrypting device, upon receiving an encrypted segments and validator(s), uses the validator to verify the message identifier and that the encrypted segment are unmodified, then uses a cryptographic key derived from the base key and message identifier to decrypt the segments. | 09-04-2014 |
20140044265 | SECURE FEATURE AND KEY MANAGEMENT IN INTEGRATED CIRCUITS - A mechanism for providing secure feature and key management in integrated circuits is described. An example integrated circuit includes a secure memory to store a secret key, and a security manager core, coupled to the secure memory, to receive a digitally signed command, verify a signature associated with the command using the secret key, and configure operation of the integrated circuit using the command. | 02-13-2014 |