| COMISSARIAT A L'ENERGIE ATOMIQUE Patent applications |
| Patent application number | Title | Published |
|---|
| 20110006263 | METHOD FOR MAKING HIGHLY EXFOLIATED VERMICULITE WITHOUT USING ANY ORGANIC BINDER OR ADDITIVE FOR FORMING THE SAME - A method for preparing an exfoliated vermiculite, comprising the following steps: (a) a step of heating a non-exfoliated hydrated vermiculite at a temperature extending from 400 to 600° C. for a period extending from 3 hours to 7 hours, in this way generating a dehydrated vermiculite; and (b) a step of contacting the dehydrated vermiculite with a solution containing an intercalating agent capable of decomposing while generating gases. | 01-13-2011 |
| 20100141612 | ELECTRODE OF A LIGHT-EMITTING DEVICE OF THE OLED TYPE - An electrode of a light-emitting device of the OLED type adapted for forming with a second electrode, an optical cavity, including at least one layer based on a material of refraction index n | 06-10-2010 |
| 20100123222 | PROCESS FOR FABRICATING A CHARGE STORAGE LAYER OF A MEMORY CELL - A process for fabricating a charge storage layer comprising metal particles of a memory cell, said layer consisting of an organic layer comprising, on the surface, said metal particles, said process comprising the following steps: (a) a step of grafting, onto a metallic, semiconductor or electrically insulating substrate, an organic layer comprising, on the surface, groups capable of complexing at least one metallic element in cationic form; (b) a step of bringing said layer into contact with a solution comprising said metallic element in cationic form, by means of which said metallic element is complexed by said abovementioned groups; and (c) a step of reducing said complexed metallic element to the metallic element in oxidation state 0, by means of which metal particles are obtained. | 05-20-2010 |
| 20090311834 | SOI TRANSISTOR WITH SELF-ALIGNED GROUND PLANE AND GATE AND BURIED OXIDE OF VARIABLE THICKNESS - Method for making a transistor with self-aligned gate and ground plane, comprising the steps of:
| 12-17-2009 |
| 20090127460 | HIGH TIME-RESOLUTION ULTRASENSITIVE OPTICAL SENSOR USING A PLANAR WAVEGUIDE LEAKAGE MODE, AND METHODS FOR MAKING SAME - A high time-resolution ultrasensitive optical detector, using a planar waveguide leakage mode, and methods for making the detector. The detector includes a stacking with a dielectric substrate, a detection element, first and second dielectric layers, and a dielectric superstrate configured to send photon(s) into the light guide formed by the first layer. The thicknesses of the layers is chosen to enable a resonant coupling between the photon(s) and a leakage mode of the guide, the stacking having an absorption resonance linked to the leakage mode for a given polarization of the photon(s). | 05-21-2009 |
