| COGNITIVE ELECTRONICS, INC. Patent applications |
| Patent application number | Title | Published |
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| 20100241938 | SYSTEM AND METHOD FOR ACHIEVING IMPROVED ACCURACY FROM EFFICIENT COMPUTER ARCHITECTURES - This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function. Alternatively a plurality of SIMD can be used to alternately conduct low-precision computations for a predetermined number of operations and high-precision operations on a fewer number of operations. In an embodiment, aggregation can include summing values within predetermined ranges of orders of magnitude, via an adding tree arrangement, so that significant digits therebetween are preserved. | 09-23-2010 |
| 20090083263 | PARALLEL PROCESSING COMPUTER SYSTEMS WITH REDUCED POWER CONSUMPTION AND METHODS FOR PROVIDING THE SAME - This invention provides a computer system architecture and method for providing the same which can include a web page search node including a web page collection. The system and method can also include a web server configured to receive, from a given user via a web browser, a search query including keywords. The node is caused to search pages in its own collection that best match the search query. A search page returner may be provided which is configured to return, to the user, high ranked pages. The node may include a power-efficiency-enhanced processing subsystem, which includes M processors. The M processors are configured to emulate N virtual processors, and they are configured to limit a virtual processor memory access rate at which each of the N virtual processors accesses memory. The memory accessed by each of the N virtual processors may be RAM. In select embodiments, the memory accessed by each of the N virtual processors includes DRAM having a high capacity yet lower power consumption then SRAM. | 03-26-2009 |
