Carsem (M) Sdn. Bhd. Patent applications |
Patent application number | Title | Published |
20150087087 | COLOR YIELD OF WHITE LEDS - A method of disposing a phosphor material on an LED such that the LED emits white light and adjusting the quantity of phosphor material such that the white light meets a color target. A formulated procedure is used to determine the adjustment required, and includes a correlation between a change in position of a color of an LED on a CIE diagram and a known quantity of phosphor material added to the LED. | 03-26-2015 |
20140021491 | MULTI-COMPOUND MOLDING - In certain embodiments, a semiconductor package includes a leadframe, a light emitter die disposed on the leadframe, and a light detector die disposed on the leadframe adjacent to the light emitter die. In some embodiments, a first transparent molding compound is disposed over the light emitter die and a second transparent molding compound is disposed over the light detector die. The first and second transparent molding compound may be disposed such that a space between them forms a cavity between the die and above the leadframe. In other embodiments a transparent molding compound is disposed simultaneously over the light emitter and light detector die and a subsequent material removal process forms a cavity within the compound between the die. In both embodiments, an opaque molding compound is disposed in the cavity between the die, and is configured to block optical cross-talk between the light emitter and light detector die. | 01-23-2014 |
20130328194 | SHORT AND LOW LOOP WIRE BONDING - A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink. | 12-12-2013 |
20130221382 | MANUFACTURING LIGHT EMITTING DIODE (LED) PACKAGES - A method of manufacturing an LED package includes mounting a large panel frame/substrate (LPF/S) having a substantially square shape to a ring. The LPF/S includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. Each of the die pads includes a planar chip attach surface. An LED chip is attached to the planar chip attach surface of each of the die pads. An encapsulant material is applied overlaying the LED chips and at least a part of the LPF/S. Each die pad and corresponding leads are separated from the LPF/S to form individual LED packages. The steps of attaching the LED chips and applying the encapsulant material are performed while the LPF/S is mounted to the ring. | 08-29-2013 |
20130200503 | PROTECTIVE LAYERS IN SEMICONDUCTOR PACKAGING - A semiconductor package includes a semiconductor die having an upper surface with bond pads thereon. A plurality of leads surround sides of the semiconductor die. Bonding wires couple each of the bond pads to a corresponding one of the plurality of leads. An encapsulant covers the upper surface and the sides of the semiconductor die and the bonding wires. The encapsulant also covers a portion of a top of each of the plurality of leads and sides of the plurality of leads that are nearest the semiconductor die. A bottom of each of the plurality of leads and the sides of the plurality of leads that are farthest from the semiconductor die are exposed outside the encapsulant. A protective film covers a lower surface of the semiconductor die and has a bottom that is substantially coextensive with the bottom of each of the plurality of leads. | 08-08-2013 |
20130109137 | LARGE PANEL LEADFRAME | 05-02-2013 |
20130062765 | LOW LOOP WIRE BONDING - A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die. | 03-14-2013 |
20120107974 | MANUFACTURING LIGHT EMITTING DIODE (LED) PACKAGES - A method of manufacturing an LED package includes mounting a large panel frame/substrate (LPF/S) having a substantially square shape to a ring. The LPF/S includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. Each of the die pads includes a planar chip attach surface. An LED chip is attached to the planar chip attach surface of each of the die pads. An encapsulant material is applied overlaying the LED chips and at least a part of the LPF/S. Each die pad and corresponding leads are separated from the LPF/S to form individual LED packages. The steps of attaching the LED chips and applying the encapsulant material are performed while the LPF/S is mounted to the ring. | 05-03-2012 |
20120104421 | LEADFRAME PACKAGE WITH RECESSED CAVITY FOR LED - An LED package includes a die pad having a bottom surface, an upper surface and a centrally located recessed cavity. The recessed cavity has a chip attach surface between the bottom surface and upper surface and sidewalls that extend from the recessed chip attach surface to the upper surface. The package additionally has leads arranged on opposing sides of the die pad. The leads have a bottom surface that is coextensive with the bottom surface of the die pad and an upper surface coextensive with the upper surface of the die pad. An LED chip is attached to the chip attach surface. The package further includes a package body having an encapsulant which fills space between the die pad and leads forming a bottom encapsulant surface that is coextensive with the bottom surfaces of the die pad and leads. | 05-03-2012 |
20120043655 | WAFER-LEVEL PACKAGE USING STUD BUMP COATED WITH SOLDER - A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed. | 02-23-2012 |
20100102444 | WAFER LEVEL PACKAGE USING STUD BUMP COATED WITH SOLDER - A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed. | 04-29-2010 |
20080286901 | Method of Making Integrated Circuit Package with Transparent Encapsulant - A method for making an IC package with transparent encapsulant includes providing a leadframe, where the leadframe includes a first die pad and a second die pad, disposing a first die on the first die pad and a second die on the second die pad, forming a cavity on the leadframe, where the cavity includes the first die pad and the second die pad, injecting an encapsulant material into the cavity and cutting the injected encapsulant material and the leadframe to form a first IC package and a second IC package. The encapsulant material is transparent for visible wavelengths. The injection of the encapsulant material is performed at an encapsulant temperature ranging from 140° C. to 160° C. | 11-20-2008 |