CANDELA MICROSYSTEMS, INC. Patent applications |
Patent application number | Title | Published |
20120008375 | CMOS IMAGE SENSOR WITH NOISE CANCELLATION - A memory comprises a two dimensional array of memory cells. Each memory cell comprises a first transistor, a second transistor and a capacitor. A multi-bit datum is stored as one of a plurality of voltage signal levels driven over a vertical input signal line and further across a source and a drain of the first transistor to be stored onto a gate of the second transistor. The first transistor is selected by a horizontal WR control line. The gate of the second transistor is connected to a first terminal of the capacitor. A second terminal of the capacitor is connected to a horizontal RD control line. The RD control line is driven to couple the second transistor to drive a signal onto a vertical output signal line during a read of the stored signal on the gate. | 01-12-2012 |
20100002112 | CMOS IMAGE SENSOR WITH NOISE CANCELLATION - An image sensor having one or more pixels within a pixel array. A vertical signal line across the pixel array conductively connects to a drain terminal of a transistor of one of the pixels. The drain terminal is driven to a first drain voltage via the vertical signal line so that the transistor enters a triode region. A gate of the transistor is placed into a tri-state during the triode region, the gate being at a first gate voltage prior to the tri-state. The drain terminal is driven to a second drain voltage during the tri-state, whereby the gate is capacitively coupled to a second gate voltage. The second drain voltage may be higher than the first drain voltage so as to effectuate a gate voltage boosting for the transistor. The transistor may be a reset transistor having a drain terminal conductively coupled to reset said photodetector. | 01-07-2010 |