| BITMICRO NETWORKS, INC. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110161568 | MULTILEVEL MEMORY BUS SYSTEM FOR SOLID-STATE MASS STORAGE - The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these. | 06-30-2011 |
| 20110113186 | REDUCING ERASE CYCLES IN AN ELECTRONIC STORAGE DEVICE THAT USES AT LEAST ONE ERASE-LIMITED MEMORY DEVICE - A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed. | 05-12-2011 |
| 20100095053 | HYBRID MULTI-TIERED CACHING STORAGE SYSTEM - A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution. | 04-15-2010 |
| 20090077306 | OPTIMIZING MEMORY OPERATIONS IN AN ELECTRONIC STORAGE DEVICE - To optimize memory operations, a mapping table may be used that includes: logical fields representing a plurality of LBA sets, including first and second logical fields for representing respectively first and second LBA sets, the first and second LBA sets each representing a consecutive LBA set; PBA fields representing PBAs, including a first PBA disposed for representing a first access parameter set and a second PBA disposed for representing a second access parameter set, each PBA associated with a physical memory location in a memory store, and these logical fields and PBA fields disposed to associate the first and second LBA sets with the first and second PBAs; and, upon receiving an I/O transaction request associated with the first and second LBA sets, the mapping table causes optimized memory operations to be performed on memory locations respectively associated with the first and second PBAs. | 03-19-2009 |
