BANDGAP ENGINEERING, INC.
|BANDGAP ENGINEERING, INC. Patent applications|
|Patent application number||Title||Published|
|20140252564||Process for Structuring Silicon - A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H||09-11-2014|
|20130247966||Nanostructured devices - A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon.||09-26-2013|
|20130099345||ELECTRICAL CONTACTS TO NANOSTRUCTURED AREAS - A process is provided for contacting a nanostructured surface. In that process, a substrate is provided having a nanostructured material on a surface, the substrate being conductive and the nanostructured material being coated with an insulating material. A portion of the nanostructured material is at least partially removed. A conductor is deposited on the substrate in such a way that it is in electrical contact with the substrate through the area where the nanostructured material has been at least partially removed.||04-25-2013|
|20120301785||PROCESS FOR FABRICATING NANOWIRE ARRAYS - A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.||11-29-2012|
|20120181502||METHOD OF ELECTRICALLY CONTACTING NANOWIRE ARRAYS - In one aspect, the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure having a non-nanostructured surface, having a top surface and a bottom surface, located on the same side of the substrate as the array of silicon nanowires; and an electrical contact in contact with the top surface of the contacting structure. In some embodiments, the device includes an aluminum oxide passivation layer over the array of nanowires. In some embodiments, the layer of aluminum oxide is deposited via atomic layer deposition.||07-19-2012|
|20120153251||SELECTIVE EMITTER NANOWIRE ARRAY AND METHODS OF MAKING SAME - Another aspect of the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure including the same material as the substrate having a non-nanostructured surface of a dimension suitable for forming an electrical contact, located on the same side of the substrate as the array of silicon nanowires; wherein the contacting structure is doped with a greater impurity concentration than the nanowire array, thereby forming a selective emitter.||06-21-2012|
|20120153250||Nanowire Device with Alumina Passivation Layer and Methods of Making Same - In one aspect, the present disclosure relates to a device including a silicon substrate, wherein at least a portion of the substrate surface can be a silicon nanowire array; and a layer of alumina covering the silicon nanowire array. In some embodiments, the device can be a solar cell. In some embodiments, the device can be a p-n junction. In some embodiments, the p-n junction can be located below the bottom surface the nanowire array.||06-21-2012|
|20110232756||DESIGNING THE HOST OF NANO-STRUCTURED OPTOELECTRONIC DEVICES TO IMPROVE PERFORMANCE - A nanostructured optoelectronic device is provided which comprises a nanostructured material and a host material intermingled with the nanostructured material. The host material may have a higher index of refraction than the nanostructured material. The host material's index of refraction may be chosen to maximize the effective active area of the device. In an alternative embodiment, the host material comprises scattering centers or absorption/luminescence centers which absorb light and reemit the light at a different energy or both.||09-29-2011|
Patent applications by BANDGAP ENGINEERING, INC.