BAE SYSTEMS Information and Electronic Systems Intergration Inc.
|BAE SYSTEMS Information and Electronic Systems Intergration Inc. Patent applications|
|Patent application number||Title||Published|
|20140325460||METHOD FOR SIMULATION OF PARTIAL VLSI ASIC DESIGN - A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.||10-30-2014|
|20130309815||ISOSTRESS GRID ARRAY AND METHOD OF FABRICATION THEREOF - An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate. The non-uniformity of length in the wire columns reduces stress in the package leads after attachment of the package to a carrier substrate, such as a printed circuit board.||11-21-2013|
|20120319408||AIRFLOW BASED MICROTURBINE POWER SUPPLY - An airflow based microturbine power supply is disclosed. In one embodiment, the airflow based microturbine power supply includes at least one microturbine configured to circulate upon receiving airflow and to convert to mechanical energy. Further, the airflow based microturbine power supply includes a generator coupled to the at least one microturbine to convert the mechanical energy of the microturbine into electrical energy via electromagnetic induction.||12-20-2012|
|20120003948||Quadratic Amplitude Control Circuit For Cosite Interference Cancellation - A quadratic amplitude matching system and associated method with an associated tuning control system is provided for continuously and automatically tuning a quadratic amplitude matching filter (QAMF) to a band center of an interfering signal to provide improved rejection of an interfering signal coupled from a transmission antenna into a local receive antenna in the presence of local multi-path, thereby providing improved interference cancellation system performance. The matching control system is provided as an element of an interference cancellation system.||01-05-2012|
|20100327998||Thermometer Coded Attenuator - Techniques are disclosed that allow for programmable attenuation using thermometer code steps. By thermometer coding the attenuator structure, monotonicity is guaranteed or otherwise greatly improved, which eliminates instability problems with automatic gain control loops and without the need for compensation or trimming. In addition, the thermometer coding technique also greatly reduces phase discontinuity between adjacent gain states.||12-30-2010|
|20090284431||INTEGRATED ELECTRONICS MATCHING CIRCUIT AT AN ANTENNA FEED POINT FOR ESTABLISHING WIDE BANDWIDTH, LOW VSWR OPERATION, AND METHOD OF DESIGN - An integrated electronics matching circuit is placed directly at the feed points of an antenna to match a transmission line to the impedance of the antenna that results in preserving the originally-designed wide bandwidth of the antenna, which in one embodiment is 10:1. A methodology is provided for the design of the integrated electronics matching circuit that marries the output of an antenna modeling tool with an integrated circuit design tool, in which the S parameter outputs of the antenna modeling tool for the antenna ports are coupled to the corresponding ports of the integrated circuit designed by the integrated circuit design tool.||11-19-2009|
Patent applications by BAE SYSTEMS Information and Electronic Systems Intergration Inc.