AZUL SYSTEMS, INC.
|AZUL SYSTEMS, INC. Patent applications|
|Patent application number||Title||Published|
|20140082632||COOPERATIVE PREEMPTION - Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.||03-20-2014|
|20130311741||GARBAGE COLLECTION WITH MEMORY QUICK RELEASE - Memory management includes identifying a region of virtual memory to be reclaimed, the region including an object that is currently located at an original virtual memory location, and the region being supported by at least a portion of a memory resource; relocating the object from the original virtual memory location to a target virtual memory location; releasing the portion of the memory resource so that the portion of memory resource can be reused; and after the portion of the memory resource is released, replacing a reference of the object that points to the original virtual memory location with a reference of the object that points to the target virtual memory location.||11-21-2013|
|20110321064||ACCELERATED CLASS CHECK - Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.||12-29-2011|
|20110302594||ACCELERATED CLASS CHECK - Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.||12-08-2011|
|20110093684||TRANSPARENT CONCURRENT ATOMIC EXECUTION - Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include application code. The block of code does not necessarily indicate that the block of code should be speculatively executed.||04-21-2011|
|20110041015||DETECTING SOFTWARE RACE CONDITIONS - Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous ordering operation.||02-17-2011|
|20080235558||Subsystem and Method for Encoding 64-bit Data Nibble Error Correct and Cyclic-Redundancy Code (CRC) Address Error Detect for Use in a 76-bit Memory Module - A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.||09-25-2008|
Patent applications by AZUL SYSTEMS, INC.