| ATMEL CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120121060 | NON-VOLATILE MEMORY COUNTER - A counter is efficiently implemented in non-volatile memory by using two binary counters and selectively using one or the other as a current counter. Writes to the binary counters are minimized by using two linear counters and using the state of the binary counters to determine which binary counter contains the current count. Write operations can be performed to the “not current” binary counter with the final write operation being to the linear counters. The linear counter write operations can be in program-only mode so that a power failure will not result in a loss of counts. | 05-17-2012 |
| 20120106250 | METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES - Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching. | 05-03-2012 |
| 20120105081 | CAPACITIVE SENSOR, DEVICE AND METHOD - Exemplary capacitive sensors may be capable of determining presence and location of a touch and capable of determining a fingerprint pattern. | 05-03-2012 |
| 20120099662 | Communication Protocol Method And Apparatus For A Single Wire Device - The present invention is a noise tolerant communication protocol device and method where a clock signal input, triggers an internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during periods around edges of changing data values. Therefore, error detection and correction circuitry is not required. A time reference pulse, produced by a bus master, is measured by the protocol device, in determine a data transmission rate by the master. The timing of sampling of input signaling from the master is determined by the protocol, device from measurement of the time reference pulse magnitude. | 04-26-2012 |
| 20120096334 | Error Detecting/Correcting Scheme For Memories - A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation. | 04-19-2012 |
| 20120068775 | Frequency Locking Oscillator - A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle. | 03-22-2012 |
| 20120064842 | Transmitting/Receiving Device and Method for Transmitting Data in a Radio Network - In one embodiment, a method includes receiving an instruction for a transceiver of a device to transmit a first data frame; in response to the instruction, generating a first control signal for a switch to couple the transceiver to a first antenna for transmission of the first data frame by the transceiver via the first antenna; determining whether the transceiver has received within a pre-determined time interval after the transmission of the first data frame a second data frame containing an acknowledgement message confirming successful receipt of the first data frame by another device; and, if the transceiver has not received within the pre-determined time interval after the transmission of the first data frame the second data frame, then generating a second control signal for the switch to couple the transceiver to the second antenna for re-transmission of the first data frame by the transceiver via a second antenna. | 03-15-2012 |
| 20120057422 | LOW POWER SENSE AMPLIFIER FOR READING MEMORY - A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current. | 03-08-2012 |
| 20120044206 | Touch Screen Element - In one embodiment, a method includes receiving one or more first output signals from a first area of a touch-sensitive position sensor; receiving one or more second output signals from a second area of the touch-sensitive position sensor; calculating a first touch-position estimate based on the first output signals; calculating a second touch-position estimate based on the second output signals; and determining, based at least in part on the first and second touch-position estimates, an intended-touch location with respect to the touch-sensitive position sensor. | 02-23-2012 |
| 20120043829 | Mode Switching RC Network - Various embodiments include apparatus, systems, and methods having a conductive contact configured to couple to a resistor-capacitor (RC) network, a device unit coupled to the conductive contact, and a mode switching unit to change a characteristic of a signal at the conductive contact based at least in part on an RC time constant of the RC network. The mode switching unit may switch the device unit between a first operating mode and a second operating mode based on a signal level of the signal. | 02-23-2012 |
| 20120039424 | Receiver and Method for the Reception of a Node by a Receiver in a Wireless Network - In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base. | 02-16-2012 |
| 20120037189 | EX-SITU COMPONENT RECOVERY - Disclosed herein are devices, methods and systems for ex-situ component recovery. The ex-situ recovery can be performed by desorbing or outgassing components of a processing system in a recovery system, rather than in the processing system itself. The recovery system can include a docking station and/or a heated vacuum chamber. The heated vacuum chamber can be used to desorb or outgas components that will be located inside the processing system, while the docking station can be used to desorb or outgas components that will be connected to the processing system. The processing system components can be placed under pressure by the recovery system to desorb or outgas contaminants and remove virtual leaks. The recovery system pressure can include a vacuum roughing pump, a turbomolecular pump, and/or a cryogenic pump to apply a pressure necessary to desorb or outgas the components. | 02-16-2012 |
| 20120036299 | Secure Information Processing - Apparatus, systems, and methods may operate to receive from a requesting device, at a memory device, a request to access a memory domain associated with the memory device, and to deny, by the memory device, the request if the memory domain comprises any part of a secure domain, and the requesting device has not asserted a secure transfer indication. Additional operations may include granting the request if the memory domain comprises some part of the secure domain and the requesting device has asserted the secure transfer signal, or if the memory domain comprises only a non-secure domain. Additional apparatus, systems, and methods are disclosed. | 02-09-2012 |
| 20120025813 | DETECTING INDUCTIVE OBJECTS USING INPUTS OF INTEGRATED CIRCUIT DEVICE - An system for detecting inductive objects includes an inductive sensor circuit for detecting changes in an electromagnetic field (“EMF”) environment and an integrated circuit (“IC”) device. The inductive sensor circuit generates an oscillating analog waveform with an envelope that indicates changes in the EMF environment. The oscillating waveform is coupled to the digital input pin of the IC. A digital interface circuit in the IC is coupled to the digital input pin and is configured for detecting if the oscillating waveform exceeds high and low threshold voltage levels. The detecting results in a digital pulse which represents changes in the EMF environment. In another implementation, a timer input capture pin can be used to detect the waveform envelope decay by storing the time when the waveform crosses a threshold value during a time period. A reduced capture time after the time period expires indicates a change in the EMF environment. | 02-02-2012 |
| 20120025375 | ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE FABRICATED USING PARTIAL ETCHING PROCESS - An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages. | 02-02-2012 |
| 20120019449 | TOUCH SENSING ON THREE DIMENSIONAL OBJECTS - Examples of touch sensors are capable of determining the position of one or more touches and/or gestures on a three dimensional object. | 01-26-2012 |
| 20120001784 | Integrating (SLOPE) DAC Architecture - A current source is used to pre-charge a capacitor to a known value. The capacitor can then be connected to a unity gain buffer to provide a low cost DAC. The DAC can include a self-calibration stage to improve accuracy. The DAC can include two or more circuit branches, each including a current source and a capacitor, where each branch can be calibrated and operated separately to reduce mismatch and to provide a continuous analog voltage output. | 01-05-2012 |
| 20110280286 | Detecting Data Symbols - In one embodiment, a method includes generating a set of sequences of chip values and calculating a correlation between a demodulated signal and each one of two or more of the sequences. Each of the correlations has an absolute value, and one of the correlations has a highest absolute value. The method includes selecting the one of the sequences with the correlation having the highest absolute value; identifying a sequence index corresponding to the selected one of the sequences; and, for each of one or more data symbols in the demodulated signal, determining a value of the data symbol based on the sequence index corresponding to the selected one of the sequences. | 11-17-2011 |
| 20110260250 | Method And Manufacturing Low Leakage Mosfets And FinFets - By aligning the primary flat of a wafer with a ( | 10-27-2011 |
| 20110243258 | Wireless Data Transmission Between a Base Station and a Transponder Via Inductive Coupling - In one embodiment, a method includes receiving a carrier signal transmitted by a base station according to either a first data-transmission protocol or a second data-transmission protocol; detecting a first field gap in the carrier signal indicating initiation of a data transmission by the base station; and determining whether a reference duration is present in the carrier signal after the first field gap. The method includes, if the reference duration is present in the carrier signal after the first field gap then, according to the first data-transmission protocol, determining a calibration value for the data transmission based on the reference duration and decoding the data transmission by measuring durations between successive subsequent field gaps and determining whether each duration as measured is a binary 1 or binary 0 based on the calibration value. | 10-06-2011 |
| 20110242051 | Proximity Sensor - In one embodiment, a method includes monitoring detection by a sensing element of a key touch on a touch screen; determining an amount of time that has elapsed since the sensing element last detected a change of capacitance indicative of a key touch on the touch screen; and, if the amount of time that has elapsed exceeds a predetermined time duration, then initiating a particular function of an apparatus. | 10-06-2011 |
| 20110238869 | Autonomous Multi-Packet Transfer for Universal Serial Bus - A USB device can be configured for multi-packet data transfer to and from endpoints with minimal software intervention. Minimal software intervention allows a Central Processing Unit (CPU) of the USB device to handle other tasks, maximizing USB bus utilization. | 09-29-2011 |
| 20110227589 | Capacitive Position Sensor - In one embodiment, a method includes receiving one or more first signals indicating one or more first capacitive couplings of an object with a sensing element that comprises a sensing path that comprises a length. The first capacitive couplings correspond to the object coming into proximity with the sensing element at a first position along the sensing path of the sensing element. The method includes determining based on one or more of the first signals the first position of the object along the sensing path and setting a parameter to an initial value based on the first position of the object along the sensing path. The initial value includes a particular parameter value and is associated with a range of paratemeter values. The range of parameter values is associated with the length of the sensing path. | 09-22-2011 |
| 20110219160 | FAST TWO WIRE INTERFACE AND PROTOCOL FOR TRANSFERRING DATA - An apparatus and method for exchanging data between devices. An interface between at least two devices features a serial clock line coupled to each device and a bidirectional serial data line coupled to each device. A delay relative to the clock signal is added to an edge of an output enable signal to prevent a collision between devices when control of the data line is switched. Multiple masters and slaves may be connected to the interface. | 09-08-2011 |
| 20110217924 | Transmitting Data Between a Base Station and a Transponder - In particular embodiments, an error correction during the transmission of the data word is made possible through the change of the modulation state at pre-defined time points. | 09-08-2011 |
| 20110199333 | Touch Sensitive Screen - One embodiment provides a capacitive sensor for determining the presence of an object, such as a user's finger or a stylus. The sensor includes a substrate on which electrodes are deposited. A resistive drive electrode is arranged on one side of the substrate and a resistive sense electrode is arranged on the other side of the substrate. A shorting connection connects between two locations on one of the electrodes. The electrodes are connected to respective drive and sense channels. | 08-18-2011 |
| 20110193192 | Stacked-Die Electronics Package with Planar and Three-Dimensional Inductor Elements - An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component. | 08-11-2011 |
| 20110170487 | Method and Apparatus for Data Communication Between a Base Station and a Transponder - A method and system for data communication between a base station and at least one transponder via a high-frequency electromagnetic carrier signal onto which information packets are modulated. Each information packet has a header section, a middle section, and a trailer section. The header section can be provided in a forward link of a data communication between the base station and the transponders for controlling data communication. The header section is used in a return link of a data communication in order to transmit information from the transponder to the base station. | 07-14-2011 |
| 20110170354 | Method and System to Access Memory - This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation. | 07-14-2011 |
| 20110163853 | Method for Selecting One or More Transponders - A method and device for selecting one or more transponders, in particular backscatter-based transponders, from a plurality of transponders by a base station, which method is based on a slotted ALOHA method, in which the base station defines numbered time slots and a random number generated in a given transponder determines a time slot when the transponder transmits its transponder-specific identification to the base station. The random number is generated in a given transponder with the aid of a random number generator, the relevant random number generator is switched into a counter operating mode after reception of a selection command transmitted by the base station, while a count state of the random number generator is decremented or incremented when the base station transmits the start of a time slot, the relevant transponder transmits a transponder-specific identification to the base station if the count state of its random number generator is equal to a predetermined value, and the relevant random number generator is then switched back into the operating mode for random number generation. | 07-07-2011 |
| 20110163851 | Method for Locating a Backscatter-Based Transponder - A method and apparatus for locating a transponder is provided. A carrier signal is transmitted by a base station and a transponder transmits a locating signal that is generated through phase modulation and backscattering of the carrier signal sent by the base station when the transponder is within a transmission range of the base station, whereby the transponder is located on the basis of the locating signal. | 07-07-2011 |
| 20110158176 | Method for Wireless Data Transmission - A method for wireless data transmission between a base station and a transponder is provided, in which data are transmitted between the base station and the transponder in the form of data packets that include a header section with at least one symbol for setting one or more transmission parameters and include at least one additional section. The transponder monitors, during the data transmission, to determine whether a time period between two successive symbol delimiters transmitted by the base station exceeds a maximum time, and if the maximum value is exceeded, a receiver unit of the transponder is reset. The maximum time can be determined in the transponder on the basis of the at least one symbol in the header section. | 06-30-2011 |
| 20110157085 | Capacitive Keyboard with Position-Dependent Reduced Keying Ambiguity - In one embodiment, a method includes receiving two or more output signals responsive to two or more capacitive couplings. Each of the capacitive couplings has occurred between a pointing object and one of two or more sensing areas within a sensing region, and each of the sensing areas has a position within the sensing region. The method includes, if two or more of the output signals each have an output-signal level that exceeds a predefined activation level, then selecting a particular one of the sensing areas with output-signal levels exceeding the predefined activation level as an intended one of the sensing areas based on a predefined ranking scheme that takes into account the positions of the sensing areas within the sensing region. | 06-30-2011 |
| 20110156876 | Method and Device for Recognizing Functional States in RFID or Remote Sensor Systems - A method for recognizing time-variable functional states, e.g., in the course of a programming process, in RFID systems is disclosed, which includes at least one transponder or remote sensor and at least one base station, which transmits data and/or power to the transponder or sensor by a carrier signal. According to the invention, after a specified process state is attained at least one confirmation symbol is transmitted by the transponder or sensor to the base station. As a result, no unfavorable “worst case” scenario has to be provided for chronologically controlling time-variable processes because the base station is able to clearly recognize the beginning and end of the process, as well as the state thereof. RFID systems or remote sensor systems can thus be controlled more quickly and more reliably, resulting especially in reduced costs. | 06-30-2011 |
| 20110145665 | ACCESSING SEQUENTIAL DATA IN A MICROCONTROLLER - System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols. | 06-16-2011 |
| 20110145548 | MICROPROCESSOR FOR EXECUTING BYTE COMPILED JAVA CODE - A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities. | 06-16-2011 |
| 20110121292 | CALIBRATION OF TEMPERATURE SENSITIVE CIRCUITS WITH HEATER ELEMENTS - One or more heating elements are disposed on a semiconductor substrate proximate a temperature sensitive circuit disposed on the substrate (e.g., bandgap circuit, oscillator). The heater element(s) can be controlled to heat the substrate and elevate the temperature of the circuit to one or more temperature points. One or more temperature measurements can be made at each of the one or more temperature points for calibrating one or more reference values of the circuit (e.g., bandgap voltage). | 05-26-2011 |
| 20110116527 | SELF-CALIBRATING, WIDE-RANGE TEMPERATURE SENSOR - A self-calibrating, wide-range temperature sensor includes a current reference, impervious to process and voltage, with the current reference mirrored into two oppositely-sized bipolar transistors or diodes. Duplicate current sources are used with a ratio of geometries between them, such that the larger current biases the smaller bipolar transistor (less cross-sectional area) and the smaller current source biases the larger bipolar transistor (higher cross-sectional area). The current source in conjunction with the differential temperature sensing provides inherent calibration without drift while the differential sensing, from the ratio of geometries in the current paths also increases sensitivity. | 05-19-2011 |
| 20110102361 | TOUCHSCREEN ELECTRODE CONFIGURATION - A touchscreen includes touchscreen electrode elements distributed across an active area of a substrate, and the touchscreen overlays a display. The touchscreen electrode elements are configured to avoid creating moiré patterns between the display and the touchscreen, such as angled, wavy, zig-zag, or randomized lines. In a further example, the electrodes form a mesh pattern configured to avoid moiré patterns. | 05-05-2011 |
| 20110073907 | INTEGRATED CIRCUIT STRUCTURES CONTAINING A STRAIN-COMPENSATED COMPOUND SEMICONDUCTOR LAYER AND METHODS AND SYSTEMS RELATED THERETO - A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein. | 03-31-2011 |
| 20110062598 | STACKED-DIE PACKAGE INCLUDING SUBSTRATE-GROUND COUPLING - Method and apparatus are provided for semiconductor device packages. In an example, an apparatus can include a first semiconductor device, a ground pad situated on an uppermost portion of the first semiconductor device and configured to electrically couple portions of the first semiconductor device to aground potential, and a second semiconductor device having at least a portion in electrical communication with an uppermost face of the first semiconductor device through a first electrically-conductive adhesive. In an example, the first electrically-conductive adhesive can be electrically coupled to the ground bond pad on the first semiconductor device. | 03-17-2011 |
| 20110044114 | APPARATUS AND METHOD FOR BIT LINES DISCHARGING AND SENSING - Some embodiments include first bit lines coupled to a first junction bus and second bit lines coupled to a second junction bus. Such embodiments can also include a first network to discharge at least one of the first bit lines through the first junction bus and to discharge at least one of the second bit lines through the second junction bus. Such embodiments can further include a second network to couple a sense amplifier to at least one of the first junction bus and the second junction bus. Other embodiments are described. | 02-24-2011 |
| 20110043482 | ANISOTROPIC TOUCH SCREEN ELEMENT - A touch sensitive position sensor for detecting the position of an object in two dimensions is described. The position sensor has first and second resistive bus-bars spaced apart with an anisotropic conductive area between them. Electric currents induced in the anisotropic conductive area by touch or proximity flow preferentially towards the bus-bars to be sensed by detection circuitry. Because induced currents, for example those induced by drive circuitry, flow preferentially along one direction, pin-cushion distortions in position estimates are largely constrained to this single direction. Such one-dimensional distortions can be corrected for very simply by applying scalar correction factors, thereby avoiding the need for complicated vector correction. | 02-24-2011 |
| 20110043226 | CAPACITIVE SENSOR - Method and apparatus are provided for a capacitive sensor. In an example, a capacitive sensor can include a first sensing element, a sensing channel operable to generate a first signal indicative of first capacitance between the sensing element and a system ground, and a processor responsive to a change in the first capacitance between the first sensing element and ground. The processor can be configured to adjust a parameter value based on a first duration of the change in the first capacitance. | 02-24-2011 |
| 20110037705 | TOUCH-SENSITIVE USER INTERFACE - A touch-sensitive user interface includes a sensor element providing a plurality of sensing areas, a measurement circuit coupled to the sensor element and operable to iteratively acquire measurement signal values indicative of the proximity of an object to the respective sensing areas, and a processor operable to receive the measurement signal values from the measurement circuit and to classify a sensing area as an activated sensing area for a current iteration according to predefined selection criteria, wherein the predefined selection criteria are such that activation of at least a first sensing area in a current iteration is suppressed if at least a second sensing area has previously been classified as an activated sensing area within a predefined period before the current iteration. Thus a sensing area may be prevented from being activated for a predefined period of time after another sensing area has been activated. Furthermore, activation of different sensing areas may be suppressed for different periods of time in response to other sensing areas having been previously activated. sensing area | 02-17-2011 |
| 20110037634 | Device and Method for Scanning Multiple ADC Channels - An analog to digital converter has an input for coupling to multiple channels having analog signals. The analog to digital converter converts the analog signals on such channels to provide a digital output. A memory device has an enable bit for each of the multiple channels and a current channel register. An interface coupled to the memory device and current channel register selects a next channel for converting by the analog to digital converter, skipping channels that are not enabled. | 02-17-2011 |
| 20110037513 | Controlling Bias Current for an Analog to Digital Converter - A converter includes an analog to digital converter having a bias current input, a control input, and an analog input to provide a digital output as a function of the analog input. A bias module is coupled to the bias current input to provide bias current to the analog to digital converter. A controller is coupled to the bias module and to the control input of the analog to digital converter. The controller controls the analog to digital converter to sample an analog input and controls the bias module to provide an operating bias current during sampling of the analog input and an idle bias current when not sampling the analog input. | 02-17-2011 |
| 20110032019 | LEVEL SHIFTER WITH OUTPUT LATCH - A level shifter for a microcontroller shifts an input voltage in a first power domain to an output voltage level consistent with a second power domain. The level shifter is enabled to shift the voltages when both power domains are operative. | 02-10-2011 |
| 20110026347 | Differential Sense Amplifier - A differential sense amplifier can perform data sensing using a very low supply voltage. | 02-03-2011 |
| 20110025463 | Parallel Antennas for Contactless Device - An electronic information device includes an integrated circuit embedded within the device. The electronic information device further includes a first antenna that is embedded within the device and is connected to the integrated circuit. The electronic information device further includes a second antenna that is embedded within the device and is connected to the integrated circuit. The first antenna is oriented within a first plane and the second antenna is oriented within a second plane that is substantially parallel to the first plane. | 02-03-2011 |
| 20110014747 | STACKABLE PACKAGES FOR THREE-DIMENSIONAL PACKAGING OF SEMICONDUCTOR DICE - An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component of a leadless three-dimensional stackable semiconductor package having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated into individual package strip for leadless packages. three-dimensional stacking is achieved by a bonding area on an uppermost portion of the sidewall. The sidewall of the strip is high enough to enclose an encapsulant covering a later mounted integrated circuit die and associated bonding wires. | 01-20-2011 |
| 20110012886 | Efficient Display Driver - A driver circuit for a display device (e.g., an LCD) omits buffers and a resistive ladder and connects the output of a switched regulator directly to a display device through a selector switch. Voltage inputs for the display device can be selectively coupled to the output of the switched regulator using the selector switch. Each voltage input can be coupled to a capacitor that is charged when the corresponding voltage input is coupled to the high voltage output of the switched regulator. In some implementations, bypass switches are connected between the voltage inputs. If the voltage of a given capacitor is too high, the excess voltage can be transferred or otherwise discharged through the bypass switch to another capacitor storing a lower voltage. | 01-20-2011 |
| 20110001215 | MULTI-COMPONENT ELECTRONIC PACKAGE - An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure. | 01-06-2011 |
| 20100329059 | APPARATUS AND METHODS FOR SENSE AMPLIFIERS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell; and a second circuit including a second circuit path coupled between the supply node and the line to charge the line during the memory operation. Additional embodiments are disclosed. | 12-30-2010 |
| 20100329023 | SENSE AMPLIFIER APPARATUS AND METHODS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed. | 12-30-2010 |
| 20100315856 | HIGH-DENSITY NON-VOLATILE READ-ONLY MEMORY ARRAYS AND RELATED METHODS - In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values. | 12-16-2010 |
| 20100315855 | ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits. | 12-16-2010 |
| 20100301122 | NON-VOLATILE MEMORY CHARGE PUMP FOR RADIO FREQUENCY IDENTIFICATION (RFID) SYSTEM - A charge pump is incorporated into circuitry of an RFID tag. The charge pump takes advantage of an antenna voltage phase to eliminate the need for a charge pump clock generator. Placement of the charge pump in the RFID circuitry reduces the number of pump stages and eliminates drivers used in each pump stage. In some implementations, an RFID tag comprises antenna circuitry, including a tuned antenna, for receiving an RF signal. Voltage conversion circuitry in the RFID tag is coupled to the antenna circuitry and operable for converting a varying magnetic field produced in the antenna to a voltage source. A charge pump is coupled to output voltage signals of the antenna circuitry which provide the charge pump with a high starting reference voltage and a two phase pump clock. | 12-02-2010 |
| 20100283651 | CYCLIC DIGITAL TO ANALOG CONVERTER - Some embodiments include apparatus and methods having an amplifier, a capacitor network coupled to the amplifier, and switching circuitry coupled to the amplifier and the capacitor network. The switching circuit is configured to successively apply a selected reference voltage selected from among a first reference voltage, a second reference voltage, and a third reference voltage to the capacitor network in response to a digital input code to generate an output voltage. Additional embodiments are disclosed. | 11-11-2010 |
| 20100277841 | THRESHOLD VOLTAGE METHOD AND APPARATUS FOR ESD PROTECTION - An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground. | 11-04-2010 |
| 20100271143 | Current-Controlled Hysteretic Oscillator - The disclosed current-controlled hysteretic oscillator operates by controlled currents opposing each other in differential pairs to set a controlled hysteresis for improved relaxation oscillations with immunity to phase or frequency error. | 10-28-2010 |
| 20100263922 | SURFACE MOUNTING CHIP CARRIER MODULE - A device includes a carrier and an integrated circuit chip having a first side supported by the carrier and a second side having contacts. The carrier has multiple carrier contacts supported by the carrier and separated from the integrated circuit chip. Multiple leads are coupled between the contacts on the integrated circuit chip and the multiple carrier contacts. A resin encapsulates the integrated circuit chip leaving the multiple carrier contacts at least partially uncovered for attaching to a card or board. | 10-21-2010 |
| 20100262880 | QUADRATURE DECODER FILTERING CIRCUITRY FOR MOTOR CONTROL - The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry. | 10-14-2010 |
| 20100258360 | Two-Dimensional Position Sensor - A two dimensional position sensor having a touch-sensitive panel defined by a single-layer electrode pattern arranged on one side of a substrate. The electrode pattern is made up of ‘n’ electrode units extending row-wise over the panel. Each electrode unit is made up of a single drive electrode extending across the touch-sensitive area of the panel and a plurality of ‘m’ sense electrodes, which collectively laterally extend across the touch-sensitive area and individually each occupy only a portion of the lateral extent. The sense electrodes are longitudinally offset from their associated drive electrode so that one edge of each sense electrode lies adjacent to one edge of the drive electrode, these coupling edges being separated by a gap dimensioned so that in use each pair of drive and sense electrodes have efficient capacitively coupling across the gap. This electrode pattern allows the longitudinal extent of each electrode unit to be made relatively small, which in turn is better for sensing multiple simultaneous touches, since this benefits from having more electrode units in any given panel. | 10-14-2010 |
| 20100250904 | METHODS AND PROCESSOR-RELATED MEDIA TO PERFORM RAPID RETURNS FROM SUBROUTINES IN MICROPROCESSORS AND MICROCONTROLLERS - Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction. | 09-30-2010 |
| 20100246282 | VOLTAGE GENERATOR FOR MEMORY ARRAY - A high voltage may be generated for programming memory cells in a memory array. A middle voltage may also be generated for reading memory cells in the memory array. Control logic and switches may be used to select between the high voltage and the middle voltage. A first oscillator generates clock signals at a high frequency for generating the voltages, and a low frequency oscillator may be used to generate pulses at a lower frequency than the first oscillator to allow the first oscillator to operate only during such pulses to conserve power during a stand-by mode of operation to maintain the middle or medium voltage. | 09-30-2010 |
| 20100241874 | Method and Apparatus to Scramble Data Stored in Memories Accessed by Microprocessors - A scrambler/descrambler module included in an integrated circuit device is operable for receiving a scrambling key and constant data that is unique to the integrated circuit device. The scrambler/descrambler module includes a first layer or circuit arrangement that uses a scrambling key to generate first scrambled data. The scrambler/descrambler module includes a second layer or second circuit arrangement that uses data that is unique to the integrated circuit device, and that is constant over the life of the integrated circuit device, to scramble the first scrambled data to generate second scrambled data. | 09-23-2010 |
| 20100237908 | LOW CURRENT COMPARATOR WITH PROGRAMMABLE HYSTERESIS - A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state ( | 09-23-2010 |
| 20100229011 | Power Reduction in Microcontrollers - The disclosed implementations provide for power reduction in microcontrollers by reactivating a clock in the microcontroller for one or more peripheral modules in response to an internal or external trigger event, thus allowing the one or more peripheral modules to respond to events while operating in a low-power sleep mode. In some implementations, one or more peripheral modules in a microcontroller provide a clock request signal to a clock generator in the microcontroller. In response to the clock request signal, the clock generator reactivates one or more oscillator sources. The clock generator resumes clock generation only for the one or more requesting peripheral modules, keeping power consumption in the microcontroller to a minimum and not disturbing other modules in the microcontroller. | 09-09-2010 |
| 20100224981 | ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE - An integrated circuit assembly comprises an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and a plurality of solder balls are formed on the plurality of external connection pads. | 09-09-2010 |
| 20100224684 | SMART CARD READER - A card reader receives an indication that a device has been plugged into a socket of the card reader. Power is provided to the socket in accordance with a first type of device. An attempt to communicate with the device is made in accordance with a first type of device protocol. If the communication attempt is not successful, power is provided to the socket in accordance with a second type of device, and communications commence with the device in accordance with a second type of device protocol. | 09-09-2010 |
| 20100223476 | SINGLE PIN COMMUNICATION MECHANISM - A method and device include a power pin, a ground pin, and a communications pin. A communications module receives power from the power pin and utilizes an edge counting communication protocol over the communication pin. | 09-02-2010 |
| 20100223434 | Dummy Write Operations - A dummy write operation is disclosed that mimics an actual write operation to a memory array. In some implementations, a dummy write operation mimics an actual write operation by starting a charge pump, selecting a correct data line in the memory array, and by following the sequencing of an actual write operation. By mimicking an actual write operation, an attacker cannot use power analysis to distinguish between dummy and actual write operations. For example, PIN comparison operations would present the same or substantially the same power trace for both positive and negative comparisons, making it difficult for an attacker to determine if a retry count was written to NVM. | 09-02-2010 |
| 20100220854 | DATA SECURITY SYSTEM - A data security system that includes a first memory device to store message data to be secured, a second memory device to store microcode including an instruction set defining a cryptographic algorithm for use in securing the message data, and a processing unit to execute the microcode to implement the cryptographic algorithm. | 09-02-2010 |
| 20100219864 | Dual Mode, Single Ended to Fully Differential Converter Structure - A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode. | 09-02-2010 |
| 20100219846 | Capacitive Sensing - A multi-channel capacitive sensor for measuring the capacitances of a plurality of sense electrodes to a system reference potential. The sensor comprises a sample capacitor having a first terminal and a second terminal, a first diode having a first terminal coupled to the second terminal of the sample capacitor and a second terminal coupled to a first sense electrode, and a second diode having a first terminal coupled to the second terminal of the sample capacitor and a second terminal coupled to a second sense electrode. The sample capacitor and diodes are coupled to a control circuit, e.g. implemented in a microcontroller. The control circuit is operable to apply a drive signal, e.g. a series of voltage pulses, to the first terminal of the sample capacitor while simultaneously applying a bias signal to the second terminal of one or other of the diodes to prevent the diode from conducting the drive signal. Thus charge transfer techniques can be used to measure multiple capacitances while sharing a common sample capacitor. This helps reduce inter-channel drift. Further measurement channels may be added by providing further diodes and corresponding sense electrodes. With three or more channels the scheme requires only one additional control circuit connection per additional channel. | 09-02-2010 |
| 20100219845 | Method and Apparatus for Sensing - An apparatus for sensing a change in capacitance of a sensing electrode to a system ground, such as that which may be used to form a touch sensor, with the sensing electrode forming touch sensitive surface is arranged to include a sleep mode of operation. The apparatus includes a sample capacitor having a first terminal coupled to the sensing electrode, and a second terminal coupled to a voltage measurement circuit. The voltage measurement circuit is arranged in operation to determine a voltage at the second terminal of the sample capacitor. A voltage biasing arrangement is arranged under the control of a controller to apply a biasing voltage or the system ground to the first terminal or the second terminal of the sample capacitor in accordance with a measurement cycle. The measurement cycle includes an initialisation part, a charging part in which the sensing electrode is charged via the sample capacitor, and a measurement part in which a voltage at the second terminal is measured and it is determined whether there has been a change in capacitance of the sensing electrode in accordance with the measured voltage. Before or after the measurement cycle, the controller is arranged to enter the sleep mode in which the sensing electrode is biased at a voltage which is greater than the system ground, whilst the second terminal of the sample capacitor is floated by not applying the system ground or a biasing voltage, so that the sensing electrode is held at a voltage above the system ground during the sleep mode. | 09-02-2010 |
| 20100208539 | VOLTAGE REGULATOR FOR MEMORY - A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell. | 08-19-2010 |
| 20100208505 | ANTI-CROSS-TALK CIRCUITRY FOR ROM ARRAYS - A circuit and method precharge a selected bit-line in a read only memory (ROM) array during a precharge period of a read cycle. At least one bit-line adjacent to the selected bit-line is discharged during the precharge period. After the precharge period, the selected bit-line is read such that parasitic capacitance effects on the selected bit-line are reduced. | 08-19-2010 |
| 20100201430 | MOS Resistor with Second or Higher Order Compensation - A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference. | 08-12-2010 |
| 20100199118 | MICROCONTROLLER WITH COMPATIBILITY MODE - A microcontroller is operable to enable a compatibility mode where a clock source of the microcontroller is adjusted to support timing requirements of applications written for legacy microcontrollers. In some implementations, one or more scaling factors and/or wait state factors are applied to the clock source of the microcontroller to ensure timing compatibility. | 08-05-2010 |
| 20100188049 | CURRENT TO FREQUENCY CONVERSION, APPARATUS AND METHODS - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include features of current to frequency conversion that may be implemented in a variety of applications. Additional apparatus, systems, and methods are disclosed. | 07-29-2010 |
| 20100172113 | METHODS FOR FORMING PACKAGED PRODUCTS - An apparatus and methods for packaging semiconductor devices are disclosed. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration. | 07-08-2010 |
| 20100149896 | SENSE AMPLIFIER - A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder. | 06-17-2010 |
| 20100149710 | SNAP-BACK TOLERANT INTEGRATED CIRCUITS - A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar transistor. A second NMOS transistor may be connected in series with the first NMOS transistor. A gate node of the second NMOS transistor may be coupled to a bias node, such that the second NMOS transistor in conductive (ON) state. An auxiliary circuit coupled to a source node of the first NMOS transistor may be configured to provide a bias potential at the source node of the first NMOS transistor, when the first NMOS transistor is in a non-conducting state (OFF). | 06-17-2010 |
| 20100127752 | LEVEL SHIFTER WITH LOW VOLTAGE DEVICES - A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs. | 05-27-2010 |
| 20100123670 | Touch Screen Sensor - A two-dimensional touch sensor comprising a plurality of electrodes arranged in a mesh pattern on a substrate. Each electrode is formed by interconnected metal traces, the metal being intrinsically opaque, but the metal traces being sufficiently narrow to be practically invisible. The metal traces have a width less than or equal to 10 μm and occupy less than or equal to 5% of the area of each electrode. The electrodes can be deposited additively via a printing process, for example using copper as the metal. The narrow width of the tracks allows the film to be highly transparent, since the electric field used in capacitive touch screens can be made to propagate with very low metal densities. | 05-20-2010 |
| 20100122097 | COMMAND DECODER FOR MICROCONTROLLER BASED FLASH MEMORY DIGITAL CONTROLLER SYSTEM - A command decoder used for a microcontroller based Flash memory digital controller system includes multiple subsystems, including the command decoder, which serves as the main user interface for interpreting commands from a user and managing the priority of commands and command modes. The command decoder also stores crucial information including address, data, opcodes, and various flags registers that are used by other subsystems including the program buffer, burst read module, register block, and microcontroller. In addition, the command decoder contains clock synchronization logic, controls the sleep function of the microcontroller and serves as a test mode controller. | 05-13-2010 |
| 20100122025 | LOW COST IMPLEMENTATION FOR SMALL CONTENT-ADDRESSABLE MEMORIES - A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object. | 05-13-2010 |
| 20100122015 | SOFTWARE ADAPTED WEAR LEVELING - A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices. | 05-13-2010 |
| 20100103707 | Contactless Interface - Power extracted from an antenna inductively coupled to an alternating magnetic field is regulated to provide voltage supplies. In some implementations, a first voltage supply (e.g., 3.8 volts) provides regulated voltage to analog circuits and a second, lower, voltage supply (e.g., 1.4 volts) provides regulated voltage to digital circuits. The first voltage supply is regulated, using shunt regulation, by a first voltage regulator circuit. The second voltage supply is regulated, using a series regulation, by a second voltage regulator circuit. The second voltage regulator circuit is supplied by the shunted current from the first voltage regulator. Excess shunt current provided by the first regulator circuit can be bypassed (e.g., bypassed to ground). The second voltage regulator circuit can use a timer circuit to control the amount of charge transferred to a second voltage supply rail. The timer circuit can compensate for different currents from the first voltage regulator circuit. | 04-29-2010 |
| 20100097346 | CAPACITIVE TOUCH BUTTONS COMBINED WITH ELECTROLUMINESCENT LIGHTING - A capacitive touch sensor includes a layer of electro-luminescent (EL) material arranged between a first electrode and a second electrode, A controller includes a capacitance sensing circuit coupled to first and/or second electrode and arranged to measure a capacitive coupling associated with the first and/or second electrode. The controller is further operable to apply an EL drive signal across the first and second electrodes to cause the layer of EL material between the electrodes to illuminate. This provides a simple structure that is sensitive to objects adjacent a sensing region defined by the first and/or second electrodes, and which may also be readily illuminated by applying an EL drive signal across the electrodes. | 04-22-2010 |
| 20100085121 | Auto Trimming Oscillator - An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the oscillator output clock frequency. The oscillator is trimmed to deliver a clock frequency which is a closest match to the reference clock frequency. | 04-08-2010 |
| 20100076742 | SIMULATION MODEL FOR TRANSISTORS - Various embodiments include methods and apparatus for simulating a transistor using a simulation model that includes a transistor simulation model coupled to diode simulation model. | 03-25-2010 |
| 20100074030 | ADAPTIVE REGULATOR FOR IDLE STATE IN A CHARGE PUMP CIRCUIT OF A MEMORY DEVICE - An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node. | 03-25-2010 |
| 20100064173 | MECHANISM FOR STORING AND EXTRACTING TRACE INFORMATION USING INTERNAL MEMORY IN MICRO CONTROLLERS - This document relates to apparatus and methods to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. Trace data can be retrieved from system memory using a debug port of the debug logic. A system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools. | 03-11-2010 |
| 20100064144 | DATA SECURITY - This document discloses data security systems and methods of securing data. A cache memory can be connected between a decryption engine and a central processing unit (“CPU”) to increase security of encrypted data that is stored in a datastore. The decryption engine can retrieve the encrypted data from the datastore, decrypt the data, and store the decrypted data in the cache. In turn, the decrypted data can be accessed by the CPU. The data can be encrypted with a secret key, so that decryption can be performed with the secret key. The key can be varied based on a memory address associated with the data. The key can be protected by restricting direct access to the decryption engine by the CPU. | 03-11-2010 |
| 20100061152 | METHOD AND SYSTEM TO ACCESS MEMORY - This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation. | 03-11-2010 |
| 20100060494 | Analog to Digital Converter - An analog to digital converter (ADC) can operate in an amplifier configuration or a converter configuration. In the amplifier configuration, the ADC receives an input voltage and scales the input voltage by a factor during at least one clock cycle. In the converter configuration, the ADC uses the scaled input voltage to determine a digital value corresponding to the input voltage. | 03-11-2010 |
| 20100059508 | SEMICONDUCTOR PROCESSING - This document discloses semiconductor processing systems, methods, and devices. The systems, methods and devices activate dopants in a processing chamber having a temperature that is less than, for example, 300 degrees. A microwave energy source provides a microwave transmission to a waveguide system that uniformly distributes the microwave transmission. The waveguide system can include a rectangular waveguide coupled to a cylindrical waveguide. The rectangular waveguide guides the microwave transmission in a second propagation direction to a cylindrical waveguide. The cylindrical waveguide uniformly distributes the electromagnetic transmission and guides the electromagnetic transmission in a third propagation direction to a processing chamber. A semiconductor wafer can be exposed to the microwave transmission and the temperature of the chamber to activate dopants in the semiconductor wafer. | 03-11-2010 |
| 20100057960 | SECURE INFORMATION PROCESSING - Apparatus, systems, and methods may operate to receive from a requesting device, at a memory device, a request to access a memory domain associated with the memory device, and to deny, by the memory device, the request if the memory domain comprises any part of a secure domain, and the requesting device has not asserted a secure transfer indication. Additional operations may include granting the request if the memory domain comprises some part of the secure domain and the requesting device has asserted the secure transfer signal, or if the memory domain comprises only a non-secure domain. Additional apparatus, systems, and methods are disclosed. | 03-04-2010 |
| 20100052963 | Digital-to-Analog Converter - A PRA-DAC is disclosed. The PRA-DAC is operable to increase its conversion speed. | 03-04-2010 |
| 20100052840 | LOW VARIATION RESISTOR - This document discloses low variation resistor devices, methods, systems, and methods of manufacturing the same. In some implementations, a low-variation resistor can be implemented with a metal-oxide-semiconductor field-effect-transistor (“MOSFET”) operating in the triode (e.g., ohmic) region. The MOSFET can have a source that is connected to a reference voltage (e.g., ground) and a gate connected to a gate voltage source. The gate voltage source can generate a gate voltage that varies in proportion to changes in the temperature of an operating environment. The gate voltage variation can, for example, be controlled so that it offsets the changes in MOSFET resistance that are caused by changes in temperature. In some implementations, the gate voltage variation offsets the resistance variance by offsetting changes in transistor mobility that are caused by changes in temperature. | 03-04-2010 |
| 20100051343 | METHOD FOR FORMING AN INTEGRAL ELECTROMAGNETIC RADIATION SHIELD IN AN ELECTRONIC PACKAGE - A method and system for fabricating an integral electromagnetic radiation shield for an electronics package is disclosed. Various embodiments include exposing a portion of at least one ground contact feature in an electronic package by removing a portion of the electronic package above the at least one ground contact feature to form at least one trench above the at least one ground contact feature; depositing electromagnetic radiation shield material in the at least one trench to substantially fill the at least one trench with a trench deposit; and depositing additional electromagnetic radiation shield material over a substantial portion of the electronic package, wherein the electromagnetic radiation shield material in the trench and over the substantial portion of the electronic package form an integral electromagnetic radiation shield which is electrically connected to the at least one ground contact feature. | 03-04-2010 |
| 20100045632 | Capacitive Position Sensor - A capacitive position sensor has a two-layer electrode structure. Drive electrodes extending in a first direction on a first plane on one side of a substrate. Sense electrodes extend in a second direction on a second plane on the other side of the substrate so that the sense electrodes cross the drive electrodes at a plurality of intersections which collectively form a position sensing array. The sense electrodes are provided with branches extending in the first direction part of the way towards each adjacent sense electrode so that end portions of the branches of adjacent sense electrodes co-extend with each other in the first direction separated by a distance sufficiently small that capacitive coupling to the drive electrode adjacent to the co-extending portion is reduced. Providing sense electrode branches allow a sensor to be made which has a greater extent in the first direction for a given number of sense channels, since the co-extending portions provide an interpolating effect. The number of sense electrode branches per drive electrode can be increased which allows a sensor to be made which has ever greater extent in the first direction without having to increase the number of sense channels. | 02-25-2010 |
| 20100044122 | Capacitive Touch Screen with Noise Suppression - A capacitive touch sensor wherein the touch sensitive panel has drive electrodes arranged on the lower side of a substrate and sense electrodes arranged on the upper side. The drive electrodes are shaped and dimensioned to substantially entirely cover the touch sensitive area with individual drive electrodes being separated from each other by small gaps, the gaps being so small as to be practically invisible. The near blanket coverage by the drive electrodes also serves to screen out interference from noise sources below the drive electrode layer, such as drive signals for an underlying display, thereby suppressing noise pick-up by the sense electrodes that are positioned above the drive electrodes. | 02-25-2010 |
| 20100038760 | Metal Leadframe Package with Secure Feature - A fabrication method for a BGA or LGA package includes a low-cost metal leadframe with internally extended leads. I/O attach lands can be placed at any location on the metal leadframe, including the center of the package. An I/O attach land can be fabricated at any position upon an extended lead (e.g., near the center of the package). During fabrication of the package, an isolation saw cut to the bottom of the package can be used to electrically disconnect the leadframe circuit from the peripheral extension traces to prevent tampering with the IC die by probing the edge metal traces. | 02-18-2010 |
| 20100038759 | Leadless Package with Internally Extended Package Leads - A DFN package includes internally extended package leads. One or more package pads are physically and electrically extended from a first edge of the package to a second, opposite edge of the package. These extended package leads can terminate at the edges of the leadframe. The package pads and the extended package leads where the IC die is attached can have full leadframe thickness. Other extended package lead features can have a reduced leadframe thickness (e.g., about half the leadframe thickness). Leadframe features can be physically and electrically connected to a tie-bar feature which can be an integral part of a leadframe matrix. The tie-bar can stabilize the leadframe features during assembly. The tie-bar can also provide electrical connectivity for post assembly leadframe plating. The tie-bar can be removed during package singulation by sawing or punching techniques to free the leadframe features both physically and electrically. | 02-18-2010 |
| 20100037000 | ONE-TIME-PROGRAMMABLE MEMORY EMULATION - This document discloses one-time-programmable (“OTP”) memory emulation and methods of performing the same. OTP memory can be emulated by managing reads and writes to a memory array in response to an instruction to write data to a OTP memory location and selectively setting a security flag that corresponds to the memory locations. The memory array can be a NAND Flash memory array that includes multiple pages of memory. The memory array can be defined by memory blocks that can include multiple pages of memory. When an OTP write instruction is received, previously stored data can be read from a first page of memory, combined with the new data and stored to a target page of memory. A security flag can be set to prevent the target page from being reprogrammed prior to an erase. | 02-11-2010 |
| 20100022072 | Semiconductor Fabrication - This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate. | 01-28-2010 |
| 20100019349 | METHOD FOR FABRICATING CONDUCTING PLATES FOR A HIGH-Q MIM CAPACITOR - A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process. | 01-28-2010 |
| 20100019306 | Semiconductor Fabrication - This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate. | 01-28-2010 |
| 20100018554 | EX-SITU COMPONENT RECOVERY - Disclosed herein are devices, methods and systems for ex-situ component recovery. The ex-situ recovery can be performed by desorbing or outgassing components of a processing system in a recovery system, rather than in the processing system itself. The recovery system can include a docking station and/or a heated vacuum chamber. The heated vacuum chamber can be used to desorb or outgas components that will be located inside the processing system, while the docking station can be used to desorb or outgas components that will be connected to the processing system. The processing system components can be placed under pressure by the recovery system to desorb or outgas contaminants and remove virtual leaks. The recovery system pressure can include a vacuum roughing pump, a turbomolecular pump, and/or a cryogenic pump to apply a pressure necessary to desorb or outgas the components. | 01-28-2010 |
| 20100017563 | MICROCONTROLLER BASED FLASH MEMORY DIGITAL CONTROLLER SYSTEM - Some embodiments includes a digital control system having a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control, and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug. Other embodiments are described. | 01-21-2010 |
| 20100014370 | PRECHARGE AND EVALUATION PHASE CIRCUITS FOR SENSE AMPLIFIERS - A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors. | 01-21-2010 |
| 20100014354 | USE OF RECOVERY TRANSISTORS DURING WRITE OPERATIONS TO PREVENT DISTURBANCE OF UNSELECTED CELLS - A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array ( | 01-21-2010 |
| 20100011250 | MICROCONTROLLER INFORMATION EXTRACTION SYSTEM AND METHOD - A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial interface, such as a JTAG interface. The interface can communicate directly with a debug register to retrieve program count values, both when the microcontroller is halted and when it is executing instructions. The polling interval to retrieve the program count values may be adjusted by a user of the debugger based on considerations such as bandwidth and accuracy. The microcontroller may transmit the program count value to the debug register from a processing register that is not accessible to the debugger. | 01-14-2010 |
| 20100008159 | Differential Sense Amplifier - A differential sense amplifier can perform data sensing using a very low supply voltage. | 01-14-2010 |
| 20100001812 | Mode Switching RC Network - Various embodiments include apparatus, systems, and methods having a conductive contact configured to couple to a resistor-capacitor (RC) network, a device unit coupled to the conductive contact, and a mode switching unit to change a characteristic of a signal at the conductive contact based at least in part on an RC time constant of the RC network. The mode switching unit may switch the device unit between a first operating mode and a second operating mode based on a signal level of the signal. | 01-07-2010 |
| 20090327709 | MEMORY ADDRESS OBFUSCATION - Apparatus, systems, and methods may operate to provide, to a memory device, an obfuscated clear-page address derived from a clear-page address that is not the same as a key-page address and/or providing, to the memory device, an obfuscated key-page address derived from the key-page address when the obfuscated clear-page address is the same as the key-page address. Additional apparatus, systems, and methods are disclosed. | 12-31-2009 |
| 20090303769 | ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits. | 12-10-2009 |
| 20090302449 | PACKAGED PRODUCTS, INCLUDING STACKED PACKAGE MODULES, AND METHODS OF FORMING SAME - An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant. | 12-10-2009 |
| 20090295447 | APPARATUS AND METHODS FOR A HIGH-VOLTAGE LATCH - Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described. | 12-03-2009 |
| 20090289329 | Differential Varactor - A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers. | 11-26-2009 |
| 20090284296 | SELECTABLE DELAY PULSE GENERATOR - A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer. | 11-19-2009 |
| 20090279361 | Addressable Memory Array - This document discloses non-volatile memory cells and methods of manufacturing the same. The memory arrays are byte, word, and/or page addressable without using a byte select transistor. The byte select transistor is eliminated by using the well, memory transistor control gates, and select transistor gates to selectively program a byte, word, or page. | 11-12-2009 |
| 20090273015 | NON-VOLATILE MEMORY CELL - This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define tunnels having one or more curvatures. | 11-05-2009 |
| 20090271536 | DESCRIPTOR INTEGRITY CHECKING IN A DMA CONTROLLER - The present invention relates to a Direct Memory Access controller that, in an embodiment, executes I/O descriptors conditionally. A linked list item contains a checksum computed on the descriptor fields. When the linked list item is fetched, the checksum is computed on the descriptor. If both checksums are equal, the linked list item is considered valid and the descriptor is executed. At the end of a DMA I/O, the next descriptor in the linked list is fetched. When the checksum fails, the descriptor is corrupted and the channel is stopped and an error is reported to the operating system. | 10-29-2009 |
| 20090265411 | CRYPTOGRAPHIC AUTHENTICATION APPARATUS, SYSTEMS AND METHODS - Apparatus, systems, and methods send an interrogation command from an interrogation and timing apparatus to a timed identification (TID) apparatus. The TID apparatus receives the interrogation command, performs a series of logical operations to calculate a response, and returns the response within a maximum length of time established by the interrogation and timing apparatus. The interrogation and timing apparatus confirms that the length of time between sending the interrogation command and receiving the response is within the maximum length of time and that the response is correct. If so, the TID apparatus is authenticated. Additional embodiments are disclosed and claimed. | 10-22-2009 |
| 20090258478 | METHOD FOR PROVIDING A NANOSCALE, HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) ON INSULATOR - Various embodiments include forming a silicon-germanium layer over a substrate of a device; forming a layer in the silicon-germanium layer, the layer including at least one of boron and carbon; and forming a silicon layer over the silicon-germanium layer. Additional embodiments are described. | 10-15-2009 |
| 20090257295 | Randomizing Current Consumption in Memory Devices - In some implementations, a memory device includes a plurality of memory cells, each memory cell storing a plurality of data bits; an input/output interface that is configured to, in response to receiving a read signal and an address value that identifies a specific memory cell in the plurality of memory cells, output a plurality of data bits corresponding to the identified specific memory cell; and a delay controller that is configured to delay the outputting to the input/output interface of at least one of the plurality of data bits based on a randomly selected or pseudo-randomly selected delay value. The memory device can further include a delay block having a plurality delay paths having varying delays, and randomly selecting or pseudo-randomly selecting the delay value can include randomly selecting or pseudo-randomly selecting one of the plurality of delay paths through which to transmit a control signal. | 10-15-2009 |
| 20090249136 | ACCESSING SEQUENTIAL DATA IN A MICROCONTROLLER - System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols. | 10-01-2009 |
| 20090248771 | TRUE RANDOM NUMBER GENERATOR - True random number generation circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers, with their output being combined to generate random numbers. At least one of the oscillators is programmable with a variable frequency. One embodiment controls the variable frequency of oscillators with output from one or more sets of oscillators and linear feedback shift registers. In other embodiments, linear feedback shift register output is captured and used to control the frequency of oscillators. | 10-01-2009 |
| 20090243539 | RANDOM NUMBER GENERATOR IN A BATTERY PACK - Apparatus, method and computer program product are provided for battery management. In one implementation, a method of communication provided. The method includes enabling determining when a battery pack is coupled to a device, the battery pack including a battery management system. The method also includes generating a random number at the battery management system, the battery management system including battery monitoring circuitry, a processor, memory and a random number generator. The method includes using the random number to provide authentication and if authentication succeeds, enabling communication between the battery pack and the device. | 10-01-2009 |
| 20090240843 | APPARATUS FOR DETECTING A USB HOST - A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication with at least one of the plurality of transistors and the first and second leads. | 09-24-2009 |
| 20090238016 | CIRCUITS TO DELAY SIGNALS FROM A MEMORY DEVICE - Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other embodiments are described. | 09-24-2009 |
| 20090218698 | Wafer-Level Integrated Circuit Package with Top and Bottom Side Electrical Connections - A wafer-level, batch processed, die-sized integrated circuit (IC) package with both top and bottom side electrical connections is disclosed. In one aspect, a number of bonding wires can be attached to bond pads on the top side (active circuit side) of an IC wafer. Trenches can be formed in the wafer at scribe regions and the bonding wires can extend through the trench. The trench can be filled with coating material. The bonding wires can be partially exposed on the top and/or bottom sides of the wafer to distribute electrical connections from the bond pads to the top and/or bottom sides of the wafer. | 09-03-2009 |
| 20090216926 | APPARATUS TO IMPROVE BANDWIDTH FOR CIRCUITS HAVING MULTIPLE MEMORY CONTROLLERS - An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller. The second busy write output signal indicates when the second memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the second memory controller. | 08-27-2009 |
| 20090210774 | ERROR DETECTING/CORRECTING SCHEME FOR MEMORIES - A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation. | 08-20-2009 |
| 20090206480 | FABRICATING LOW COST SOLDER BUMPS ON INTEGRATED CIRCUIT WAFERS - A low cost method of forming solder bumps on an integrated circuit (IC) wafer includes depositing solder directly onto stud bumps formed on bond pads of the IC wafer. In some implementations, stud bumps are formed on the IC wafer by performing wire ball-bonding onto metal bond pads of the wafer. Photodefinable solder mask material is applied to the wafer and cured. The photodefinable solder mask material is exposed to form open solder mask areas at the metal bond pad areas. Solder paste is applied into the open solder mask areas. Reflowing the solder paste on the wafer forms solder bumps that wet to the stud bumps. The solder mask is then stripped from the wafer. Other processes (e.g., a wave-soldering machine, stencil or screen printing process) can also be used to wet solder onto stud bumps to form solder bumps. | 08-20-2009 |
| 20090206452 | METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE - A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided. | 08-20-2009 |
| 20090201615 | METHOD AND APPARATUS FOR ESD PROTECTION - A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit. | 08-13-2009 |
| 20090194804 | NON-VOLATILE MEMORY CELL - Disclosed herein are non-volatile cells and methods of manufacturing the same. The nonvolatile memory cells include a high voltage device, a low voltage device, and a memory cell formed on a semiconductor substrate. The high voltage device, low voltage device, and memory cell are all self-aligned by using the gates associated with each of the devices as a mask during formation of the respective sources and drains. | 08-06-2009 |
| 20090189159 | GETTERING LAYER ON SUBSTRATE - Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a device region is formed in the device layer having a depth that maintains a distance in the device layer between the gettering layer and the device region. | 07-30-2009 |
| 20090187770 | Data Security Including Real-Time Key Generation - Methods for providing data security are described. A security device ( | 07-23-2009 |
| 20090180611 | REPRESENTATION CHANGE OF A POINT ON AN ELLIPTIC CURVE - An elliptic curve cryptographic system where point coordinates are transformed from a first coordinate system to a second coordinate system. The transformed coordinates are processed by field operations, which have been modified for operating on the transformed point coordinates. In some implementations, the point coordinates are transformed from an affine coordinate system to a projective coordinate system using a non-random value for the projective coordinate. In some implementations, the transformed projective representation of the point can be changed from a first representation of the point in projective coordinates to a second representation of the point in projective coordinates, where the projective coordinate used in the representation change is a random value. | 07-16-2009 |
| 20090180609 | Modular Reduction Using a Special Form of the Modulus - A special form of a modulus and a modified Barrett reduction method are used to perform modular arithmetic in a cryptographic system. The modified Barrett reduction is a method of reducing a number modulo another number without the use of any division. By pre-computing static values used in the Barrett reduction method and by using a special form of the modulus, the calculation of reducing a number modulo another number can be reduced. This can result in a decrease in computation time, speeding up the overall cryptographic process. | 07-16-2009 |
| 20090168586 | CIRCUIT TO CONTROL VOLTAGE RAMP RATE - A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability. | 07-02-2009 |
| 20090166898 | Method of increasing reliability of packaged semiconductor integrated circuit dice - A method increases a reliability of packaged semiconductor integrated circuit dice by identifying one or more dice on a wafer having failed an electrical test. One or more failed dice are added to a character map. A first tier of buffer dice is added to the initial character map adjacent to each die on the character map. Both the failed dice and the first tier of buffer dice are indicated or marked, such as by inking, thereby indicating dice not requiring packaging. A wafer may include multiple die, with die corresponding to the die in the character map being marked. The marked die thus include die that have failed an electrical test plus die that may be likely to fail in the future due to their proximity to the failed die. | 07-02-2009 |
| 20090161429 | DYNAMIC COLUMN REDUNDANCY REPLACEMENT - A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits. For a program mode of operation, a multi-bit data program redundancy register stores actual redundant input data information and a FIFO register masks internal operations of the memory controller logic while a user is sending data. For a read mode of operation, actual redundant output information is stored in a multi-bit data read redundancy register such that, if a match is found, data from the shift register is replaced with redundant data bits and sent to the data output terminal to provide dynamic replacement of data bits from defective non-volatile memory cells. | 06-25-2009 |
| 20090158084 | Redundant Bit Patterns for Column Defects Coding - Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory array. The defective cell groups are later re-identified by checking the redundant bit pattern encoded in the cell groups. If new defective cell groups are identified, the memory array is identified as failing. If no new defective cell groups are identified, the memory array is identified as passing, and the identified defective cell groups are repaired. | 06-18-2009 |
| 20090153380 | CURRENT COMPENSATION FOR DIGITAL-TO-ANALOG CONVERTER - A current compensation circuit and an optimized current compensation circuit are disclosed for a Parallel Resistors Architecture (PRA) digital-to-analog converter (DAC). The circuits are used to balance code dependent current consumption of the PRA-DAC. | 06-18-2009 |
| 20090153232 | Low voltage charge pump - A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor. | 06-18-2009 |
| 20090150681 | Secure Software Download - Software can be downloaded securely using a multi-encryption method, where the decryption is completed when the software is executed. In one aspect, a multi-encrypted data item is received. One or more of the encryptions on the multi-encrypted data item is decrypted, yielding a partially decrypted data item. The partially decrypted data item is stored in a reserved portion of a storage medium. The partially decrypted data item is fetched from the storage medium and decrypted to yield the data item. The decryption can be performed using one or more circuits that implement multiple decryption processes, including multiple algorithm-key combinations. | 06-11-2009 |
| 20090146267 | SECURE CONNECTOR GRID ARRAY PACKAGE - Methods, systems, IC packages, and electrical devices for providing data security for ICs. A substrate-on-substrate connector grid array package with an electrical shield can protect sensitive information in a secure IC from being accessed by physical attacks. A current flow in the electrical shield can be monitored for disturbances which can indicate an attack on the IC package. | 06-11-2009 |
| 20090141554 | MEMORY DEVICE HAVING SMALL ARRAY AREA - Memory arrays can be implemented including word lines connected to memory transistors and corresponding select transistors. Each memory transistor is also connected to an array select transistor. Each select transistor is also connected to a bit line. The memory transistors are arranged such that they define bytes of data. A well line is connected to each portion of the semiconductor substrate that defines an array of bytes. | 06-04-2009 |
| 20090121965 | SPHERICAL ANTENNA - An antenna comprises a first circular coil, a second circular coil, and a third circular coil, and a housing unit including a sending/receiving interrogator chip. The first, second, and third coil are each connected to the housing unit at two points on each of the first, second, and third coil, and the first, second, and third coil are connected substantially in parallel. | 05-14-2009 |
| 20090114951 | MEMORY DEVICE - A memory device can be implemented including word lines connected to an array of memory transistors. Each memory transistor is also connected to bit lines and a select transistor. The select transistors each have their sources connected to a conductive source line, by a shunt and the gate of each select transistor is connected to a select line. | 05-07-2009 |
| 20090109754 | NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES - In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines. | 04-30-2009 |
| 20090096532 | DIFFERENTIAL AMPLIFIER WITH SINGLE ENDED OUTPUT - Various embodiments for converting a differential signal to a single ended signal are disclosed. The embodiments comprise a transistor pair for receiving a differential signal; and a tank circuit coupled to the transistor pair. The tank circuit includes a first inductor and one or more capacitors. The embodiments also include a second inductor magnetically coupled to the first inductor to form a balanced/unbalanced inductor (BIMI) arrangement. The BIMI arrangement directly converts the differential signal to a single ended signal. | 04-16-2009 |
| 20090096501 | APPARATUS AND METHOD FOR PREVENTING SNAP BACK IN INTEGRATED CIRCUITS - A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on. | 04-16-2009 |
| 20090086541 | COLUMN REDUNDANCY RAM FOR DYNAMIC BIT REPLACEMENT IN FLASH MEMORY - A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip. | 04-02-2009 |
| 20090077409 | CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE - A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit. | 03-19-2009 |
| 20090073781 | Sense Amplifier - A single ended sense amplifier circuit is disclosed that is operable to measure a state of a memory cell. The amplifier can track and compensate for variations in cell current via feedback to maintain precision. The amplifier can be used with low supply voltages while still providing high-speed operation. | 03-19-2009 |
| 20090073283 | METHOD AND APPARATUS FOR CAPTURING IMAGES - In a production system including a plurality of imaging devices associated with a respective production tool, an image capture unit, a controller, and an image storage unit, an image capturing method and apparatus is disclosed. The imaging device records the image and transmits the image to the image capture unit. The image capture unit processes the received image and stores the processed image in the image storage unit. | 03-19-2009 |
| 20090072889 | Charge Pump - An improved charge pump design useful in low power applications derives an alternative voltage from a supply voltage. The design can be constructed using PMOS manufactured according to standard processes such that triple well manufacturing processes are not required. The design can incorporate control gate circuitry to increase efficiency and decrease degradation due to the threshold voltage of the transistors used. | 03-19-2009 |
| 20090058697 | METHOD AND SYSTEM FOR MINIMIZING THE ACCUMULATED OFFSET ERROR FOR AN ANALOG TO DIGITAL CONVERTER - A method and system utilized with an analog to digital converter is disclosed. The method and system comprise providing a first conversion on an input signal. In the first conversion, an offset error is added to the input signal to provide a first result. The method and system further includes providing a second conversion on the input signal. In the second conversion, an offset error is subtracted from the input signal to provide a second result. The first and second results are then combined to substantially remove the offset error. A system and method in accordance with the present invention compensates for the accumulated offset error over many samples, thereby achieving much higher accuracy in the offset error compensation. | 03-05-2009 |
| 20090058595 | Biometric Control Device - Systems and methods for a biometric control device. Actuation of a control device can include direction information which can be used to generate a control signal associated with the actuation. Control signals can facilitate user functions on a recipient device. | 03-05-2009 |
| 20090058459 | AUTO-TRIM CIRCUIT - An auto-trim circuit that sets trim bits for an integrated circuit includes a coarse bit calibration circuit for determining a first portion of the trim bits as a set of coarse bits, and a fine bit calibration circuit for determining a second portion of the trim bits as a set of fine bits wherein said fine bits. | 03-05-2009 |
| 20090043836 | METHOD AND SYSTEM FOR LARGE NUMBER MULTIPLICATION - Methods, apparatus and systems for large number multiplication. A multiplication circuit is provided to compute the product of two operands (A and B), at least one of which is wider than a width associated with the multiplication circuit. Each of the operands includes contiguous ordered word-wide operand segments (A | 02-12-2009 |
| 20090041229 | Elliptic Curve Point Transformations - In an elliptic curve cryptographic system, point coordinates in a first coordinate system are transformed into a second coordinate system. The transformed coordinates are processed by field operations, which have been modified for operating on the transformed point coordinates. In some implementations, the point coordinates are transformed using a linear transformation matrix having coefficients. The coefficients can be fixed, variable or random. In some implementations, the transformation matrix is invertible. | 02-12-2009 |
| 20090040825 | NOVEL ROW REDUNDANCY SCHEME IN A MULTICHIP INTEGRATED MEMORY - Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time. | 02-12-2009 |
| 20090019207 | DUAL BUS MATRIX ARCHITECTURE FOR MICRO-CONTROLLERS - A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix. | 01-15-2009 |
| 20090016523 | Masking and Additive Decomposition Techniques for Cryptographic Field Operations - Masking and additive decomposition techniques are used to mask secret material used in field operations (e.g., point multiplication operations) performed by cryptographic processes (e.g., elliptic curve cryptographic processes). The masking and additive decomposition techniques help thwart “side-channel” attacks (e.g., power and electromagnetic analysis attacks). | 01-15-2009 |
| 20080315848 | VOLTAGE REGULATOR FOR AN INTEGRATED CIRCUIT - A voltage regulator is disclosed. The voltage regulator includes a comparator for providing a gated output signal; and a state machine for receiving the gated output signal. The voltage regulator further includes at least one switch cell controlled by the state machine, for delivering charge to a load. Accordingly, a voltage regulator in accordance with the present invention yields N times (where N is an integer greater than one) the linear efficiency over typical linear regulators without requiring any external components. Therefore improved regulator efficiency is provided for low power devices. | 12-25-2008 |
| 20080313582 | Accurate Transistor Modeling - A method and system for generating transistor models. In one embodiment, the method includes generating a transistor model that characterizes a topology of a circuit, and characterizes at least one coupling or at least one interaction between at least two transistors of the circuit. | 12-18-2008 |
| 20080304191 | THRESHOLD VOLTAGE METHOD AND APPARATUS FOR ESD PROTECTION - An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground. | 12-11-2008 |
| 20080301433 | Secure Communications - The subject matter of this specification can be embodied in, among other things, an apparatus that includes a verification module to provide information used to identify a user of the apparatus, a memory for storing information used for securing communications transmitted to a remote device, a processing unit for generating a secured communication based on the stored information, and an interface to communicate with a peripheral interface of a host device. The host device configured to transmit the secured communication to the remote device without accessing content of the secured communication. | 12-04-2008 |
| 20080298385 | DEVICE AND METHOD OF SUPPLYING POWER TO TARGETS ON SINGLE-WIRE INTERFACE - A single-wire interface communication system is capable of providing both electrical communication of signals and power between devices coupled to the system. Coupled to the single-wire interface is at least one target device which contains a PMOS transistor, a charge storage device, an inverter controlling the PMOS transistor, and a target device function. The charge storage device provides power to the target device function and to the inverter. The PMOS transistor receives power from the single-wire interface at a power-supply voltage level and charges the charge storage device to the same level. Non-communication periods produce a charging period sufficient for the charge storage device to attain the power-supply voltage level. | 12-04-2008 |
| 20080290955 | LOW COST AND LOW VARIATION OSCILLATOR - An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements. | 11-27-2008 |
| 20080290930 | LOW VOLTAGE CHARGE PUMP - A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor. | 11-27-2008 |
| 20080290904 | Frequency Monitor - A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step. | 11-27-2008 |
| 20080290426 | DMOS DEVICE WITH SEALED CHANNEL PROCESSING - A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step. | 11-27-2008 |
| 20080286967 | METHOD FOR FABRICATING A BODY TO SUBSTRATE CONTACT OR TOPSIDE SUBSTRATE CONTACT IN SILICON-ON-INSULATOR DEVICES - A method of forming an electrical contact between an active semiconductor device layer and a base substrate. The method includes forming a first masking layer over an uppermost surface of the active semiconductor layer, patterning a window in the masking layer, and etching an opening down to the base substrate within an area defined by the window. The opening is filled with a semiconductor contact material while simultaneously adding a dopant to the semiconductor contact material thereby forming an electrical contact between the active semiconductor device layer and the base substrate. | 11-20-2008 |
| 20080285326 | HIGH DENSITY NON-VOLATILE MEMORY ARRAY - A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines. | 11-20-2008 |
| 20080284383 | Charge Detector - The subject matter of this specification can be embodied in, among other things, an apparatus that includes a battery system, which includes at least one cell and a charge enable device to couple the at least one cell to a charging voltage. The apparatus also includes an excessive voltage detector to output a signal to control the charge enable device. The signal prevents charging of the at least one cell if an excessive charging voltage is detected based on an activation of a clamping component. | 11-20-2008 |
| 20080280439 | OPTIMAL CONCENTRATION OF PLATINUM IN A NICKEL FILM TO FORM AND STABILIZE NICKEL MONOSILICIDE IN A MICROELECTRONIC DEVICE - A method of forming a nickel monosilicide layer on silicon-containing features of an electronic device that includes depositing a nickel film over the silicon-containing features. The nickel film is co-deposited with a selected material. The selected material has an atomic percentage in a range of about 10% to 25%. A single anneal step is then applied to the nickel film thus directly forming the nickel monosilicide layer. | 11-13-2008 |
| 20080279320 | BI-DIRECTIONAL SINGLE WIRE INTERFACE - A single-wire, bi-directional communication protocol is provided in which the sending device transmits its clock frequency and its bit transmission period and data through a predefined waveform pattern or “learning sequence” that is recognizable by the receiving device and in a period of time, as measured in number of sending clock cycles, that is known to the receiving device. By clocking the full length of the predefined waveform pattern using its own internal clock, the receiving device becomes aware of the bit transmission period of the sending device. | 11-13-2008 |
| 20080277482 | Managing Power and Timing in a Smart Card Device - In some implementations, a mobile device includes a first interface configured to communicably couple to a removable integrated circuit card; a second interface configured to wirelessly communicate with a contactless reader that is external to the mobile device; a communication interface that couples the first interface and the second interface and that is configured to obtain information from an integrated circuit card that is coupled to the first interface in response to receipt by the second interface of an information request from the contactless reader; and a programmable timer that is configured to be started in response to the second interface receiving an information request from the contactless reader, and that is further configured to, upon reaching a programmed value, cause the second interface to transmit the obtained information to the contactless reader. | 11-13-2008 |
| 20080276051 | Configurable Memory Protection - A method can include receiving a signal associated with an attempted access to data that is stored at a specific location in memory; obtaining a selection value that selects which memory protection register of multiple alternative memory protection registers is to provide a memory protection attribute for the specific location in memory; obtaining, from the selected memory protection register, a memory protection attribute; and controlling access to the specific location in memory based on the obtained memory protection attribute. | 11-06-2008 |
| 20080276035 | Wear Leveling - A reference memory location can be designated in a memory device. A memory location can be designated in response to storing data in the memory device. If the identified memory location is associated with the reference memory location then an allocated memory location can be designated relative to the reference memory location, and the allocated memory location can be leveled. | 11-06-2008 |
| 20080272720 | ACCURATE MOTOR SPEED CONTROL - A method of and system for controlling a brushless direct current (BLDC) motor includes providing with a lookup table a predetermined corresponding desired revolution time (DRT) for the BLDC motor for an ambient temperature. A Hall device is used to measure an actual revolution time (RT) of the BLDC motor. DRT and RT are compared to change duration of a pulse width modulation (PWM) signal in response to the comparison result. The PWM signal is applied to one of two BLDC motor windings. | 11-06-2008 |
| 20080270667 | SERIALIZATION OF DATA FOR COMMUNICATION WITH MASTER IN MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization. | 10-30-2008 |
| 20080270656 | SERIALIZATION OF DATA FOR COMMUNICATION WITH DIFFERENT-PROTOCOL SLAVE IN MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a system including bus communication to a slave includes a bridge operative to interface a first bus protocol to a bus matrix that uses a second bus protocol. A first serializer coupled to the bridge serializes information received from the bridge and sends the serialized information over a communication bus. A second serializer coupled to the communication bus receives the serialized information and deserializes the serialized information. A slave uses the first protocol and is coupled to the second serializer, where the deserialized information is provided to the slave, and the slave provides a response to the information from the bridge. | 10-30-2008 |
| 20080270655 | SERIALIZATION OF DATA FOR COMMUNICATION WITH SLAVE IN MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization. | 10-30-2008 |
| 20080270650 | SERIALIZATION OF DATA FOR MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a system includes a matrix operative to select destinations for information on buses connected to the matrix. A first serializer provided on a first device serializes information received from the matrix and sends the serialized information over a communication bus. A second serializer provided on a second device receives the serialized information and deserializes the serialized information, where the deserialized information is provided to a peripheral provided on the second device. | 10-30-2008 |
| 20080266982 | CHANNEL DISCHARGING AFTER ERASING FLASH MEMORY DEVICES - A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise. | 10-30-2008 |
| 20080266301 | DISPLAY CONTROLLER OPERATING MODE USING MULTIPLE DATA BUFFERS - A display controller unit for controlling a display on a display panel comprises a first set of registers to hold data to be displayed and a second set of registers loadable from the first set of registers. A set of multiplexers has first data inputs coupled to the first set of registers, second data inputs coupled to the second set of registers, and select inputs. Logic circuitry is coupled to the output of the set of multiplexers and to the control inputs of the multiplexers, the control circuitry providing select information to the set of multiplexers and providing waveforms to the display panel to selectively display data from the first set of registers and the second set of registers in accordance with the select information. | 10-30-2008 |
| 20080266001 | DUAL REFERENCE PHASE TRACKING PHASE-LOCKED LOOP - A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain. | 10-30-2008 |
| 20080259712 | FAST READ PORT FOR REGISTER FILE - Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response. | 10-23-2008 |
