| ATI Technologies ULC Patent applications |
| Patent application number | Title | Published |
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| 20120131596 | Method and System for Synchronizing Thread Wavefront Data and Events - Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed. | 05-24-2012 |
| 20120127689 | INTEGRATED PACKAGE CIRCUIT WITH STIFFENER - The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. | 05-24-2012 |
| 20120127367 | METHOD AND APPARATUS FOR PROVIDING TEMPORAL IMAGE PROCESSING USING MULTI-STREAM FIELD INFORMATION - An apparatus and method provides temporal image processing by producing, for output on a single link such as a single cable or wireless interface, packet based multi-steam information wherein one stream provides at least frame N information for temporal imaging processing and a second stream that provides frame N−1 information for the same display, such as a current frame and a previous frame or a current frame and next frame. The method and apparatus also outputs the packet based multi-stream information and sends it for the same display for use by the same display so that the receiving display may perform temporal image processing using the multi-stream multi-frame information sent with a single link. | 05-24-2012 |
| 20120110309 | Data Output Transfer To Memory - Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a memory includes: forming, based upon one or more of the outputs, a combined memory export instruction comprising one or more data elements and one or more control elements; and sending the combined memory export instruction to the memory. The combined memory export instruction can be sent to memory in a single clock cycle. Another method includes: forming, based upon outputs from two or more of the threads, a memory export instruction comprising two or more data elements; embedding at least one address representative of the two or more of the outputs in a second memory instruction; and sending the memory export instruction and the second memory instruction to the memory. | 05-03-2012 |
| 20120096218 | APPARATUS AND METHODS FOR TUNING A MEMORY INTERFACE - The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device. | 04-19-2012 |
| 20120075353 | System and Method for Providing Control Data for Dynamically Adjusting Lighting and Adjusting Video Pixel Data for a Display to Substantially Maintain Image Display Quality While Reducing Power Consumption - System and method for providing control data for dynamically adjusting lighting and adjusting video pixel data for a display to substantially maintain image display quality while reducing power consumption. In accordance with one or more embodiments, image statistics, e.g., histogram data representing luma values corresponding to pixels for a video frame, are analyzed to determine whether the pixels represent one or more of a plurality of images which includes an image containing primarily natural imagery, an image containing primarily graphics imagery, and an image containing a combination of at least respective portions of natural and graphics imagery. Based on such analysis, control data are provided to enable light source brightness reduction by one of a plurality of percentages and pixel brightness increases, e.g., in accordance with one of a plurality of multiple-segment piecewise linear curves defined in accordance with respective segment slopes, thresholds, and threshold offsets in accordance with whether the incoming pixel data primarily represents a natural image, primarily represents a graphics image, or represents a combination of natural and graphics images. | 03-29-2012 |
| 20120070094 | VARIABLE-LENGTH CODE DECODER - An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers. | 03-22-2012 |
| 20120066640 | APPARATUS FOR PROVIDING MULTI-MODE WARPING OF GRAPHICAL USER INTERFACE OBJECTS - Apparatus provides for providing multi-mode warping of graphical user interface (GUI) objects, such as but not limited to a pointing object (e.g., cursor) and a window. In one example, the apparatus includes logic operative to provide a user interface that allows a user to select different warping modes. In one example, a user may select a pointing object warping mode and/or a window warping mode. In the pointing object warping mode, the apparatus applies a warp operation to one or more pointing objects that uses display content information to determine where to move the pointing object. In the window warping mode, the apparatus applies a warp operation to one or more windows that also uses display content information to determine where to move the window. The destination position of the GUI object is determined based on content identification information associated with display content such as name, serial number or label that identifies the display content. | 03-15-2012 |
| 20120066624 | METHOD AND APPARATUS FOR CONTROLLING MOVEMENT OF GRAPHICAL USER INTERFACE OBJECTS - A method and apparatus provides for controlling movement of one or more graphical user interface (GUI) objects such as a cursor and/or a window. In one example, the method and apparatus applies a warp operation to the GUI object that uses display content information to determine where to move the cursor and/or window. The destination position of the GUI object is determined based on content identification information associated with display content such as name, serial number or label that identifies the display content. The display content may be any visible object to be displayed on the display screen, including but is not limited to, windows, taskbars, sidebars, docks, program launchers, icons, controls, and background (wallpaper). The warp operation may be an immediate relocation of the GUI object to the destination position without any user intervention during the relocation. | 03-15-2012 |
| 20120047526 | System and Method for Mapping Audio and Video Streams from Audio/Video Source to Multiple Audio/Video Sinks - System and method for mapping audio and video streams from an audio/video (AV) source to respective ones of a plurality of AV sinks. In accordance with one or more embodiments, the audio and video playback and content protection capabilities of each one of the AV sinks are determined based on AV data received via a video channel interface from each one of the AV sinks. Also determined are the audio and video streams available from the AV source. Respective ones of the audio and video streams available from the AV source are mapped to each one of the AV sinks in accordance with their audio and video playback and content protection capabilities. | 02-23-2012 |
| 20120038835 | STAND-BY MODE TRANSITIONING - A device for rapidly instituting an active mode of a digital-television enabled system, the system including a first, volatile memory configured to load and store software instructions, includes: an input configured to receive first digital audio and video information; a first output configured to convey second audio and information toward a display regarding the first audio and video information; at least one second output configured to convey commands to, and receive information from, the first memory; and a processor configured to perform functions in accordance with software instructions stored in first and second memories and to cause the first memory to load software instructions for provision to the processor such that first instructions for processing at least one of the first audio information and the first video information are loaded and stored by the first memory with a higher priority than second instructions for performing other functionality. | 02-16-2012 |
| 20120030488 | METHOD AND APPARATUS FOR INDICATING MULTI-POWER RAIL STATUS OF INTEGRATED CIRCUITS - Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit. The multi-power rail status indicating logic may include a synchronous assertion/asynchronous de-assertion multi-power rail status signal generator that receives the clock signal and the asynchronous multi-power rail voltage stability signal, and in response to of the assertion of the asynchronous multi-power rail voltage stability signal, synchronizes the asynchronous multi-power rail voltage stability signal with the clock signal to assert the multi-power rail status signal. | 02-02-2012 |
| 20120025870 | METHOD AND APPARATUS FOR VOLTAGE LEVEL SHIFTING WITH CONCURRENT SYNCHRONIZATION - Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal. | 02-02-2012 |
| 20120019543 | MULTI-THREAD GRAPHICS PROCESSING SYSTEM - A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads. | 01-26-2012 |
| 20120017118 | METHOD AND APPARATUS FOR TESTING AN INTEGRATED CIRCUIT INCLUDING AN I/O INTERFACE - Methods and apparatus provide for testing an integrated circuit including an input/output (I/O) interface. The method and apparatus place the I/O interface in a test mode by test enabling logic. During the test mode, the method and apparatus also provide, by a clock generator in the I/O interface, an internal phase-aligned receiver clock signal to a plurality of transceivers in the I/O interface. The clock generator is a transmitter portion of one of the plurality of transceivers in the I/O interface. The method and apparatus then monitor for errors in loopback data from the plurality of transceivers in the I/O interface by an automatic test equipment (ATE). The phase of the internal phase-aligned receiver clock signal is aligned with the loopback data of the plurality of transceivers, and the frequency of the internal phase-aligned receiver clock signal may be above about 200 MHz. | 01-19-2012 |
| 20120002873 | METHOD AND APPARATUS FOR BLOCK BASED IMAGE COMPRESSION WITH MULTIPLE NON-UNIFORM BLOCK ENCODINGS - Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks. | 01-05-2012 |
| 20120001925 | Dynamic Feedback Load Balancing - A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating. | 01-05-2012 |
| 20120001905 | Seamless Integration of Multi-GPU Rendering - A computer based rendering system is provided. The computer based rendering system includes an abstraction mechanism to provide configuring instructions to two or more processors, the configuring instructions being operative to facilitate scene rendering. The configuring provides processor setup instructions to at least one driver. Each of the two or more processors renders a respective portion of the scene independent of the other of the processors. | 01-05-2012 |
| 20110320890 | DATA TRANSMISSION APPARATUS WITH INFORMATION SKEW AND REDUNDANT CONTROL INFORMATION AND METHOD - Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed. | 12-29-2011 |
| 20110279156 | PROGRAMMABLE FINE LOCK/UNLOCK DETECTION CIRCUIT - An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition. | 11-17-2011 |
| 20110268425 | POWER MANAGEMENT IN MULTI-STREAM AUDIO/VIDEO DEVICES - A method of managing power consumption in a video device capable of displaying encoded multi-stream video is disclosed. Power reduction is achieved by limiting the amount of video and audio decoding and processing performed on at least some of the encoded streams, by taking particular application contexts into account. In a normal power consumption mode, audio/video data from all streams are decoded and digitally processed for output. In response to detecting a reduced power consumption mode, audio/video from at least some of the streams are processed in a modified manner to reduce power consumption. | 11-03-2011 |
| 20110255002 | METHOD AND APPARATUS FOR DISPLAY OF A DIGITAL VIDEO SIGNAL - A method and apparatus for display of a digital video signal includes a demodulator capable of receiving a major channel of the digital video signal. The major channel of the digital video signal includes one or more minor channels, wherein the minor channels are specific and separate channels of broadcast information. The method and apparatus for display of a digital video signal further includes decoders coupled to the demodulator, wherein the decoders receive the minor channels disposed within the major channel. The decoders thereupon generate minor channel video signals, wherein the minor channel video signal includes the video information for each associated channel. The method and apparatus further includes receiving the incoming video signals and format the video signals for simultaneous display of active video from multiple channels. A display configurator provides the minor channel video signals to an output display, to actively display the minor channels. | 10-20-2011 |
| 20110254154 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 10-20-2011 |
| 20110242142 | MULTIPLE DISPLAY CHROMINANCE AND LUMINANCE METHOD AND APPARATUS - An apparatus includes a chrominance and luminance module. The chrominance and luminance module obtains display characteristics of each of a plurality of displays. The chrominance and luminance module selectively adjusts, on a per display basis, chrominance and luminance for each of the displays based on the display characteristics. In one example, the displays collectively display a single large surface. | 10-06-2011 |
| 20110225813 | METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS - A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials. | 09-22-2011 |
| 20110219190 | CACHE WITH RELOAD CAPABILITY AFTER POWER RESTORATION - A method and apparatus for repopulating a cache are disclosed. At least a portion of the contents of the cache are stored in a location separate from the cache. Power is removed from the cache and is restored some time later. After power has been restored to the cache, it is repopulated with the portion of the contents of the cache that were stored separately from the cache. | 09-08-2011 |
| 20110216077 | GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER - A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer. | 09-08-2011 |
| 20110215823 | APPARATUS AND METHOD FOR MONITORING CURRENT FLOW TO INTEGRATED CIRCUIT IN TEMPERATURE-COMPENSATED MANNER - A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate. | 09-08-2011 |
| 20110211074 | FIELD SEQUENCE DETECTOR, METHOD AND VIDEO DEVICE - A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences. | 09-01-2011 |
| 20110164065 | Method And Apparatus For Configuring Display Bezel Compensation For A Single Large Surface Display Formed By A Plurality Of Displays - A method includes displaying, on a single large surface display, a first moveable and second fixed portion of a visual test object. The first portion is displayed on the display to be configured and the second portion is displayed on at least one neighboring display, and are shown in a relative orientation adjacent to a common border formed by a first bezel of the display to be configured and a second bezel of the at least one neighboring display, and any space in between. The method obtains bezel compensation configuration information in response to input aligning the first portion with the second portion. A user may provide input by moving the first portion to align it with the second portion so that a third portion of the visual test object appears hidden by the common border. The object therefore appears aligned “behind” the bezel. | 07-07-2011 |
| 20110161547 | METHOD AND DEVICE FOR DISABLING A HIGHER VERSION OF A COMPUTER BUS AND INTERCONNECTION PROTOCOL FOR INTEROPERABILITY WITH A DEVICE COMPLIANT TO A LOWER VERSION OF THE COMPUTER BUS AND INTERCONNECTION PROTOCOL - A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol. | 06-30-2011 |
| 20110157302 | THREE-DIMENSIONAL VIDEO DISPLAY SYSTEM WITH MULTI-STREAM SENDING/RECEIVING OPERATION - A three-dimensional processing circuit includes a multi-stream 3D image sender that produces packet based multi-stream information that includes a first stream that has first eye view information, such as left eye frame information and a second stream that includes corresponding second eye view information, such as right eye frame information, for display on a single display, wherein each stream comprises a same object viewed from differing view perspectives. In one example, the multi-stream information is communicated as packetized data over a single cable, for example wherein a packet includes both the left eye and right eye information. In addition, the encoder provides as part of the multi-stream information, control information indicating that the first and second streams are for a single display. In one example, the multi-streams are communicated concurrently so that the single display can display stereoscopic left and right eye frame information. A corresponding receiver is also disclosed that decodes the packet based multi-stream information and combines the decoded left eye frame information and corresponding right eye information for a 3D viewing effect. In one example this may be based on control information associated with the packet based multi-stream information. Related methods are also set forth. | 06-30-2011 |
| 20110156753 | DUAL LOOP LEVEL SHIFTER - A method and apparatus are disclosed to control one or more input output (I/O) pads. An input signal is translated to an output signal having a desired logic level using a first latch loop. The state of the first latch loop is maintained by a second latch loop, integrated with the first latch loop, when a latching indication is received. The integration between the first latch loop and the second latch loop is such that the second latch loop creates an input-output connection if transmission gates in the second latch loop are conductive, and disables the input-output connection if the transmission gates are not conductive. | 06-30-2011 |
| 20110148899 | Image Quality Configuration Apparatus, System and Method - A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed. | 06-23-2011 |
| 20110145622 | DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHOD FOR SWITCHING THE CLOCK SPEED - A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports. | 06-16-2011 |
| 20110144970 | Apparatus and method for partitioning a display surface into a plurality of virtual display areas - A method and apparatus that partitions a single display's viewable area into at least two virtual viewable areas, and emulates the at least two virtual viewable areas as at least two emulated physical displays with an operating system such that the operating system behaves as if interfacing with at least two actual independent physical displays. The method provides the operating system with generated display identification data (such as “EDID”) for each of the emulated physical displays in response to a query from the operating system. The method and apparatus also receive notification of an interrupt (where the interrupt corresponds to the single physical display), and reports to the operating system with at least two sets of interrupt reporting information, corresponding to the at least two emulated physical displays, as if two interrupts were received. The operating system is thereby “faked” into acting as if two physical displays are in operation. | 06-16-2011 |
| 20110116656 | PULSE CODE MODULATION CONVERSION CIRCUIT AND METHOD - A circuit includes an enhanced frequency range linear pulse code modulation conversion circuit. The enhanced frequency range linear pulse code modulation conversion circuit is driven by a clock signal within a frequency range. The enhanced frequency range linear pulse code modulation conversion circuit provides enhanced frequency range linear pulse code modulated information. More specifically, the enhanced frequency range linear pulse code modulation conversion circuit is provided by selectively decimating and interpolating non-enhanced frequency range linear pulse code modulated information based on a desired output sampling frequency and the frequency range. | 05-19-2011 |
| 20110115524 | Logic Cell Having Reduced Spurious Toggling - A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state. | 05-19-2011 |
| 20110102383 | INTEGRATED CIRCUIT WITH IMPROVED LEVEL SHIFTER - Level shifting circuitry and corresponding enable signal generating circuitry provides improved leakage current control while eliminating the need for supplying reference voltage input in the enable signal generator. The level shifting circuitry is a type of cascode free level shifting circuit that does not include cascode transistors as in the prior art but instead utilizes cross coupled logic to provide level shifting while also utilizing enable signal controlled transistors to control leakage current through the cross coupled logic during power up sequencing. The level shifting circuitry provides improved leakage current limiting structure for power up sequencing whether a lower level supply voltage ramps up faster than the higher level supply voltage or vice a versa. | 05-05-2011 |
| 20110099407 | Apparatus for High Speed Data Multiplexing in a Processor - A processer, for example a field programmable gate array (FPGA), comprises input/output (I/O) logic including timing adjustment logic operative to synchronize a time division multiplexed (TDM) line of the I/O logic using an a priori known test pattern. The timing adjustment logic may include clock cycle data alignment logic operative to adjust data on the TDM line by increments of a clock cycle to match it to an a priori known test pattern, and skew logic operative to prevent leading or trailing edges of the data from aligning with edges of a clock pulse leading or trailing edge. The I/O logic may be a Serializer/Deserializer (SerDes) logic that includes a state machine operative to control the clock cycle data alignment logic and skew logic to adjust and synchronize the data with the known test pattern. | 04-28-2011 |
| 20110096079 | Method and System for Displya Output Stutter - Apparatus and methods for reducing power consumption of a data transfer interface in a computer system are disclosed. In one embodiment, a method for reducing power consumption of a data transfer interface between a first device and a second device, includes, identifying a free interval between a first data and a second data, disabling the data transfer interface during the free interval, enabling the data transfer interface at the end of the free interval, and transmitting the second data. The method may also include a step of notifying the second device that the data transfer interface is being temporarily disabled. Another embodiment, for example, includes the transfer of display data (or video frames) over an interface, such as, a DisplayPort interface, between a graphics controller device and a timing controller device in a computer system. | 04-28-2011 |
| 20110095415 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 04-28-2011 |
| 20110068632 | INTEGRATED CIRCUIT ADAPTED TO BE SELECTIVELY AC OR DC COUPLED - An integrated circuit is adapted to be selectively AC or DC coupled to an external device at a coupling point. The integrated circuit includes a first connector connected to the coupling point by way of a coupling capacitor for AC coupling, a second connector connected to the coupling point for DC coupling, and a switch to selectively short the first and second connectors and thereby the coupling capacitor, when the integrated circuit is DC coupled to the device. The switch may be a MOSFET bridge comprising a switch control MOSFET interconnected between the first and second connectors, with the switch control MOSFET receiving at its gate a mode status signal for turning on the switch control MOSFET and thereby shorting the MOSFET bridge when the integrated circuit is DC coupled to the external device. The MOSFET bridge also includes a number of dynamically biased nMOSFETs connected in series with the switch control MOSFET in order to protect switch control MOSFET from high external supply voltages, and a number of dynamically biased pMOSFETs connected in parallel with the switch control MOSFET. | 03-24-2011 |
| 20110066778 | METHOD AND APPARATUS FOR TRANSPORTING AND INTEROPERATING TRANSITION MINIMIZED DIFFERENTIAL SIGNALING OVER DIFFERENTIAL SERIAL COMMUNICATION TRANSMITTERS - A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge. | 03-17-2011 |
| 20110063308 | DISPLAY SYSTEM WITH FRAME REUSE USING DIVIDED MULTI-CONNECTOR ELEMENT DIFFERENTIAL BUS CONNECTOR - A method includes reducing power of a first graphics processor by disabling or not using its rendering engine and leaving a display engine of the same first graphics processor capable of outputting display frames from a corresponding first frame buffer to a display. A display frame is rendered by a second graphics processor while the rendering engine of the first graphics processor is in a reduced power state, such as a non-rendering state. The rendered frame is stored in a corresponding second frame buffer of the second graphics processor, such as a local frame buffer and copied from the second frame buffer to the first frame buffer. The copied frame in the first frame buffer is then displayed on a display while the rendering engine of the first graphics processor is in the reduced power state. Accordingly thermal output and power output is reduced with respect to the first graphics processor since it does not do frame generation using its rendering engine, it only uses its display engine to display frames generated by the second graphics processor. | 03-17-2011 |
| 20110060928 | Method and Apparatus for Disabling a Device - A method of operating a device is provided. The method includes transitioning the GPU to a substantially disabled state in response to a first received signal, and generating, while the GPU is in the substantially disabled state, a response signal in response to a second received signal. The response signal is substantially similar to a second response signal that would be generated by the GPU in a powered state in response to the second received signal. | 03-10-2011 |
| 20110060924 | Power Management in Multi-GPU Systems - A method of power management is provided. The method includes detecting an event, assign a first responsibility to a first graphics processing unit (GPU) and a second responsibility to second GPU, and changing a power state of the first and second GPUs based on the first and second responsibilities, respectively. The first responsibility is different from the second responsibility. | 03-10-2011 |
| 20110060847 | METHOD AND APPARATUS FOR TRANSPORTING AND INTEROPERATING TRANSITION MINIMIZED DIFFERENTIAL SIGNALING OVER DIFFERENTIAL SERIAL COMMUNICATION TRANSMITTERS - A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge. | 03-10-2011 |
| 20110057940 | Processing Unit to Implement Video Instructions and Applications Thereof - Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data. | 03-10-2011 |
| 20110057939 | Reading a Local Memory of a Processing Unit - Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit. | 03-10-2011 |
| 20110057936 | Managing Resources to Facilitate Altering the Number of Active Processors - A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU. | 03-10-2011 |
| 20110050734 | Method and Apparatus for Providing Reduced Power Usage of a Display Interface - A method detects by a display driver logic, inactivity between the display driver logic and a display logic, and deactivates an auxiliary channel by the display driver logic, wherein the auxiliary channel is between the display driver logic and the display logic. The method also detects, by the display driver logic via the auxiliary channel, a required operating mode capability of a display; and determines a minimum number of connection lines needed between the display driver logic and the display logic, to operate the display in the required operating mode capability. A display driver logic includes a connection port suitable for operative connection to a display logic, wherein the display drive logic is operative to detect inactivity between the display driver logic and the display logic, and deactivate an auxiliary channel between the display driver logic and the display logic. | 03-03-2011 |
| 20110050709 | PIXEL CLOCKING METHOD AND APPARATUS - An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals. | 03-03-2011 |
| 20110050314 | DISPLAY LINK CLOCKING METHOD AND APPARATUS - An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals. | 03-03-2011 |
| 20110047489 | METHOD AND APPARATUS FOR CONFIGURING A PLURALITY OF DISPLAYS INTO A SINGLE LARGE SURFACE DISPLAY - A method is disclosed that provides, by mapping logic, output to a selected display of a plurality of displays forming an arrangement, where the selected display provides a visual indication in response to the output. The visual indication indicates that the selected display is ready to be mapped to an image data portion corresponding to the selected display's physical position within the arrangement. The method maps the image data portion to the selected display. The image data portion is stored in a frame buffer, and is mapped in response to input indicating the selected display's physical position. The frame buffer stores a single large surface image as a plurality of image data portions, where each image data portion is mapped to a corresponding display of the plurality of displays. An apparatus is also disclosed, that operates in accordance with the method. | 02-24-2011 |
| 20110045706 | ELECTRICAL CONNECTOR, CABLE AND APPARATUS UTILIZING SAME - An electrical connector, such as a circuit board connector, includes a first group or subassembly of electrical contacts physically separate from an adjacent and second group or subassembly of contacts. The first group of electrical contacts and second group of electrical contacts each include a row of lower contacts and upper contacts. The second group of electrical contacts has an identical but mirrored configuration as the first group of electrical contacts. | 02-24-2011 |
| 20110043514 | METHOD AND APPARATUS FOR MULTIPLE DISPLAY SYNCHRONIZATION - A circuit includes a plurality of display path circuits and a timing and frame synchronization circuit. The timing and frame synchronization circuit aligns a first blanking interval of first timing information provided by a first of the display path circuits for a first display based on a second blanking interval of second timing information provided by a second of the display path circuits for a second display. | 02-24-2011 |
| 20110032018 | IN-RUSH/OUT-RUSH CURRENT LIMITING CIRCUIT AND DEVICES CONTAINING SAME - An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure. | 02-10-2011 |
| 20110024898 | METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS - A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials. | 02-03-2011 |
| 20110001535 | SEQUENTIAL CIRCUIT WITH DYNAMIC PULSE WIDTH CONTROL - A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit. | 01-06-2011 |
| 20100322318 | VIDEO DECODER WITH REDUCED POWER CONSUMPTION AND METHOD THEREOF - A video decoder ( | 12-23-2010 |
| 20100293402 | DEVICE HAVING MULTIPLE GRAPHICS SUBSYSTEMS AND REDUCED POWER CONSUMPTION MODE, SOFTWARE AND METHODS - Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. | 11-18-2010 |
| 20100271503 | Digital Camera Module White Balance Calibration Method and Apparatus Using Only Single Illumination Source Data - A method includes determining white balance calibration color ratios for a plurality of illumination sources by using a representative camera of a given type to establish a set of ratios. Because the ratios are fixed for the given camera type, a plurality of cameras of the type may store the fixed ratios, and calibrate by measuring only the reference illumination source. Later white balancing is achieved by using the measured reference illumination source color ratios and the stored fixed ratios as scaling factors to map from the reference illumination source to any other illumination source. The method includes an off-line advance calibration procedure to obtain the fixed ratios, an on-line per camera calibration procedure to obtain color ratios for the reference source, and subsequent white balancing which uses the fixed ratios/scaling factors and the reference source color ratios. | 10-28-2010 |
| 20100262893 | ROBUST CONTROL/DELINEATION IN SERIAL STREAMS - Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronizaiton, transmitter/receiver synchronization or for other control signalling. | 10-14-2010 |
| 20100262746 | METHOD OF INTEGRATING A PERSONAL COMPUTING SYSTEM AND APPARATUS THEREOF - An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions. | 10-14-2010 |
| 20100260296 | Embedded Clock Recovery - Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. A method for a sink device to recover a source data rate includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters. Corresponding systems and computer program products are also described. | 10-14-2010 |
| 20100259676 | DETECTION AND ENHANCEMENT OF IN-VIDEO TEXT - The present disclosure relates to methods and apparatus for detecting text information in a video signal that includes subtitles, captions, credits, or other text, and also for applying enhancements to the display of text areas in video. The sharpness and/or contrast ratio of subtitles of detected text areas may be improved. Text areas may be displayed in a magnified form in a separate window on a display, or on a secondary display. Further disclosed are methods and apparatus for extending the duration for which subtitles appear on the display, for organizing subtitles to be displayed in a scrolling format, for allowing the user to control when a subtitle advances to the next subtitle using a remote control, and for allowing a user to scroll back to a past subtitle in cases where the user has not finished reading a subtitle. Additionally, optical character recognition (OCR) technology may be applied to detected areas of a video signal that include text, and the text may then be displayed in a more readable font, displayed in a translated language, or rendered using voice synthesis technology. | 10-14-2010 |
| 20100254605 | MOVING TEXT DETECTION IN VIDEO - Methods and apparatus for detecting moving text in video comprising receiving consecutive frames from a video stream, extracting a sequence of pixels from the consecutive frames, categorizing the pixels, thinning the pixels, correlating corresponding thinned pixels in the frames, identifying the peaks that are equal to or exceed a threshold, and performing further processing on the peaks to determine if the peaks contain moving text. | 10-07-2010 |
| 20100231592 | GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER - A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer. | 09-16-2010 |
| 20100230805 | MULTI-DIE SEMICONDUCTOR PACKAGE WITH HEAT SPREADER - A semiconductor device includes first and second stacked semiconductor dies on a substrate. A lid having a plurality of fins extending downwardly into the cavity is mounted on the substrate to encapsulate the semiconductor dies. At least some of the fins are longer than other ones of said fins. The lid is attached to the substrate, with the longer fins extending downwardly above a region of the substrate not occupied by the first die. The shorter fins extend downwardly above a region of said first die not covered by said second die. A thermal interface material fills the remainder of the cavity and is in thermal communication with both dies, the substrate and the fins. The lid may be molded from metal. The lid may be bonded to the topmost die, using a thermal bonding material that may be liquid metal, or the like. | 09-16-2010 |
| 20100225741 | 3D VIDEO PROCESSING - A method and apparatus for reducing motion judder in a 3D input source are disclosed. The 3D input source is separated into left and right images. Motion vectors for the left and right images are calculated. Frame rate conversion is performed on the left and right images, to produce motion compensated left and right images. The left and right images and the motion compensated left and right images are reordered for display. Alternatively, the motion estimation and motion compensation can be performed on the 3D input source, and the input image and the motion compensated image can then be separated into respective left and right images. The method and apparatus can be adapted to perform 2D to 3D conversion by extracting a 2D input source into left and right 3D images and performing motion estimation and motion compensation. | 09-09-2010 |
| 20100218149 | METHOD AND APPARATUS FOR HARDWARE DESIGN VERIFICATION - An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation. | 08-26-2010 |
| 20100188411 | Non-Graphics Use of Graphics Memory - Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc. | 07-29-2010 |
| 20100185800 | COMMUNICATION PROTOCOL FOR SHARING MEMORY RESOURCES BETWEEN COMPONENTS OF A DEVICE - In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components. | 07-22-2010 |
| 20100176848 | INPUT/OUTPUT BUFFER CIRCUIT - A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage. | 07-15-2010 |
| 20100166257 | METHOD AND APPARATUS FOR DETECTING SEMI-TRANSPARENCIES IN VIDEO - A method and apparatus for detecting semi-transparencies in video is disclosed. | 07-01-2010 |
| 20100161923 | METHOD AND APPARATUS FOR REALLOCATING MEMORY CONTENT - Coherent memory copy logic is operative to copy data from a source memory location to a destination memory location and duplicate a write request to a source memory region to produce a duplicated write request. Coherent memory copy logic is also operative to execute the duplicated write request to copy content from the external memory region to the destination memory region. Power to the source memory can then be reduced to save power while the internal memory is being used. Accordingly, a type of “hardware memory mover” does not require the use of any complex software synchronization and does not result in any service interruption during a memory move. The coherent memory copy logic reallocates the application memory space from, for example, external memory to internal memory within a chip in a manner that is transparent to the application software and the user. Corresponding methods are also set forth. | 06-24-2010 |
| 20100161261 | Method and Apparatus for Integrated Circuit Temperature Control - A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element, wherein the third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage; and calculating an error corrected difference between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n. | 06-24-2010 |
| 20100157711 | Self-Refresh Based Power Saving Circuit and Method - A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the adjustable impedance circuit in response to the impedance control signal. In addition, the self-refresh adjustable impedance driver circuit provides a memory interface signal based on the memory self-refresh information. | 06-24-2010 |
| 20100156915 | Multi-Thread Graphics Processing System - A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads. | 06-24-2010 |
| 20100155938 | FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT - An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL. | 06-24-2010 |
| 20100153758 | METHOD AND APPARATUS FOR OPTIMIZING POWER CONSUMPTION IN A MULTIPROCESSOR ENVIRONMENT - A method and apparatus for reducing net power consumption in a computer system includes identifying a plurality of processing states operable to execute a task. A processing state and current drain pattern is selected that is most power efficient. A selected processing state may include one or more processing elements of the computer system such as one or more processors or accelerators and indicates the manner in which one or more portions of the received task may be distributed among the processing elements of the computer system. The current drain pattern selected may be a constant current drain pattern or a pulsed current drain pattern and may be selected to optimize power consumption when executing the task among the one or more processing elements. | 06-17-2010 |
| 20100150225 | Adaptive Frequency Domain Filtering For Phase Plane Correlation - In a Phase Plane Correlation (PPC) process, using adaptive frequency domain filtering to aid in generating candidate motion vectors. It is determined when it is beneficial to pre-filter an input image, prior to a PPC process. This results in more reliable and consistent PPC surfaces than otherwise. The filter is applied in the frequency domain where time-domain convolution becomes a much more efficient component-wise multiplication with an in-place window. An energy measure of the high-frequency content in the computed Fourier surfaces gauges the degree of high frequency content in the image. First, the Fourier transform of the two images is computed. Then, the high-frequency content is estimated from the Fourier surfaces. A window function is computed as a function of the high-frequency energy. The window is applied to the Fourier surfaces. Then, the modified Fourier surfaces are fed into the PPC process. | 06-17-2010 |
| 20100149701 | ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD - A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants. In addition, an ESD feedback circuit is employed in conjunction with control logic to suitably control the ESD control logic during an ESD event. Circuitry is also used during a power up event to render the shunt structure non-conductive. | 06-17-2010 |
| 20100134680 | METHOD AND APPARATUS FOR DEJUDDERING IMAGE DATA - A method and apparatus of dejuddering image data includes receiving a video data signal that includes a plurality of successive source frames. A first source frame of the plurality of successive source frames is displayed a predetermined number of times. A first black frame is displayed, and successive source frames are displayed. | 06-03-2010 |
| 20100125858 | METHOD, SYSTEM AND APPARATUS FOR TRI-STATING UNUSED DATA BYTES DURING DDR DRAM WRITES - A memory interface circuit includes a plurality of data bus drivers and logic adapted to be operatively responsive to write driver mask information. If desired, the plurality of bus drivers and the logic may be implemented in separate integrated circuits. The plurality of bus drivers are adapted to be responsive to a write operation. The logic is also adapted to disable any one of the plurality of data bus drivers based on the write driver mask information during the write operation. | 05-20-2010 |
| 20100123810 | Flicker Detection Circuit for Imaging Sensors that Employ Rolling Shutters - Circuitry, apparatus and methods provide flicker detection and improved image generation for digital cameras that employ image sensors. In one example, circuitry and methods are operative to compare a first captured frame with a second captured frame that may be, for example, sequential and consecutive or non-consecutive if desired, to determine misalignment of scene content between the frames. A realigned second frame is produced by realigning the second frame with the first frame if the frames are determined to be misaligned. Luminance data from the realigned second frame and luminance data from the pixels of the first frame are used to determine if an undesired flicker condition exists. If an undesired flicker condition is detected, exposure time control information is generated for output to the imaging sensor that captured the frame, to reduce flicker. This operation may be done, for example, during a preview mode for a digital camera, or may be performed at any other suitable time. | 05-20-2010 |
| 20100110084 | PARALLEL PIPELINE GRAPHICS SYSTEM - The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2̂n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen's tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic. | 05-06-2010 |
| 20100103323 | METHOD, APPARATUS AND SOFTWARE FOR DETERMINING MOTION VECTORS - Motion vectors are determined from two images by obtaining one or more candidate motion vectors from the two images. Regions of the two images associated with the candidate motion vector are modified. Thereafter, further candidate motion vectors are obtained from the modified images, reducing the interfering effect of regions for which motion vectors have already been determined. | 04-29-2010 |
| 20100088453 | Multi-Processor Architecture and Method - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 04-08-2010 |
| 20100088025 | Route mapping system and method - A route mapping system includes a route module, a wireless coverage module, and a wireless coverage route module. The route module provides a plurality of routes in response to origination and destination information. The wireless coverage module provides wireless coverage information for a plurality of wireless service providers in response to the plurality of routes. The wireless coverage route module provides a plurality of wireless coverage routes in response to the plurality of routes and the wireless coverage information. | 04-08-2010 |
| 20100085366 | METHOD AND APPARATUS FOR RENDERING VIDEO - Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter (DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. A dummy switch receives the video-output from each of the VGAs. When a VGA is not providing information to the output port, the dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port. This allows the video graphics controller to maintain a constant thermal state. | 04-08-2010 |
| 20100079489 | SYSTEM AND METHOD FOR EFFICIENT DIGITAL VIDEO COMPOSITION - An efficient method of compositing planes onto a target surface using a computing device with graphics processing capability is disclosed. The method includes partitioning the target surface, on which planes are composited, into partitions. Each one of the partitions contains connected pixels to be formed by compositing an identical subset of the planes to be composited. Each partition is associated with a corresponding subset of the planes. Each partition and its corresponding set of associated planes are then provided to a graphics processor for composition, using exemplary software components including an application programming interface, a library and device driver software. An image is formed on the target surface by compositing each partition. Using the disclosed method, a single pass through stages of the graphics pipeline for the graphics processor is sufficient to composite multiple planes to form an image on the target surface. | 04-01-2010 |
| 20100066918 | MOBILE TELEVISION CONTROL LOGIC AND METHOD FOR IMPROVED CHANNEL SWITCHING TIME - A method, control logic, and executable instructions stored in memory enable faster switching between mobile television channels displayed on handheld devices. In one example, a tuner is controlled to receive a first wireless digital burst, such as a wireless digital burst of a digital video broadcasting-handheld (“DVB-H”) signal, including first channel information. The first channel information corresponds to a first mobile television channel to be displayed, and video based on the first channel information is provided. If desired, battery power consumption by the handheld device is then reduced by turning off the tuner. The tuner is then turned on to receive a second wireless digital burst including second channel information. The second channel information corresponds to the second mobile television channel to be displayed. The second channel information is buffered in a buffer while the video based on the first channel information is provided. If desired, battery power consumption is then reduced by again turning off the tuner. The tuner is again turned on to receive another burst. | 03-18-2010 |
| 20100061648 | PROTECTION FILTER FOR IMAGE AND VIDEO PROCESSING - A filter includes a conventional filtering block and a protection block. The conventional filtering block receives input values and provides filtered values. The protection block receives filtered values and a group of input values proximate the current input, to ensure that the output is lies within a range computed for the current input. The range is determined by the protection block based on the group of input values proximate the current input. Any algorithm or statistical function may be applied to the group of input values to determine the range. If a filtered value provided by the conventional filtering block is outside the range, then the protection block computes and outputs a value that is within the range. The filter may be used in temporal or spatial filtering of images and video to mitigate artifacts such as motion artifacts and static artifacts. | 03-11-2010 |
| 20100057466 | METHOD AND APPARATUS FOR SCROLLING TEXT DISPLAY OF VOICE CALL OR MESSAGE DURING VIDEO DISPLAY SESSION - A method and communication device disclosed includes displaying a video on a display, converting voice audio data to textual data by applying voice-to-text conversion, and displaying the textual data as scrolling text displayed along with the video on the display and either above, below or across the video. The method may further include receiving a voice call indication from a network, providing the voice call indication to a user interface where the voice call indication corresponds to an incoming voice call; and receiving a user input for receiving the voice call and displaying the voice call as scrolling text. In another embodiment, a method includes displaying application related data on a display; converting voice audio data to textual data by applying voice-to-text conversion; converting the textual data to a video format; and displaying the textual data as scrolling text over the application related data on said display. | 03-04-2010 |
| 20100053158 | UNIFIED TESSELLATION CIRCUIT AND METHOD THEREFOR - A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information. | 03-04-2010 |
| 20100053061 | ADAPTIVE BACKLIGHT CONTROL AND CONTRAST ENHANCEMENT - A transform function represented by at least n points that define n-1 regions is determined based at least in part on a first set of values associated with a display frame and a maximum average contrast function. The n points can be determined in response to a change in an average contrast of the display frame compared to an average contrast of a previous display frame exceeding a predetermined threshold. The first set of values is converted to a corresponding second set of values based on the transform function. A backlight control signal is generated based on an average contrast of the second set of values, whereby the backlight control signal is configured to control an intensity of a backlight of a display. Further, a video signal is generated based on the second set of values, whereby the video signal configured to drive the display. | 03-04-2010 |
| 20100044884 | INTEGRATED CIRCUIT PACKAGE EMPLOYING PREDETERMINED THREE-DIMENSIONAL SOLDER PAD SURFACE AND METHOD FOR MAKING SAME - An integrated circuit package employs a solder pad that includes a predetermined three dimensional surface that is adapted to receive solder. In one example, the predetermined three dimensional surface includes at least one predetermined hill or protruding portion and a valley portion, such as a lower portion, having a predetermined relative height between the hill portion and a valley portion. The predetermined three dimensional surface can be configured in any suitable configuration and may include contoured patterns, non-patterns, or any other suitable configuration as desired. A related method is also described. | 02-25-2010 |
| 20100026710 | Integration of External Input Into an Application - Provided are systems, methods, and computer program products for integrating external input into an application, with little or no modification to the application. Such a system includes a graphics processing unit (GPU) and an interface module. The GPU is configured to execute graphics processing tasks for the application. The interface module is configured to (i) receive a camera view of the application and an input from an after-market device and (ii) generate an adjusted camera view based on the camera view of the application and the input from the after-market device. The adjusted camera view is then provided to a display device. | 02-04-2010 |
| 20100023978 | Method and Apparatus for Determining Broadcast Reception Requirements Based on Location - A disclosed method comprises obtaining location data including geographic coordinates; searching stored digital video broadcast network requirements data corresponding to the location data; and tuning to a digital video broadcast network channel indicated by the digital video broadcast network requirements data. The step of obtaining location data may further comprise obtaining Global Positioning System (GPS) data; and searching using the GPS data. An integrated circuit includes tuner logic, operative to tune to, and receive, a digital video broadcast network channel in response to a command; location data logic to receive location data; digital video broadcast network reception requirements logic to obtain location data from the location data logic and search stored digital video broadcast network requirements data corresponding to the location data, and send the command to the tuner logic to tune to a digital video broadcast network channel indicated by the digital video broadcast network requirements data. | 01-28-2010 |
| 20100017893 | System for Securing Register Space and Method of Securing the Same - A system includes a processing device, at least one data processing module, and a security control module. The security control module is operatively connected to both the processing device and the data processing module. The security control module is operative to control access to a protected register that is associated with the at least one data processing module. As such, the security control module operates as a firewall or filter to allow or deny access to a protected register. Security-unaware data processing module are therefore secured in the system at a central location while eliminating the need to use only security-aware data processing module. A method for securing data processing modules, including security-unaware data processing module, is also disclosed. | 01-21-2010 |
| 20100017659 | Secure Boot Circuit and Method - A circuit includes a circuit identification storage module and a control module. The circuit identification storage module stores circuit identification information. The control module receives the circuit identification information and in response thereto selectively performs a secure boot procedure or a test boot procedure. The control circuit performs the secure boot procedure when the circuit identification information indicates that the circuit is a production circuit. The control circuit performs the test boot procedure when the circuit identification information indicates that the circuit is a test circuit. A related method is also disclosed. | 01-21-2010 |
| 20100017652 | APPARATUS WITH REDUNDANT CIRCUITRY AND METHOD THEREFOR - An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry. | 01-21-2010 |
| 20100013689 | REDUCED COMPONENT DIGITAL TO ANALOG DECODER AND METHOD - An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages. | 01-21-2010 |
| 20090322632 | PHYSICALLY SMALL TUNABLE NARROW BAND ANTENNA - A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna. | 12-31-2009 |
| 20090315899 | GRAPHICS MULTI-MEDIA IC AND METHOD OF ITS OPERATION - A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC. | 12-24-2009 |
| 20090307502 | METHOD AND APPARATUS FOR SECURING DIGITAL INFORMATION ON AN INTEGRATED CIRCUIT READ ONLY MEMORY DURING TEST OPERATING MODES - The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations. | 12-10-2009 |
| 20090307411 | METHOD AND APPARATUS FOR SECURING DIGITAL INFORMATION ON AN INTEGRATED CIRCUIT DURING TEST OPERATING MODES - The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode. | 12-10-2009 |
| 20090307406 | Memory Device for Providing Data in a Graphics System and Method and Apparatus Thereof - A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. | 12-10-2009 |
| 20090292934 | INTEGRATED CIRCUIT WITH SECONDARY-MEMORY CONTROLLER FOR PROVIDING A SLEEP STATE FOR REDUCED POWER CONSUMPTION AND METHOD THEREFOR - A method comprising determining that a minimum operation level of an integrated circuit ( | 11-26-2009 |
| 20090288160 | INTEGRATED CIRCUIT WITH SECURE BOOT FROM A DEBUG ACCESS PORT AND METHOD THEREFOR - An integrated circuit ( | 11-19-2009 |
| 20090288137 | Distributed Digital Rights Management System and Method - A digital rights management system includes an authentication module and a decryption module. If desired, the modules can be implemented in separate integrated circuits. The authentication module retrieves authentication information for protected content and powers down after the authentication information is retrieved. The decryption module decrypts the protected content based on the authentication information while the authentication module is powered down. | 11-19-2009 |
| 20090285390 | INTEGRATED CIRCUIT WITH SECURED SOFTWARE IMAGE AND METHOD THEREFOR - The various embodiments herein disclosed include a method wherein an integrated circuit ( | 11-19-2009 |
| 20090276558 | LANE MERGING - A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state. | 11-05-2009 |
| 20090276464 | IMAGE PROCESSING SYSTEM AND METHOD - An image processing system and method receives one or more digital images in the form of image data, including selected object data of a digital image, and determines, by an electronic recognition process, if a recognition match is available between the selected object data of the digital image and image object library data associated with image descriptor library data. An automated library user interface presents selectable matched object descriptor data associated with the image descriptor library data when a recognition match occurs between the selected object data of the digital image and the image descriptor library data. In response, the automated library user interface provides user feedback data to confirm that the image descriptor library data corresponds with the selected object data of the digital image, or entered descriptor data if no match or an incorrect match occurs, to create library descriptor associated image data. | 11-05-2009 |
| 20090259437 | NOISE MEASUREMENT IN VIDEO IMAGES - A method and apparatus are disclosed wherein the horizontal and vertical variances of the pixels of an image are determined to calculate a noise measurement in a received image. | 10-15-2009 |
| 20090232213 | Method and apparatus for super-resolution of images - A method to generate super-resolution images using a sequence of low resolution images is disclosed. The method includes generating an estimated high resolution image, motion estimating between the estimated high resolution image and comparison images from the sequence of low resolution images, motion-compensated back projecting, and motion-free back projecting that results in a super resolved image. A corresponding system for generating super-resolution images includes a high resolution image estimation module, a motion estimating module, a motion-compensated back projection module, a motion-free back projection module, an input interface, and an output interface. | 09-17-2009 |
| 20090218689 | FLIP CHIP SEMICONDUCTOR ASSEMBLY WITH VARIABLE VOLUME SOLDER BUMPS - A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads. | 09-03-2009 |
| 20090213226 | LOW-COST AND PIXEL-ACCURATE TEST METHOD AND APPARATUS FOR TESTING PIXEL GENERATION CIRCUITS - A method and system of testing pixels output from a pixel generation unit under test includes generating pixels from the pixel generation unit under test using a first test data pattern to generate pixel information. The method and system also generate a per pixel error value for a pixel from the unit under test that contains an error based on the pixel by pixel comparison with pixel information generated substantially concurrently with pixels by a different unit using the first test data pattern. If desired, corresponding pixel screen location information (e.g., x-y location) can also be determined for the pixel that has the error. The per pixel error and x-y location information can be displayed. | 08-27-2009 |
| 20090204736 | COMPUTING DEVICE WITH FLEXIBLY CONFIGURABLE EXPANSION SLOTS, AND METHOD OF OPERATION - A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters. | 08-13-2009 |
| 20090167958 | SYSTEM AND METHOD OF MOTION VECTOR ESTIMATION USING CONTENT ASSOCIATIVITY - A method and apparatus that is able to favor keeping objects in motion intact is provided. Additionally a method and apparatus regularizing a motion vector field that has been previously determined by a traditional algorithm is provided. Finally, a mechanism is provided that allows for improving a contextual understanding of an object structure even when the group of pixels under consideration is much smaller than the object in motion. | 07-02-2009 |
| 20090167930 | METHOD AND APPARATUS WITH FAST CAMERA AUTO FOCUS - A method and apparatus improves an auto focus system by altering, such as by positioning, at least one lens of a digital camera to a plurality of predetermined nonuniform lens positions corresponding to predetermined nonuniform lens position data. The method and apparatus selects a final lens position for the lens based on the predetermined nonuniform lens position data. In one example, a fixed number of predetermined nonuniform lens positions define a set of lens positions used to capture images during an auto focus operation. A final image is captured using a final lens position. The final lens position is determined by comparing focus metric information from each of the frames obtained at the various predetermined nonuniform focus lens positions and selecting the frame with, for example, the best focus metric as the lens position to be used for the final picture or image capture. | 07-02-2009 |
| 20090167923 | METHOD AND APPARATUS WITH DEPTH MAP GENERATION - An apparatus and method are disclosed wherein a depth map is generated using a single camera (e.g., single lens of a camera) and multiple images are captured by the camera. In one example, a single digital camera is used to capture a set of images corresponding to a set of lens positions based on lens position data. In this example, the lens position data may be either uniform or nonuniform lens position data. The method and apparatus determines focus metric information for each of a plurality of regions of interest in each image of a set. A determination is made of a best lens position for each of the regions of interest based on the focus metric information from the images in the set and are stored as data in a depth map. Image generation operations are then performed based on the generated depth map, such as determining whether or not to use a flash to capture a final image, to determine a type of color operation to be performed on the final image, or any other suitable image generation operation. In one example, the depth map is generated by selecting a best focus metric among the various images that were captured for a particular region of interest. Once the depth map is generated using data from the multiple images, depth map based control logic then determines how to use the depth map to effect an image processing operation. Among other advantages, multiple cameras need not be employed nor do external light sensors need be employed to generate a depth map for use in image processing operations. Other advantages will be recognized by those of ordinary skill in the art. | 07-02-2009 |
| 20090167778 | APPARATUS AND METHOD FOR SINGLE-PASS, GRADIENT-BASED MOTION COMPENSATED IMAGE RATE CONVERSION - A mipmap generator generates pairs of mipmaps that are each of a lower resolution that its respective source image. A single-pass, gradient-based motion vector generator generates an image motion vector map having values that represent the motion trajectories for pixels in the first and second source images. An image interpolator generates an interpolated image based on the source images and the image motion vector map. A motion detector generates a motion factor map based on a pair of mipmaps from those generated by the mipmap generator that represents a detected degree of motion between the first and second source images. The blending module generates a blended, upconverted new image using the motion factor map, the interpolated image and one of the first and second motion maps. | 07-02-2009 |
| 20090162029 | ADJUSTING VIDEO PROCESSING IN A SYSTEM HAVING A VIDEO SOURCE DEVICE AND A VIDEO SINK DEVICE - One of a video source device and a video sink device may: (a) deactivate a video processing function at the one device and send a command for causing the other of the video source device and the video sink device to activate the video processing function; (b) activate the video processing function at the one device and send a command for causing the other device to deactivate the video processing function; and (c) based on user input indicating whether (a) or (b) resulted in a preferred video image, effect (a) or (b). The one device may receive an indication of video processing functions of which the other device is capable, such that (a), (b) and (c) may be performed for each indicated video processing function of which the one device is also capable. A user interface including at least one selectable control for indicating whether a video image resulting from (a) or (b) is preferred may be displayed. | 06-25-2009 |
| 20090161988 | SYSTEM AND METHOD OF IMAGE CORRELATION BASED ON IMAGE STRUCTURE - A method and apparatus that augments the traditional Phase Plane Correlation (PPC) approach incorporates image structure into the correlation process. In so doing, the energy in spurious peaks that can occur in the phase plane correlation surface are dramatically reduced. | 06-25-2009 |
| 20090161987 | METHOD AND APPARATUS FOR PROCESSING IMAGE DATA - A method and apparatus of processing image data comprises correlating received image data. Image statistics are computed based upon the correlated image and eccentricity is estimated based upon the computed image statistics. An entropy metric of the correlated received image data is determined. An interpretation based upon the image statistics, estimated eccentricity, and entropy metric is performed and a report including the content of the processed image data is generated. | 06-25-2009 |
| 20090161017 | METHOD, APPARATUS AND MACHINE-READABLE MEDIUM FOR DESCRIBING VIDEO PROCESSING - An upstream video processor may perform video processing upon video data to created processed video data. The video processing may include at least one of color correction, contrast correction, gamma correction, sharpness enhancement, and edge enhancement. Metadata indicative of the performed video processing may also be generated. The processed video data and metadata may be passed to a downstream video processor, the latter for use in determining what further video processing, if any, to apply. An intermediate video processor may receive video data and metadata indicating video processing performed thereupon by an upstream video processor. Based on the received metadata, additional video processing may be performed, and new metadata indicating the additional video processing may be generated. Composite metadata may be generated from the received and new metadata and may be passed along with the processed video data to a downstream video processor for use in determining what further video processing, if any, to apply. | 06-25-2009 |
| 20090161009 | METHOD, APPARATUS AND MACHINE-READABLE MEDIUM FOR HANDLING INTERPOLATED VIDEO CONTENT - Spatial or temporal interpolation may be performed upon source video content to create interpolated video content. A video signal including the interpolated video content and non-interpolated video content (e.g. the source video content) may be generated. At least one indicator for distinguishing the non-interpolated video content from the interpolated video content may also be generated. The video signal and indicator(s) may be passed from a video source device to a video sink device. The received indicator(s) may be used to distinguish the non-interpolated video content from the interpolated video content in the received video signal. The non-interpolated video content may be used to “redo” the interpolation or may be recorded to a storage medium. | 06-25-2009 |
| 20090160531 | MULTI-THRESHOLD VOLTAGE-BIASED CIRCUITS - A circuit and a method of operation to reduce dynamic and static power dissipation in the circuit are disclosed. The circuit is multi-threshold, voltage-biased and includes a p-channel field effect transistor (FET) and an n-channel FET. A source terminal of the p-channel FET interconnects to a higher-voltage rail of a power supply and a source terminal of the n-channel FET interconnects to a lower-voltage rail of the power supply. At least one of the FETs includes a back contact. The circuit may be operated by applying a fixed bias voltage to the back contact. The fixed bias voltage is independent of the power supply voltage which may be varied. In a normal state, the supply voltage is adjusted to decrease dynamic power consumption. In a low power state, the supply voltage is further adjusted to limit leakage current. The circuit may optionally include a second fixed biasing voltage source so that both FETs are biased. | 06-25-2009 |
| 20090157938 | ELECTRONIC DEVICES USING DIVIDED MULTI-CONNECTOR ELEMENT DIFFERENTIAL BUS CONNECTOR - In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing. The electronic device housing further includes a passive or active cooling mechanism such as a fan positioned to cool the circuitry during normal operation. In one example, the electronic device does not include a host processor and instead a host processor is in a separate electronic device that communicates with the graphics processing circuitry through the divided multi connector element differential bus connector. In another example, a CPU (or one or more CPUs) is also co-located on the circuit substrate with the circuitry to provide a type of parallel host processing capability with an external device. | 06-18-2009 |
| 20090157914 | DISPLAY SYSTEM WITH FRAME REUSE USING DIVIDED MULTI-CONNECTOR ELEMENT DIFFERENTIAL BUS CONNECTOR - A method includes reducing power of a first graphics processor by disabling or not using its rendering engine and leaving a display engine of the same first graphics processor capable of outputting display frames from a corresponding first frame buffer to a display. A display frame is rendered by a second graphics processor while the rendering engine of the first graphics processor is in a reduced power state, such as a non-rendering state. The rendered frame is stored in a corresponding second frame buffer of the second graphics processor, such as a local frame buffer and copied from the second frame buffer to the first frame buffer. The copied frame in the first frame buffer is then displayed on a display while the rendering engine of the first graphics processor is in the reduced power state. Accordingly thermal output and power output is reduced with respect to the first graphics processor since it does not do frame generation using its rendering engine, it only uses its display engine to display frames generated by the second graphics processor. | 06-18-2009 |
| 20090156060 | ELECTRICAL CONNECTOR, CABLE AND APPARATUS UTILIZING SAME - An electrical connector, such as a circuit board connector, includes a housing having therein a divided multi-connector element. The electrical connector is adapted to electrically connect with a substrate, such as a circuit board. The divided multi-connector element includes a divided electrical contact configuration that includes a first group or subassembly of electrical contacts physically separate from an adjacent and second group or subassembly of contacts. The first group of electrical contacts and second group of electrical contacts each include a row of lower contacts and upper contacts. The second group of electrical contacts has an identical but mirrored configuration as the first group of electrical contacts. | 06-18-2009 |
| 20090153737 | METHOD, APPARATUS AND MACHINE-READABLE MEDIUM FOR APPORTIONING VIDEO PROCESSING BETWEEN A VIDEO SOURCE DEVICE AND A VIDEO SINK DEVICE - To apportion desired video processing between a video source device and a video sink device, at one of the devices, and based upon an indication of video processing algorithms of which the other device is capable and an indication of video processing algorithms of which the one device is capable, a set of video processing algorithms for achieving desired video processing is identified. The identified set of video processing algorithms is classified into a first subset of algorithms for performance by the other device and a second subset of algorithms for performance by the one device. At least one command for causing the other device to effect the first subset of video processing algorithms is sent. The one device may be configured to effect the second subset of algorithms. | 06-18-2009 |
| 20090153734 | METHOD, APPARATUS AND MACHINE-READABLE MEDIUM FOR VIDEO PROCESSING CAPABILITY COMMUNICATION BETWEEN A VIDEO SOURCE DEVICE AND A VIDEO SINK DEVICE - At one of a video source device and a video sink device, an indication of video processing capabilities of the other of the video source device and said video sink device is received. Based upon the indication and an indication of video processing capabilities of the one device, one of a plurality of video processing algorithms is selected for execution by the one device. The selecting may be based upon a set of precedence rules. Categories of video processing may for example include scan-rate conversion, interlacing, de-interlacing, de-noise, scaling, color correction, contrast correction and detail enhancement. | 06-18-2009 |
| 20090150823 | Apparatus and Method for Improved Window Management in a Grid Management System - An apparatus is operative to output display data for displaying a first application window and a second application window, wherein each application window is associated with an active application. The apparatus attaches the first application window with a first grid section using a grid management system, and based on user input associated with the second application window, performs a grid-based operation, such as swapping, splitting, or sharing. A method is also described that includes one or more of a grid-based swapping operation, a grid-based splitting operation, and a gird-based sharing operation. | 06-11-2009 |
| 20090150817 | Method and Apparatus Utilizing Profiles to Reduce Software Complexity - Apparatus and methods relate to applications with references to profiles, wherein the profiles have parameter information that corresponds to device graphical user interface options. Profiles may be associated with hardware operations of the device, such as image, video, or audio en/decoding, and the parameter information corresponds to the capabilities and specifications of a hardware device. Corresponding systems for creating applications with at least one profile reference are also described. | 06-11-2009 |
| 20090147133 | METHOD AND APPARATUS FOR HIGH QUALITY VIDEO MOTION ADAPTIVE EDGE-DIRECTIONAL DEINTERLACING - A method for deinterlacing video includes constructing a temporary frame of deinterlaced video based on a first (i.e., current) field of interlaced video, wherein the temporary frame includes pixels in lines of the temporary frame associated with the first field of interlaced video, placeholder pixels in identified areas of motion in lines of the frame associated with a missing field of interlaced video, and pixels from an opposite field of polarity of interlaced video in areas without motion. The method further includes replacing the placeholder pixels in the identified areas of motion with pixels interpolated using an edge direction interpolation scheme based on pixels in the first field of interlaced video, resulting in a reconstructed frame. In one example, a motion adaptive interpolator may construct the temporary frame, and an edge directional interpolator may generate the reconstructed/deinterlaced the frame. | 06-11-2009 |
| 20090147021 | WIDE COLOR GAMUT DISPLAY SYSTEM - A wide gamut RGB digital display, such as an LCD display, digital television, printer, or any other suitable display, includes wide color gamut configuration message control logic that is operative to indicate, to an image source provider, wide gamut RGB indication information and wide color gamut format definition information that indicates that wide gamut RGB color data is to be received by the wide gamut RGB digital display. The wide gamut configuration message control logic is also operatively responsive to wide gamut confirmation information that is received from the image source provider. The wide gamut RGB digital display also includes logic that is operative to display received wide gamut RGB color data that was received in response to the wide gamut RGB indication information and the format definition information. | 06-11-2009 |
| 20090132785 | SIMD processor executing min/max instructions - A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays. | 05-21-2009 |
| 20090121761 | INTRA-PAIR DIFFERENTIAL SKEW COMPENSATION METHOD AND APPARATUS FOR HIGH-SPEED CABLE DATA TRANSMISSION SYSTEMS - A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew. The differential skew compensation circuit receives a pair of complementary differential input signals including a noninverting input signal and an inverting input signal, and in response generates a skew compensated first differential output signal and a skew compensated second differential output signal. The differential skew compensation circuit compares the relative delay of the skew compensated first differential output signal and the skew compensated second differential output signal, and in response delays at least one of the noninverting input signal or the inverting input signal to reduce intrapair skew. | 05-14-2009 |
| 20090115457 | Apparatus and Methods for Self-Biasing Differential Signaling Circuitry Having Multimode Output Configurations for Low Voltage Applications - The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output. | 05-07-2009 |
| 20090108679 | WIRELESS ENERGY TRANSFER - Method for wireless energy transfer is disclosed. According to an embodiment, the method includes transferring electrical energy from one electronic device to another electronic device with the help of electromagnetic waves. An electronic device that requires electrical energy can get energy transferred from one or more other electronic devices present in its vicinity. The electrical energy being transferred can be used to charge the battery of the electronic device. | 04-30-2009 |
| 20090100278 | Method and Apparatus for Managing Power Consumption Relating to a Differential Serial Communication Link - Briefly, a method, apparatus and system for managing power corresponding to a differential serial communication link that has a link width defined for example by one or more lanes wherein the lanes are adapted to communicate clock recovery information in a data stream, determines, during normal operating conditions, such as conditions other than power on, reset or link fault conditions, a desired link width for the serial communication link and then changes the link width accordingly. | 04-16-2009 |
| 20090096792 | FILL MODE DETERMINATION IN VECTOR GRAPHICS - An efficient method for improving use of different fill modes in vector graphics and a system using the method. The filling method uses a graphics hardware that is capable of producing objects to be filled. Before the actual filling the edges of the objects must be computed. Edges are then stored into an edge buffer. The buffer may be a separate buffer block or a pointer to a memory. The edge buffer comprises only the edges of the object to be rendered. When the object is actually is rendered, rendering function is called with at least one parameter. The parameters include the fill mode with which the object is rendered to the screen. | 04-16-2009 |
| 20090088246 | INTERACTIVE SOUND SYNTHESIS - The subject matter relates to a method for synthesizing game related sound using the laws of physics. In one implementation, one or more interactions between game elements within a game environment are identified. Properties associated with each of the gaming element are determined and parameters of the interactions are calculated. Based on these parameters and the properties of the elements, stored sound samples are used to produce appropriate sound. | 04-02-2009 |
| 20090087120 | APPARATUS AND METHOD FOR GENERATING A DETAIL-ENHANCED UPSCALED IMAGE - An upscaler is disclosed that upscales each of a maximum value map, a minimum value map and an average value map to a destination resolution. A blending module generates a detail-enhanced upscaled image of the source image having the destination resolution by blending corresponding pixel values from an upscaled image of the source image with at least one of: the upscaled maximum value map and the upscaled minimum value map. The blending may be based on the strength of detected edges in the source image and further based on a comparison of each pixel value in the upscaled image with a corresponding pixel value in an average value map. A source image characteristic calculator may generate the maximum value map, the minimum value map and the average value map based on the intensity values of a source image. | 04-02-2009 |
| 20090086093 | SINGLE-PASS MOTION ADAPTIVE DEINTERLACER AND METHOD THEREFORE - A frame construction engine constructs a first frame of deinterlaced video and a second frame of deinterlaced video based on a first field of interlaced video and based on a second field of interlaced video, independent of any other fields of interlaced video. The frame construction engine constructs the first frame of deinterlaced video by assigning pixel values from the first field of interlaced video to corresponding pixel locations in the first frame. The frame construction engine constructs the second frame of deinterlaced video by assigning pixel values from the second field of interlaced video to corresponding pixel locations in the second frame. Missing pixel locations in each of the frames are selected from a corresponding field of spatially interpolated pixel values or from an opposite field of deinterlaced video. | 04-02-2009 |
| 20090086036 | METHOD AND APPARATUS FOR CAMERA SHAKE EFFECT IMAGE STABILIZATION - A method and apparatus for camera shake effect image stabilization determines a most favorable image sharpness metric out of image sharpness metrics from a plurality of images that were captured at a same lens position. A final image is selected based on the most favorable image sharpness metric. | 04-02-2009 |
| 20090083655 | METHOD AND TOOL FOR VIRTUAL DESKTOP MANAGEMENT - A method for providing a desktop management tool includes displaying an active desktop having at least one application window representing an active application; storing data representing a virtual desktop in memory; while displaying the active desktop, receiving non-menu-based user input representing an application-move operation between the active desktop and the virtual desktop; and associating the active application with the virtual desktop. The method may also include displaying, as part of the active desktop, a visual representation of the virtual desktop. Other examples of the described method also include displaying an enlarged view of the contents of a virtual desktop in response to additional user input. An example apparatus for implementing the described methods is also described. | 03-26-2009 |
| 20090061954 | SERVER INITIATED POWER MODE SWITCHING IN PORTABLE COMMUNICATION DEVICES - In a process, a power mode indicator is transmitted from a content server and is received by a Portable Communication Device (PCD). The indicator is indicative of a power mode potentially available to a circuit block in the PCD. The circuit block exhibits different levels of power consumption when operated in different power modes and is operated in the indicated power mode in response to the received power mode indicator. The content server may be a stream server. The circuit block may be operated in the power mode to receive/process a data stream. | 03-05-2009 |
| 20090061918 | Method and Apparatus for Managing Power Consumption Relating to a Differential Serial Communication Link - A circuit includes a primary transceiver, a secondary transceiver, and control logic. The primary transceiver communicates information via a primary communication link. The secondary transceiver communicates information via a secondary communication link. The control logic is operatively coupled to the primary and secondary transceivers. The control logic selectively powers down the primary transceiver based on primary communication link traffic trigger information and causes communication using the secondary transceiver instead of the primary transceiver based on the primary communication link traffic trigger information. | 03-05-2009 |
| 20090060380 | DEVICE AND METHOD FOR REDUCING VISUAL ARTIFACTS IN COLOR IMAGES - A circuit and method for reducing artifacts in decoded color video and images are disclosed. The circuit includes a buffer for receiving an input pixel in a first color-space, and a detector for determining after transformation into a second color-space, if at least one component of the transformed pixel would fall outside a predetermined range. The determination may be made by comparing components of the input pixel, to corresponding ranges in the first color-space. Upon determining that at least one component of the transformed pixel would be outside a corresponding predetermined bound in the second color-space, the detector causes the circuit to output a pixel in the first color-space, with at least one predetermined component. The output of the circuit may subsequently be converted to the second color-space by an external color-space converter and displayed onto a color display. The method reduces visible artifacts caused by clipping during color-space conversion. | 03-05-2009 |
| 20090060367 | METHOD AND APPARATUS FOR PRODUCING A CONTRAST ENHANCED IMAGE - A method and apparatus for enhancing an input image to produce a contrast enhanced output image is disclosed. The method involves producing a contrast value for each pixel in the input image, the contrast value being proportional to an intensity gradient between each respective pixel and at least one pixel adjacent the respective pixel. The method also involves selecting pixels in the input image having respective contrast values that meet a first criterion, thereby forming a selected plurality of pixels and producing a frequency distribution of intensity values of the selected plurality of pixels. The method further involves selecting at least one range of intensity values in the frequency distribution that meet a second criterion, thereby producing a selected range of intensity values for enhancement. The method also involves producing the contrast enhanced output image by at least one of (i) expanding pixel intensity values in the input image that fall within the selected range of intensity values; and (ii) compressing pixel intensity values in the input image that fall outside the selected range of intensity values. | 03-05-2009 |
| 20090057887 | WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads. | 03-05-2009 |
| 20090049321 | CIRCUITS WITH TRANSIENT ISOLATION OPERABLE IN A LOW POWER STATE - An integrated circuit suitable for power conservation is disclosed. The circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices. | 02-19-2009 |
| 20090046863 | REMOTE-CONTROL DEVICE WITH DIRECTIONAL AUDIO SYSTEM - A method of directing an audio signal to an intended user by a remote-control device coupled to an audio/video device is described. The remote-control device sends an instruction to the audio/video device to transmit an audio signal. The remote-control device receives the audio signal and process the audio signal to generate a directional audio. The directional audio is then routed to an intended user such that the directional audio signal is audible to the intended user, other recipients in the vicinity. | 02-19-2009 |
| 20090033671 | MULTI-SAMPLE RENDERING OF 2D VECTOR IMAGES - A method and device for enhanced rendering providing reduced memory bandwidth requirements in a graphics processor. In the rendering process, a classification buffer of limited bit length is used for classifying the pixels. Based on the classification, a decision on the pixel color may be made without accessing the multi-sample buffer for a portion of the pixels. This reduces the memory bandwidth requirements. | 02-05-2009 |
| 20090027106 | Substantially Zero Temperature Coefficient Bias Generator - In an embodiment, a bias generator circuit comprises a first circuit and a second circuit. The first circuit includes a first input coupled to a voltage source and a first output that provides a first output current having a substantially non-zero temperature coefficient. The first circuit comprises a first transistor and a second transistor. The second circuit includes a second input that receives the first output current from the first circuit and a second output that provides a second output current. The second circuit comprises a third transistor and a fourth transistor. The second output current has a substantially zero temperature coefficient dependent on (i) a difference between an effective channel size of the first transistor and an effective channel size of the second transistor, and (ii) a difference between an effective channel size of the third transistor and an effective channel size of the fourth transistor. | 01-29-2009 |
| 20080316299 | VIRTUAL STEREOSCOPIC CAMERA - The subject matter relates to a virtual stereoscopic camera for displaying 3D images. In one implementation, left and right perspectives of a source are captured by image capturing portions. The image capturing portions include an array of image capturing elements that are interspersed with an array of display elements in a display area. The image capturing elements are confined within limited portions of the display area and are separated by an offset distance. The captured left and right perspectives are synthesized so as to generate an image that is capable of being viewed in 3D. | 12-25-2008 |
| 20080284480 | SCAN FLIP-FLOP WITH INTERNAL LATENCY FOR SCAN INPUT - A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits. | 11-20-2008 |
| 20080273602 | DATA TRANSMISSION APPARATUS WITH INFORMATION SKEW AND REDUNDANT CONTROL INFORMATION AND METHOD - Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed. | 11-06-2008 |
| 20080266326 | AUTOMATIC IMAGE REORIENTATION - Method for automatic image reorientation is disclosed. In an embodiment, the method includes reorienting a displayed image in response to a change in relative orientation of a viewer image with respect to a reference image. The reorientation is performed to compensate, at least partially, for the change in relative orientation of the viewer image. | 10-30-2008 |
| 20080253087 | THERMAL MANAGEMENT SYSTEM FOR AN ELECTRONIC DEVICE - A configurable multiple inlet thermal management device, such as an air-mover or passive heat sink, for electronic devices. The thermal management device is arranged on a computing device or on a component of a computing device or similar, such as an expansion module or alike, so that incoming air flow decreases the temperature of the heat producing components. In order to provide best possible air flow the air-mover comprises blade design that pressurizes the air flow from at least one side of the air-mover component. The air-mover includes removable covers for providing the openings required for intake air from the desired direction and for providing a fan wind. Depending on the application the openings may be permanently opened or closed. The intake air flow is then directed in form of fan wind towards the heat producing elements. | 10-16-2008 |
| 20080250212 | METHOD AND APPARATUS FOR ACCESSING MEMORY USING PROGRAMMABLE MEMORY ACCESSING INTERLEAVING RATIO INFORMATION - A method and apparatus stores data representing a non 1:1 memory access interleaving ratio for accessing a plurality of memories. The method and apparatus interleaves memory accesses to at least either a first memory that is accessible via a first (and associated memory) bus having first characteristics or a second memory accessible via a second bus having different characteristics, based on the data representing the non 1:1 interleaving memory access ratio. | 10-09-2008 |
| 20080245555 | CIRCUIT SUBSTRATE WITH PLATED THROUGH HOLE STRUCTURE AND METHOD - A circuit substrate includes an outer plated through hole structure and an inner plated through hole structure located within the outer plated through hole structure. In one example, the circuit substrate includes a core and an outer plated through hole structure having a first metal layer configured over the core to form an outer plated through hole. The circuit substrate also includes an inner plated through hole structure located within the outer plated through hole structure having a second metal layer positioned inside of the outer plated through hole with an insulation layer interposed between the first and second metal layers. Methods for making such a circuit substrate are also described. | 10-09-2008 |
| 20080232704 | Video decoder with adaptive outputs - In one aspect, there is provided a video decoder including a first write port to write uncompressed video data to a first buffer in a first format adapted based on an input required by the video decoder and to suppress writing to the first buffer. The video decoder also includes a second write port to write uncompressed video data to a second buffer in a second format adapted to provide the uncompressed video data for subsequent processing external to the video decoder. | 09-25-2008 |
| 20080231711 | AUTOMATED COMPLIANCE TESTING FOR VIDEO DEVICES - A method of automated video device testing, and source and sink video devices are disclosed. A test signal may be provided by way of a video link from a video source to a video sink, over a video link extending therebetween. The method includes receiving on the video link a request from the video sink to provide the test signal; identifying based on the request, a requested test signal; providing the requested test signal from the video source to the video sink over the video link. In another embodiment, a video sink may be queried over a video link to determine a metric describing at least a portion of know video signal, as received and determined at the video sink to verify integrity of the video signal at the video sink. | 09-25-2008 |
| 20080218521 | OFFSET TILES IN VECTOR GRAPHICS - An efficient rendering method for processing computer graphics in tiles. First a frame of data, typically at least one polygon, is received for rendering. While rendering a polygon the tile for the polygon is assigned so that it minimizes the number of the tiles needed for processing the polygon. It is possible to compute an offset value between the static tiles and the assigned tiles. If the offset value is computed, the rendering into an actual screen may be based on that. | 09-11-2008 |
| 20080205634 | METHOD, MODULE AND SYSTEM FOR PROVIDING CIPHER DATA - A method of providing cipher data during a period of time when output of a primary source of cipher data is unavailable is disclosed. The method comprises switching from a primary source of cipher data to an alternate source of cipher data at a beginning of the period of time; using the cipher data from the alternate source during the period of time; and switching back to the primary source at an end of the period of time. | 08-28-2008 |
| 20080204460 | DEVICE HAVING MULTIPLE GRAPHICS SUBSYSTEMS AND REDUCED POWER CONSUMPTION MODE, SOFTWARE AND METHODS - Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. | 08-28-2008 |
| 20080204285 | ROBUST CONTROL/DELINEATION IN SERIAL STREAMS - Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling. | 08-28-2008 |
| 20080201500 | MULTIPLE INTERRUPT HANDLING METHOD, DEVICES AND SOFTWARE - A device, method and software for handling multiple interrupts in a peripheral device are disclosed. The disclosed method includes, upon a hardware event in the peripheral device recording the hardware event and determining an acceptable period before which an interrupt should be generated to service the event. A timer at the peripheral device is adjusted as needed to maintain a value within the acceptable period. Upon expiry of the timer a single interrupt is generated to a processor interconnected to the peripheral device. In response to the single interrupt, software code is executed on the processor to service un-serviced hardware events for which an indicator has been recorded. | 08-21-2008 |
