| ASAHI KASEI MICRODEVICES CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120127005 | FAST QUANTIZER APPARATUS AND METHOD - An apparatus and method for a fast quantizer comparator comprising three stages: a preamplifier stage, a regeneration latch stage, and a data latch stage. Time delay is reduced by changing the initial voltages of the regeneration latch outputs. The current source is provided at the tail of the comparator, enabling time delay optimization. When the PMOS equalization switch turns off, it makes the clock signal feedthrough and provides charge injection into the outputs. Because of these charges, the time delay of the comparator is variable. Only a very low current sets the output voltages because the resetting time is longer than the comparison time. | 05-24-2012 |
| 20120068865 | FAST DATA WEIGHTED AVERAGE CIRCUIT AND METHOD - A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer. | 03-22-2012 |
| 20120032831 | ADDER-EMBEDDED DYNAMIC PREAMPLIFIER - A method and apparatus for an adder-embedded dynamic preamplifier system with dynamic comparator and current mode adder including differential switches for precharging, a switch for evaluation; and reference, feedfoward input sections. When differential switches are closed, OUTN and OUTP are precharged. During the evaluation, discharging currents are proportionately determined by input and reference values. A following latch amplifies the discharging differences of OUTN and OUTP. | 02-09-2012 |
| 20120007644 | COMPARATOR-BASED BUFFER WITH RESISTIVE ERROR CORRECTION - A comparator-based buffer method and system enhance the driving capability of high-gain amplifiers with switched-capacitor loads. It includes a current source, a comparator, switches, sampling capacitor and overshoot correction resistor. A correction solution using a resistor in the charging path and a correction phase reduces the overshoot of the output voltage while constraining power consumption and minimizing components. Spectre® simulations verify the effectiveness of the invention. | 01-12-2012 |
| 20120007589 | POSITION DETECTING APPARATUS - The present invention provides a single component implementing highly precise pulse detection for rotational or liner position detecting apparatuses for jog dials and mechanical products. Focusing on the fact that the phase difference between the magnetic fields in circumferential and radial directions generated by a magnetized ring is precisely 90 degrees, a position detecting apparatus of the present invention includes two Hall elements placed at a distance; a protective film provided on magnetic sensitive portions of the two Hall elements to cover the magnetic sensitive portions; a thin-film magnetic plate placed on the protective film to cover the magnetic sensitive portions of the two Hall elements; and further a processing circuit calculating the sum and difference of the signals from the two Hall elements to generate signals having an accurate phase difference of 90 degrees. The position detecting apparatus can therefore detect the rotation direction and precise rotation angle. | 01-12-2012 |
| 20110266630 | Semiconductor Device and Method for Manufacturing the Same - A configuration of a lateral transistor suited for the hybrid-integration (BiCMOS) of a high-performance lateral transistor (HCBT) and a CMOS transistor, and a method for manufacturing the lateral transistor are provided. A semiconductor device includes a HCBT | 11-03-2011 |
| 20110210422 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part. | 09-01-2011 |
| 20110175762 | SECOND ORDER NOISE COUPLING WITH ZERO OPTIMIZATION MODULATOR AND METHOD - A method and apparatus for a modified noise-coupled modulator using zero optimization technique is disclosed. By realizing the resonator coefficient as a part of branches other than those of the main transfer function, the problem of improving SQNR without degrading other specifications is solved. Second order noise coupling is used to implement zeros without using feedback branches going into the first integrator. Embodiments use a first-order modulator, second-order noise coupling and a resonator. It allows lower power consumption and smaller size by removing small capacitor values and gain factors and reducing the number of amplifiers. | 07-21-2011 |
| 20110037526 | OSCILLATOR - There is provided an oscillator using a high-frequency crystal resonator which can satisfy the drive level needed for the crystal resonator and expand a variable frequency range. An oscillator having an oscillation circuit CC for oscillating the resonator SS is provided with a limiter circuit LM | 02-17-2011 |
| 20110001554 | CHARGE PUMP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a charge pump circuit which is preferably used for reducing noise generated when electric charges are accumulated in a capacitor of the charge pump circuit. A load driving system | 01-06-2011 |
