| ARM Limited Patent applications |
| Patent application number | Title | Published |
|---|
| 20120131313 | Error recovery following speculative execution with an instruction processing pipeline - An instruction processing pipeline | 05-24-2012 |
| 20120131312 | Data processing apparatus and method - A data processing apparatus | 05-24-2012 |
| 20120126879 | Apparatus and method for controlling power gating in an integrated circuit - A technique for controlling power gating in an integrated circuit is provided. The integrated circuit comprises a block of components to be power gated, and power gating circuitry for selectively isolating the block of components from the source voltage supply in order to achieve such power gating. Voltage regulator circuitry is used to provide a control voltage to the power gating circuitry when performing such power gating operations, the control voltage being settable to any of a plurality of predetermined voltage levels. An adaptive controller receives operating parameter data from either or both of the block of components and the power gating circuitry, that operating parameter data being indicative of leakage current. The adaptive controller then issues a feedback control signal to the voltage regulator circuitry whose value is dependent on the received operating parameter data. The voltage regulator circuitry is then responsive to the feedback control signal to change the control voltage between the plurality of predetermined voltage levels, until the operating parameter data indicates that a desired leakage current has been obtained within the power gating circuitry. Such an approach enables a balance to be achieved between reducing leakage current and reducing wear out of the power gating circuitry. | 05-24-2012 |
| 20120124421 | Error management within a data processing system - A data processing system | 05-17-2012 |
| 20120124346 | Decoding conditional program instructions - A processor | 05-17-2012 |
| 20120124340 | Retirement serialisation of status register access operations - A processor | 05-17-2012 |
| 20120124337 | Size mis-match hazard detection - An out-of-order processor | 05-17-2012 |
| 20120124301 | Buffer store with a main store and an auxiliary store - A loop buffer is provided with a main store | 05-17-2012 |
| 20120124300 | Apparatus and method for predicting target storage unit - A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry. | 05-17-2012 |
| 20120110396 | Error handling mechanism for a tag memory within coherency control circuitry - A data processing system | 05-03-2012 |
| 20120110387 | TRACE SYNCHRONIZATION - A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream. | 05-03-2012 |
| 20120102303 | Exception control in a multiprocessor system - A data processing apparatus is provided with a plurality of processing units ( | 04-26-2012 |
| 20120089818 | Decoding instructions from multiple instructions sets - A data processing apparatus, method and computer program are described that are capable of decoding instructions from different instruction sets. The method comprising: receiving an instruction; if an operation code of said instruction is an operation code of an instruction from a base set of instructions decoding said instruction according to decode rules for said base set of instructions; and if said operation code of said instruction is an operation code of an instruction from at least one further set of instructions decoding said instruction according to a set of decode rules determined by an indicator value indicating which of said at least one further set of instructions is currently to be decoded. | 04-12-2012 |
| 20120081164 | Timing circuit and method of generating an output timing signal - A timing circuit and corresponding method are provided to generate an output timing signal in dependence on an input timing signal. The timing circuit comprises a plurality of circuit components, each circuit component configured to receive an input dependent on the input timing signal and to generate an output in dependence on that input. Each circuit component performs switching operations by switching its output level in response to a transition of its input level. Each circuit component exhibits a delay in switching its output level, the delay comprising a first delay associated with a first switching of its output level and a second delay associated with a second switching of its output level. The first switching is in an opposite direction to the second switching and the first delay and the second delay exhibit a change in magnitude as each circuit component repeatedly performs its switching operations. This change in magnitude is in opposite directions for the first delay and the second delay respectively, and the plurality of circuit components are arranged such that a timing of the output timing signal is dependent on both said first delay and said second delay, such that the effects of each on the timing of the output signal counteract one another. | 04-05-2012 |
| 20120081150 | Method of adapting standard cells - A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow. Then a local width of the current collection path at a selected distance from the maximum current location is determined, the local width being less than or equal to the maximum width, such that the local width satisfies the minimum path width requirement with respect to a maximum local current that will occur at the selected distance, the maximum local current being a sum of the current contributions from those current collection points which contribute to the local current. | 04-05-2012 |
| 20120079458 | Debugging of a data processing apparatus - A data processing apparatus is provided comprising processing circuitry and instruction decoding circuitry. The data processing apparatus is capable of operating at a plurality of different privilege. Processing circuitry of the data processing apparatus imposes on program instructions different access permissions to at least one of a memory and a set of registers at different ones of the different privilege levels. A debug privilege-level switching instruction is provided and decoding circuitry is responsive to this instruction to switch the processing circuitry from a current privilege level to a target privilege level if the processing circuitry is in a debug mode. However, if the processing circuitry is in a non-debug mode the instruction decoding circuitry prevents execution of the privilege-level switching instruction regardless of the current privilege level. | 03-29-2012 |
| 20120079254 | Debugging of a data processing apparatus - A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state. | 03-29-2012 |
| 20120079243 | Next-instruction-type-field - A graphics processing unit core | 03-29-2012 |
| 20120079211 | Coherency control with writeback ordering - Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry. | 03-29-2012 |
| 20120078987 | Vector floating point argument reduction - A processing apparatus is provided with processing circuitry | 03-29-2012 |
| 20120075321 | MONITORING GRAPHICS PROCESSING - A graphics processing apparatus is provided with rendering circuitry which separately renders different areas of a frame of pixel values. Monitoring circuitry coupled to the rendering circuitry captures for each area rendered one or more parameters and stores these parameters to a parameter memory. A performance frame can be generated from the captured and stored parameters with performance-representing pixel values for each area within the performance frame corresponding to an area within the image frame and having a visual characteristic selected in dependence upon the performance parameter which was captured. The visual characteristic may be a grey-scale value, a pixel intensity or a pixel colour. | 03-29-2012 |
| 20120066552 | Data processing apparatus, trace unit and diagnostic apparatus - A trace circuit | 03-15-2012 |
| 20120066481 | Dynamic instruction splitting - A data processing apparatus and method are provided. The data processing apparatus is configured to perform data processing operations in response to data processing instructions including a multiple operation instruction, in response to which multiple data processing operations are performed. The data processing apparatus comprises two or more data processing units configured to perform the data processing operations and an instruction arbitration unit configured to perform sub-division of a multiple operation instruction into a plurality of sub-instructions and to perform allocation of the plurality of sub-instructions amongst the two or more data processing units, wherein each sub-instruction is arranged to cause one of the two or more data processing units to perform at least one data processing operation of the multiple data processing operations. The instruction arbitration unit is configured to perform the sub-division and the allocation dynamically in dependence on a current availability of a resource for each of the two or more data processing units, enabling more efficient usage of the resources of each of the data processing units to be made. | 03-15-2012 |
| 20120059804 | Data compression and decompression using relative and absolute delta values - A data compressor is disclosed for receiving a data stream comprising a plurality of data items and for outputting a compressed data stream, said data compressor comprising: a data input for receiving said data stream; a delta value calculator for generating a compressed delta value, said delta value calculator being configured to receive said plurality of data items from said data input and being configured for at least some of said received data items to access said data store to determine if a related data item to said received data item is stored in said data store and: in response to said related data item being stored, to retrieve said related data item from said data store and to calculate a delta value from said received data item and said related data item and to output said delta value; and in response to said related data item not being stored in said data store to calculate a delta value from said received data item and a predetermined value and to output said delta value; a data store for storing said plurality of data items received at said data input; said data compressor further comprising: a data store controller for controlling the storage of said plurality of data items in said data store, said data store controller being configured to access said data store in response to receipt of a data item at said data input and to determine if a storage location is allocated to said data item and: if so to store said data item in said allocated storage location; and if not to allocate a storage location to said data item and to evict and discard any data stored in said allocated storage location and to store said data item in said allocated storage location. A data decompressor for decompressing the compressed data stream is also disclosed. | 03-08-2012 |
| 20120044957 | Time-division multiplexing processing circuitry - An integrated circuit | 02-23-2012 |
| 20120044608 | Receiver circuit with high input voltage protection - An integrated circuit | 02-23-2012 |
| 20120039393 | Video decoding apparatus and method - A video decoding apparatus for decoding an encoded video bitstream having frames of video data encoded in rows of macroblocks. The video decoding apparatus comprises a parsing unit configured to receive the encoded video bitstream and to interpret the encoded video bitstream to generate items of macroblock information to be used for reconstructing the video frames of video data. The parsing unit is configured to store the items of macroblock information in a memory in bitstream order. The video decoding apparatus further comprises a line control unit configured to generate line control information associated with each row of macroblocks, the line control information comprising a sequence of pointers to the items of macroblock information stored in the memory, such that sequentially reading the sequence of pointers accesses the items of macroblock information in raster scan order. The line control information is stored in said memory in association with said items of macroblock information. A reconstruction pipeline is configured to reconstruct the frames of video data with reference to the line control information. | 02-16-2012 |
| 20120036340 | Data processing apparatus and method using checkpointing - A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction. | 02-09-2012 |
| 20120036335 | Timing control circuit - A timing control circuit comprises at least three current control units coupled in parallel between a first circuit and a second circuit node. The current control units each have an active mode and an inactive mode. The current control units are responsive to a timing trigger event to pass current whose magnitude is dependent on how many of the current control units are in the active mode. The current control units comprise a plurality of groups. Current control units within a same group are responsive to a change in a bit of a control value corresponding to that group to switch together between the active and inactive modes, such that the magnitude of the current is dependent on which of the groups are in the active mode. The signal timing in the associated circuit is varied in dependence on the magnitude of the current. | 02-09-2012 |
| 20120030520 | Storage and output of trace data - A trace output unit for collecting, buffering and outputting trace data generated by trace circuitry monitoring processing activities of a data processing apparatus is described. The trace output unit comprises an input for receiving a stream of trace data; a plurality of data stores arranged in parallel with each other for storing the trace data; and storage control circuitry for controlling storage of items of the trace data in the data stores. The control circuitry is configured to route the trace items to selected ones of the data stores and to store control data identifying related trace items stored in different data stores. The trace output unit further comprises output control circuitry configured to identify related trace items stored in different data stores from the stored control data and to recombine the related trace items from different data stores to form an output trace data stream. | 02-02-2012 |
| 20120030499 | Distribution of an incrementing count value - Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount. | 02-02-2012 |
| 20120023382 | Data processing system and method for regulating a voltage supply to functional circuitry of the data processing system - A data processing system and method for regulating a voltage supply to functional circuitry of the data processing system is provided. The functional circuitry is configured to operate from a voltage supply whose voltage level is variable, the functional circuitry having at least one error correction circuit configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Voltage regulator circuitry provides the voltage supply to the functional circuitry, and modifies the voltage level of the voltage supply based on a feedback control signal. Error rate history circuitry receives error indications from the error correction circuit during operation of the functional circuitry and generates error rate history information therefrom. An adaptive controller then generates the feedback control signal in dependence on the error rate history information such that the adaptive controller adjusts the feedback control signal over time having regard to the error rate history information in order to obtain a predetermined target non-zero error rate within the functional circuitry. Such an approach enables a significant reduction in power consumption of the data processing system to be achieved. | 01-26-2012 |
| 20120014192 | Two stage voltage level shifting - A voltage level shifter for shifting an output signal from a first voltage level to a second voltage level and then to a further boosted second voltage level is disclosed. The voltage level shifter comprises: an input for receiving an input signal; an output for outputting an output signal; a first power supply input for connecting to a first voltage source supplying said first voltage level; a second power supply input for connecting to a second voltage source supplying said second voltage level; and a third power supply input for connecting to a third voltage source supplying said boosted second voltage level; said voltage level shifter being responsive to a predetermined change in said input signal to isolate said first power supply input from said output and to connect said second power supply input to said output and being responsive to said output signal attaining a predetermined value to connect said third power supply input to said output and to isolate said second power supply input from said output. | 01-19-2012 |
| 20120013319 | Power control apparatus and method - A power control apparatus for controlling a supply voltage for an associated circuit comprises a power input for receiving an input voltage and a power output for supplying the supply voltage to the circuit. A switch device is provided with a first terminal coupled to the power input, a second terminal coupled to the power output and a control terminal for receiving a sleep select signal. A control device selectively configures the switch device to act as either a power gating switch, in which the switch device is responsive to the sleep select signal to select whether or not to supply the input voltage to the power output; or a retention switch in which a voltage difference is formed between the power input and the power input and the switch device supplies a retention voltage to the power output, the retention voltage being different to the input voltage. | 01-19-2012 |
| 20120011291 | Apparatus and method for controlling issuing of transaction requests - Transaction requests requesting a service from the slave device are received from a master device at a transaction interface. The transaction requests are selectively issued to the bus system under control of an issue control circuit. A target outstanding transaction value N.x is received at a control interface. The target outstanding transaction value has an integer portion N and a fractional portion x. The issue control circuit controls the transaction interface to issue the transaction requests to the bus system in dependence upon the target outstanding transaction value so that a time averaged number of outstanding transaction requests corresponds to the target outstanding transaction value. | 01-12-2012 |
| 20120007878 | Switching between dedicated function hardware and use of a software routine to generate result data - An apparatus for processing data | 01-12-2012 |
| 20120006122 | Stress detection within an integrated circuit having through silicon vias - An integrated circuit | 01-12-2012 |
| 20120005454 | Data processing apparatus for storing address translations - Memory address translation buffering circuitry is provided comprising a primary storage bank and a secondary storage bank. Storage bank accessing circuitry is provided to perform a parallel lookup of the primary storage bank and the secondary storage bank for virtual to physical address translation entries. Buffering management circuitry is configured to transfer an address translation entry between the primary storage bank and the secondary storage bank dependent upon an occupancy level of at least one of the primary storage bank and secondary storage bank. | 01-05-2012 |
| 20110320651 | Buffering of a data stream - A data processing apparatus is provided comprising a buffer for buffering data contained in a data stream generated by a data stream generator and received by a data stream receptor. Buffer occupancy tracking circuitry is provided and configured to maintain a high buffer utilisation value providing an indication of a high buffer occupation level for a given time period during utilisation of the buffer. Alternatively, in an apparatus where the buffer is implemented in dedicated memory, the buffer occupancy tracking circuitry is configured to store a programmable buffer size limit controlling a maximum allowable buffer storage capacity. | 12-29-2011 |
| 20110314342 | Tracing speculatively executed instructions - A trace unit for generating items of trace data indicative of processing activities of a processor executing a stream of instructions, the stream of instructions comprising a plurality of groups of instructions, the processor executing at least some of the instructions speculatively is disclosed. The trace unit comprises: trace circuitry for monitoring a behaviour of the processor; storage circuitry for storing current trace control data for controlling the trace circuitry; a data store for storing at least some of the trace control data; the trace circuitry being configured to store the trace control data in the data store in response to detection of execution of the group of instructions; the trace circuitry being responsive to detecting the at least one processor cancelling at least one group of the speculatively executed instructions to retrieve at least some of the trace control data stored in the data store for the group of instructions executed before the cancelled speculatively executed instructions and to store the retrieved trace control data in the storage circuitry. | 12-22-2011 |
| 20110314340 | Correlating trace data streams - A data processing apparatus is provided with trace circuitry for generating a plurality of trace streams including an instruction trace stream | 12-22-2011 |
| 20110314264 | Key allocation when tracing data processing systems - A trace unit is provided which is configured to generate items of trace data indicative of processing activities, of a data processing unit. The trace unit comprises a trace indexing unit configured to associate an index value with at least a subset of the items of trace data generated by the trace unit. The trace indexing unit is configured to generate each index value as one of a predetermined sequence of index values, wherein an n+1 | 12-22-2011 |
| 20110314224 | Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus - An apparatus and method are provided for handling access operations issued to local cache structures within a data processing apparatus. The data processing apparatus comprises a plurality of processing units each having a local cache structure associated therewith. Shared access coordination circuitry is also provided for coordinating the handling of shared access operations issued to any of the local cache structures. For a shared access operation, the access control circuitry associated with the local cache structure to which that shared access operation is issued will perform a local access operation to that local cache structure, and in addition will issue a shared access signal to the shared access coordination circuitry. For a local access operation, the access control circuitry would normally perform a local access operation on the associated local cache structure, and not notify the shared access coordination circuitry. However, if an access operation extension value is set, then the access control circuitry treats such a local access operation as a shared access operation. Such an approach ensures correction operation even after an operating system and/or an application program are migrated from one processing unit to another. | 12-22-2011 |
| 20110307664 | Cache device for coupling to a memory device and a method of operation of such a cache device - A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilisation, thereby giving rise to both performance improvements and power consumption reductions. | 12-15-2011 |
| 20110302460 | Apparatus and method for detecting an approaching error condition - An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus. The data processing apparatus includes a second sequential storage structure which is arranged to latch the output signal generated by combinatorial circuitry dependent on a second clock signal. The second sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry, and transition detection circuitry for detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct. The second sequential storage structure can be operated in either a first mode of operation or a second mode of operation. In the first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal, to thereby enable an approaching setup timing error due to a propagation delay within the combinatorial circuitry to be detected. In the second mode of operation, the predetermined timing window is a timing window after the time at which the main storage element latches said value of the output signal such that an approaching hold timing error due to an increase in skew between the first and second clock signals is detected. Such a technique provides a simple and efficient mechanism for detecting a variety of approaching error conditions whilst the second sequence storage structure continues to operate correctly. | 12-08-2011 |
| 20110298550 | Ultra low power oscillator - A frequency generator is provided which is embodied in an integrated circuit manufactured at a process node below 100 nm. The frequency generator comprises a current starved oscillator configured to generate an output frequency signal in dependence on a voltage of a bias signal and a self-biased current generator configured to generate the bias signal, wherein the self-biased current generator comprises a first transistor and a second transistor connected in series. The bias signal is taken from a midpoint between the first transistor and the second transistor, and respective gates of the first and second transistors are connected to keep said first and second transistors in a cut-off state. Accordingly the self-biased current generator operates in a deep sub-threshold state and a current of said bias signal is dependent on a leakage current in the first and second transistors. | 12-08-2011 |
| 20110298517 | Master-slave flip-flop circuit - A master-slave flip-flop circuit comprises a master stage for retaining a master signal, a slave stage for retaining a slave signal and a retention stage. During a normal mode of operation, the retention stage captures a retention signal having a value dependent upon the slave signal. During a retention mode of operation, the retention stage isolates the retention signal from changes in the stage signal and retains the retention signal. During the retention mode the retention stage also provides a master restore signal to the master stage and provides a slave restore signal to the slave stage. The master restore signal and the slave restore signal have values dependent on the retention signal for configuring the master stage and slave stage such that the master and slave signals have values corresponding to the retention signal. | 12-08-2011 |
| 20110298516 | Clock state independent retention master-slave flip-flop - A master-slave flip-flop circuit is provided with a retention capability to support operation in both a normal mode and a retention mode. During the retention mode the retention circuitry drives the output signal via either a first path | 12-08-2011 |
| 20110291731 | Integrated circuit with timing adjustment mechanism - An integrated circuit | 12-01-2011 |
| 20110288809 | Communication of a diagnostic signal and a functional signal by an integrated circuit - An integrated circuit | 11-24-2011 |
| 20110276966 | Managing task dependency within a data processing system - A processing apparatus includes task manager circuitry | 11-10-2011 |
| 20110276848 | Data processing apparatus and method for testing a circuit block using scan chains - A data processing apparatus comprises a circuit block to be tested, and a plurality of scan chains, each scan chain providing a mechanism for providing input test data to, and receiving output test data from, at least a portion of the circuit block during a test mode of operation. Configurable decompression circuitry is provided for supporting a plurality of decompression schemes associated with more than one test generation tool, and configuration circuitry is responsive to a configuration stimulus to configure the configurable decompression circuitry to implement a selected decompression scheme. Thereafter, on receipt of compressed input test data, the configurable decompression circuitry applies the selected decompression scheme to the compressed input test data to produce the input test data to be provided to the plurality of scan chains. Configurable compression circuitry can also be provided in a similar manner, with the configuration stimulus being used to configure the configurable compression circuitry to implement a selected compression scheme to be applied to the output test data in order to produce compressed output test data to be issued from an output interface. Such a mechanism provides a particularly flexible approach for supporting compression and decompression schemes in association with the data input to, and output from, the plurality of scan chains. | 11-10-2011 |
| 20110276614 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A RECIPROCAL OPERATION ON AN INPUT VALUE TO PRODUCE A RESULT VALUE - A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step performing the computation: X | 11-10-2011 |
| 20110271126 | Data processing system - A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units. | 11-03-2011 |
| 20110264887 | Preload instruction control - A processor | 10-27-2011 |
| 20110264827 | Performance by reducing transaction request ordering requirements - A data processing apparatus is disclosed that is configured to communicate via an output port with a plurality of devices and to issue a stream of transaction requests to the output port, the stream of transaction requests comprising at least some device transaction requests destined for the plurality of devices. Device transactions are transactions that may affect each other and therefore should be completed in an order in which they are received at the output port in. The output port is configured to output the received transaction requests as a single serial stream of transaction requests. The data processing apparatus comprises: a destination device detector for monitoring the device transaction requests and for determining which of the plurality of devices each of the device transaction requests are destined for; the output port comprises ordering circuitry configured to treat the plurality of devices as at least two subsets of devices, at least one of the subsets comprising at least two devices; the ordering circuitry being configured to receive the stream of transaction requests and to classify each of the device transaction requests into one of the at least two subsets in response to determination of a destination device by said destination device detector, and to maintain said order that said device transaction requests within each subset are received in, such that device transaction requests within each subset are output by the output port and executed by their respective destination devices in the received order, while device transaction requests within different subsets may be output in an order that is different to the received order. | 10-27-2011 |
| 20110261633 | Memory with improved data reliability - An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory cells, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means of the common word line signal, a read data value is determined in dependence on a voltage of the shared bit line, dependent on data values stored in the at least three memory cells. If, at a time of the read operation, one of the at least three memory cells holds a complement value of the written data value, the voltage of the shared bit line nonetheless has a value such that the read data value is determined with the same value as the written data value. | 10-27-2011 |
| 20110249481 | Generating ROM bit cell arrays - A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area. Thus the system designer can reuse an existing memory architecture, yet still retain an advantageous degree of flexibility with regard to performance characteristic selection of the final ROM bit cell array. | 10-13-2011 |
| 20110246843 | ERROR DETECTION IN PRECHARGED LOGIC - An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged. | 10-06-2011 |
| 20110231691 | Synchronization in data processing layers - A data processing apparatus is provided having a hierarchy of layers comprising at least two data processing layers, each data processing layer configured to receive data and to generate processed data for passing to a next lower layer in said hierarchy, according to a protocol specific to that data processing layer. Each data processing layer is configured intermittently to add synchronization information to its processed data, the synchronization information providing semantic information required to interpret the processed data. Each data processing layer is further configured to output its synchronization information in response to a synchronization request signal received from a lower layer in said hierarchy, and at least one data processing layer is configured, when outputting its synchronization information, to issue its synchronization request signal to a higher layer in the hierarchy. | 09-22-2011 |
| 20110231633 | Operand size control - A data processing system | 09-22-2011 |
| 20110231461 | Identifier selection - A data processing apparatus is provided which is configured to select 2 | 09-22-2011 |
| 20110225555 | Structural feature formation within an integrated circuit - An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts | 09-15-2011 |
| 20110225402 | Apparatus and method for handling exception events - Processing circuitry | 09-15-2011 |
| 20110225397 | Mapping between registers used by multiple instruction sets - A processor | 09-15-2011 |
| 20110225389 | Translation table control - Memory address translation circuitry | 09-15-2011 |
| 20110219376 | Method, apparatus and trace module for generating timestamps - The present invention relates to the field of data processing, in particular, a method, apparatus | 09-08-2011 |
| 20110213935 | Data processing apparatus and method for switching a workload between first and second processing circuitry - A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. The switch controller is arranged, during the handover operation, to cause the source processing circuitry to make its current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory shared between the first and second processing circuitry at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. Further, the source processing circuitry and second processing circuitry implement an accelerated mechanism to make the current architectural state available to the destination processing circuitry without routing of the current architectural state via the shared memory. Since the accelerated mechanism is quick and energy efficient, it increases the number of situations it which it is energy efficient to make the switch from one processing circuitry to the other. | 09-01-2011 |
| 20110213934 | Data processing apparatus and method for switching a workload between first and second processing circuitry - A data processing apparatus and method are provided for switching performance of a workload between two processing circuits. The data processing apparatus has first processing circuitry which is architecturally compatible with second processing circuitry, but with the first processing circuitry being micro-architecturally different from the second processing circuitry. At any point in time, a workload consisting of at least one application and at least one operating system for running that application is performed by one of the first processing circuitry and the second processing circuitry. A switch controller is responsive to a transfer stimulus to perform a handover operation to transfer performance of the workload from source processing circuitry to destination processing circuitry, with the source processing circuitry being one of the first and second processing circuitry and the destination processing circuitry being the other of the first and second processing circuitry. During the handover operation, the switch controller causes the source processing circuitry to makes it current architectural state available to the destination processing circuitry, the current architectural state being that state not available from shared memory at a time the handover operation is initiated, and that is necessary for the destination processing circuitry to successfully take over performance of the workload from the source processing circuitry. In addition, the switch controller masks predetermined processor specific configuration information from the at least one operating system such that the transfer of the workload is transparent to that operating system. Such an approach has been found to yield significant energy consumption benefits whilst avoiding complexities associated with providing operating systems with the capability for switching applications between processing circuits. | 09-01-2011 |
| 20110208935 | Storing secure mode page table data in secure and non-secure regions of memory - Apparatus for data processing | 08-25-2011 |
| 20110206133 | Parallel parsing in a video decoder - A video decoder configured to decode an encoded video bitstream comprises a first parsing unit and a second parsing unit, each configured to independently parse the encoded video bitstream to derive parsing state information therefrom on which subsequent parsing of the encoded video bitstream at least partially depends and to identify macroblock information for decoding. The encoded video bitstream comprises frame header information defining a sequence of frames and each frame is composed of macroblocks represented by macroblock information. A control unit of the video encoder allocates each frame of macroblock information to one of the two parsing units to parse. The two parsing units are both configured to parse frame header information to thereby each derive parsing state information for the encoded video bitstream, and the two parsing unit are each configured to parse macroblock information allocated to them, skipping macroblock information allocated to the other parsing unit. | 08-25-2011 |
| 20110202801 | Trace data priority selection - An integrated circuit | 08-18-2011 |
| 20110202740 | Storing secure page table data in secure and non-secure regions of memory - Apparatus for data processing | 08-18-2011 |
| 20110202739 | Restricting memory areas for an instruction read in dependence upon a hardware mode and a security flag - An apparatus for processing data | 08-18-2011 |
| 20110202726 | Apparatus and method for handling data in a cache - A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system. | 08-18-2011 |
| 20110191543 | Area and power efficient data coherency maintenance - An apparatus for storing data that is being processed is disclosed. The apparatus comprises: a cache associated with a processor and for storing a local copy of data items stored in a memory for use by the processor, monitoring circuitry associated with the cache for monitoring write transaction requests to the memory initiated by a further device, the further device being configured not to store data in the cache. The monitoring circuitry is responsive to detecting a write transaction request to write a data item, a local copy of which is stored in the cache, to block a write acknowledge signal transmitted from the memory to the further device indicating the write has completed and to invalidate the stored local copy in the cache and on completion of the invalidation to send the write acknowledge signal to the further device. | 08-04-2011 |
| 20110191539 | Coprocessor session switching - A data processing apparatus is provided, configured to carry out data processing operations on behalf of a main data processing apparatus, comprising a coprocessor core configured to perform the data processing operations and a reset controller configured to cause the coprocessor core to reset. The coprocessor core performs its data processing in dependence on current configuration data stored therein, the current configuration data being associated with a current processing session. The reset controller is configured to receive pending configuration data from the main data processing apparatus, the pending configuration data associated with a pending processing session, and to store the pending configuration data in a configuration data queue. The reset controller is configured, when the coprocessor core resets, to transfer the pending configuration data from the configuration data queue to be stored in the coprocessor core, replacing the current configuration data. | 08-04-2011 |
| 20110187438 | Reducing current leakage in a semiconductor device - An integrated circuit, method of controlling power supplied to semiconductor devices, a method of designing an integrated circuit and a computer program product are disclosed. The integrated circuit comprises: a semiconductor device for handling data; a power source for powering said semiconductor device, said power source comprising a high voltage source for supplying a high voltage level and a low voltage source for supplying a low voltage level; a plurality of switching devices arranged between at least one of the high or low voltage sources and the semiconductor device. There is also a control device for controlling a first set of the plurality of switching devices to connect one of the high or low voltage sources to the semiconductor device and for controlling a second set of the plurality of switching devices to connect the one of the high or low voltage sources to the semiconductor device. At least some of the first set of the plurality of switching devices have a higher resistance when closed and providing a connection than at least some of the second set of the plurality of switching devices such that when the first set of the plurality of switching devices connect the semiconductor device to the one of the voltage sources the semiconductor device operates with a lower performance than when the second set of the plurality of switching devices connect the semiconductor device to the one of said voltage sources. | 08-04-2011 |
| 20110181343 | Power controlling integrated circuit and retention switching circuit - A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device. A further data structure corresponding to a standard cell is provided comprising an overdriven retention switching device and a voltage switching device and yet a further standard cell data structure is provided comprising an overdriven voltage switching device. | 07-28-2011 |
| 20110179309 | Debugging a multiprocessor system that switches between a locked mode and a split mode - A data processing system | 07-21-2011 |
| 20110179308 | Auxiliary circuit structure in a split-lock dual processor system - A multiple-processor system | 07-21-2011 |
| 20110179255 | Data processing reset operations - A processor | 07-21-2011 |
| 20110173482 | Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operations - A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data. Each of the processing circuitry and the redundant copy include checking circuitry for determining whether the speculative processing was correct, and initiating corrective action if the speculative processing was not correct. By sharing the prediction circuitry rather than replicating it within both the processing circuitry and the redundant copy, significant area and power consumption benefits can be achieved without affecting the ability of the apparatus to detect faults. | 07-14-2011 |
| 20110167247 | System for efficiently tracing data in a data processing system - A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program instruction; tracing circuitry for tracing operation of the data processing apparatus for outputting a prediction indicator indicating whether or not the predicted response is correct; a data store configured to store information relating to the predicted response of said data processing circuitry at the given execution point for use by at least one of said prediction logic and said tracing circuitry a later execution point; and a history buffer configured to store historical information with regard to one or more entries of the data store at a corresponding execution point previous to the given execution point to enable restoration of said data store to a state corresponding to said previous execution point. | 07-07-2011 |
| 20110158021 | Reducing peak currents required for precharging data lines in memory devices - A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal. The plurality of switching devices each comprising at least two switches, the at least two switches comprising a data output switch controlled by the data output request signal and a power switch controlled by the power mode signal, the plurality of switching devices connecting the output lines to the predetermined voltage in response to both the power mode signal indicating an operational mode and the data output request signal indicating data is to be output; wherein the power mode switch is configured to have a higher capacitance than the data output switch. | 06-30-2011 |
| 20110150090 | Video encoder - A video encoding apparatus for encoding a video stream comprising: a reference frame cache configured to cache reference frame video data retrieved from a reference frame storage unit in external memory, the reference frame video data cached in the reference frame cache being derived from an individual frame of the video stream; a first source frame storage unit configured to store a first block of unencoded video data taken from a first source frame of the video stream; a second source frame storage unit configured to store a second block of unencoded video data taken from a second source frame of the video stream; a first video encoder configured to perform a first encoding operation to encode the first block of unencoded video data with reference to the reference frame video data cached in the reference frame cache; and a second video encoder configured to perform a second encoding operation to encode said second block of unencoded video data with reference to the reference frame video data cached in the reference frame cache, wherein the first video encoder and the second video encoder are configured to perform the first encoding operation and the second encoding operation in parallel with one another. | 06-23-2011 |
| 20110148892 | Forming a windowing display in a frame buffer - A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile | 06-23-2011 |
| 20110145646 | Use of statistical representations of traffic flow in a data processing system - An apparatus and method are provided for performing verification tests for a design of a data processing system. The apparatus comprises a system under verification representing at least part of the design of the data processing system, and a transactor for connecting to an interface of the system under verification, and for generating signals for input to the system under verification via the interface during performance of the verification tests. Profile storage stores a profile providing a statistical representation of desired traffic flow at the interface, the statistical representation providing statistical information for a plurality of traffic attributes and also identifying at least one dependency between such traffic attributes. The transactor then references the profile in order to determine the signals to be generated, such that the signals generated take account of the specified dependencies identified in the profile. Such a mechanism enables the transactor to more realistically replicate the traffic flow that will be observed in the real system. Another aspect to the present invention provides a mechanism for generating such profiles. | 06-16-2011 |
| 20110141837 | Voltage regulation circuitry - Voltage regulation circuitry is provided comprising a pull-up p-type threshold device connecting a supply voltage node to an output voltage node, the pull-up p-type threshold device configured to be switched off in dependence on a control signal. A pull-down stack connects the output voltage node to a reference voltage node, the pull-down stack comprising a pull-down p-type threshold device and a pull-down n-type threshold device connected in series. An inverter is configured to receive an input from the output voltage node and is configured to generate a cut-off signal, wherein the pull-down n-type threshold device is configured to be switched on in dependence on the control signal and the pull-down p-type threshold device is configured to be switched off in dependence on the cut-off signal. | 06-16-2011 |
| 20110125986 | Reducing inter-task latency in a multiprocessor system - A method of reducing inter-task latency for software comprising a sequence of instructions including a synchronous remote procedure call to be executed on a multiprocessor system comprising a calling processor and at least one remote engine. The method comprises the steps of: inputting the software; inputting a runtime resource description describing a runtime environment of the multiprocessor system; identifying the synchronous remote procedure call in the sequence of instructions; replacing the synchronous remote procedure call in the sequence of instructions with an initiation instruction and a wait instruction to generate a substitute sequence of instructions; reordering the substitute sequence of instructions with reference to the runtime resource description and the dependencies to generate a reordered sequence of instructions; and outputting the reordered sequence of instructions. | 05-26-2011 |
| 20110125944 | Synchronising activities of various components in a distributed system - An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a barrier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronise request. | 05-26-2011 |
| 20110122712 | Controlling voltage levels applied to access devices when accessing storage cells in a memory - A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line. | 05-26-2011 |
| 20110121876 | State retention circuit and method of operation of such a circuit - A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal. As a result, the isolation structure isolates the storage element from the input during the retention mode of operation, causing the storage element to retain its stored state prior to entry of the retention mode of operation irrespective of changes in the clock signal or changes in the input during the retention mode of operation. Such a design provides a clock independent pulse retention storage structure of small area, high performance and low energy consumption. | 05-26-2011 |
| 20110107166 | Error recovery within integrated circuit - An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate. | 05-05-2011 |
| 20110106871 | Apparatus and method for performing multiply-accumulate operations - A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques. | 05-05-2011 |
| 20110106868 | Floating point multiplier with partial product shifting circuitry for result alignment - A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount determining circuitry | 05-05-2011 |
| 20110103400 | Check data encoding using parallel lane encoders - An encoder for generating check data to accompaning payload data uses parallel lane encoders | 05-05-2011 |
| 20110102446 | Graphics processing systems - A graphics processor | 05-05-2011 |
| 20110102091 | Operating parameter monitor for an integrated circuit - An integrated circuit | 05-05-2011 |
| 20110102072 | Power management of an integrated circuit - An integrated circuit | 05-05-2011 |
| 20110101998 | Operating parameter monitoring circuit and method - A monitoring circuit | 05-05-2011 |
| 20110099451 | Error control coding for single error correction and double error detection - An error correction coding is provided that generates P bits of check data from K M-bit words of payload data. The P bits of check data include an address field A, a bit error indicating field E and an auxiliary field P−(E+A). The address field encodes a set of error addresses which has a cardinality equal to the bit size K of the payload data and providing a one-to-one mapping between values of the address field and the locations of a single bit error within the payload data. The bit error indicating field indicates if a bit error is present. The auxiliary field is a minimum size bit vector such that together with the address field and the bit area indicating field it provides a checksum for a systematic code for the payload data with a minimum Hamming distance serving to provide either single error correction capability or single error correction and double error detection capability. | 04-28-2011 |
| 20110095804 | Apparatus and method providing an interface between a first voltage domain and a second voltage domain - An interface between first and second voltage domains is provided. A level shifter is configured to receive an input signal from the first voltage domain and to level shift the input signal to provide an output signal for passing to the second voltage domain. A control signal generator is configured to generate a second voltage domain control signal in dependence on at least one first voltage domain control signal from a controller in the first voltage domain. The level shifter is configured to be in a retention state when the second voltage domain control signal has a first value, such that its output signal is held constant even when the controller becomes not actively driven by the first voltage supply. The level shifter is configured to be in a transmission state when the second voltage domain control signal has a second value, wherein the output signal depends on the input signal. | 04-28-2011 |
| 20110093750 | Hardware resource management within a data processing system - A processor | 04-21-2011 |
| 20110093723 | Display of a verification image to confirm security - A handheld device | 04-21-2011 |
| 20110093686 | Register state saving and restoring - In a data processing apparatus | 04-21-2011 |
| 20110093683 | Program flow control - A data processing apparatus includes a data engine | 04-21-2011 |
| 20110093557 | Maintaining required ordering of transaction requests in interconnects using barriers and hazard checks - Interconnect circuitry for a data processing apparatus with a hazard checker for eliminating barrier transaction requests is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device The interconnect circuitry comprises: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing the received transaction requests from the at least one input to the at least one output; wherein the control circuitry is configured to maintain an ordering of at least some transaction requests with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests that occur before the barrier transaction request in the stream of transaction requests with respect to at least some of the transaction requests that occur after the barrier transaction request in the stream of transaction requests. The interconnect circuitry comprises hazard checking circuitry for checking a stream of transaction requests and comparing a transaction request within the stream of transaction requests against earlier outstanding transaction requests that have not yet completed, to determine if the transaction request may potentially generate a data hazard, and in response to detecting a potential hazard between the transaction request and at least one of the outstanding transaction requests the hazard checking circuitry is configured to stall the transaction request until the at least one outstanding transaction request has completed; and barrier termination circuitry associated with the hazard checking circuitry for detecting a barrier transaction request within the stream of transaction requests and terminating the barrier transaction request. | 04-21-2011 |
| 20110087858 | Memory management unit - A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided. | 04-14-2011 |
| 20110087819 | Barrier transactions in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained. | 04-14-2011 |
| 20110087809 | Reduced latency barrier transaction requests in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the interconnect circuitry comprising: at least one input for receiving transaction requests from the at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said control circuitry comprises a response signal generator, said response signal generator being responsive to receipt of said barrier transaction request to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further. | 04-14-2011 |
| 20110085391 | Memory with improved read stability - A static random access memory is disclosed. The SRAM comprises: at least one data line for transferring data to and from the memory and at least one reset line; a plurality of storage cells each being arranged for connection to the at least one data line and the at least one reset line, each storage cell comprising: an asymmetric feedback loop, the feedback loop comprising a first access node for holding a data value when the feedback loop stores the data value and a second access node for holding a complementary version of the data value when the feedback loop stores the data value; an access device for selectively providing a connection between the at least one data line and the first access node; a reset device for selectively providing a connection between the at least one reset line and the second access node; the memory further comprising: data access control circuitry for generating control signals in response to data access requests for independently controlling the access device and the reset device to provide the connections; wherein: the data control circuitry is configured to: generate a data access control signal to trigger the access device to provide the connection between the first access node and the at least one data line in response to a write request to write a predetermined value to the storage cell, and in response to a read request to read a stored value from the storage cell; and generate a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell. | 04-14-2011 |
| 20110080959 | Video reference frame retrieval - A video data processing apparatus is provided comprising processing circuitry for performing video processing operations requiring access to video reference frames, and a memory management unit configured to translate virtual addresses into physical addresses. Translation circuitry is provided responsive to a memory access request for reference frame pixel data issued by the processing circuitry to perform a translation process on video reference frame information such that the set of input values for at least one hash function in the memory management unit comprises video reference frame identifier bits contained with the video reference frame information. This approach has been found to reduce the frequency of aliasing in the memory management unit when retrieving video reference frames. | 04-07-2011 |
| 20110080419 | Methods of and apparatus for controlling the reading of arrays of data from memory - A display controller reads blocks of data from a frame buffer and stores them in a local memory buffer of the display controller before outputting the blocks of data to a display. The display controller uses similarity meta-data associated with the output frame in the frame buffer to determine whether a new block of data to be processed for display is similar to a block of data already stored in the local memory of the display controller or not. If it is determined that the data block to be processed is similar to a data block already stored in the local buffer of the display controller, the display controller does not read a new data block from the frame buffer but instead provides the existing data block in its buffer to the display. | 04-07-2011 |
| 20110074800 | Method and apparatus for controlling display operations - A graphics processing system includes a graphics processor | 03-31-2011 |
| 20110074765 | Graphics processing system - A transaction elimination hardware unit | 03-31-2011 |
| 20110072323 | Supporting scan functions within memories - A memory is disclosed comprising: a storage array for storing data; and access circuitry for transmitting data to and from the storage array. The access circuitry forms a data path for inputting and outputting data to the storage array. The access circuitry comprises a latch configured to latch in response to a first phase of a first clock signal and a further latch configured to latch in response to a second phase of a second clock signal, the further latch comprises an output latch for outputting the data from the storage array, and the first and second clock signals are synchronised with each other. The memory further comprises: a multiplexer, a scan input and a scan enable input, the multiplexer being responsive to an asserted scan enable signal at the scan enable input to form a scan path comprising the latch and the further latch connected together to form a master slave flip flop, such that scan data input at the scan input passes through the master slave flip flop and not through the storage array while the scan enable signal is asserted and is output by the output latch. | 03-24-2011 |
| 20110072178 | Data processing apparatus and a method for setting priority levels for transactions - A data processing apparatus and method for setting priority levels for transactions is provided. The data processing apparatus has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The at least one master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry is used to apply an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource, the arbitration policy using the priority level associated with each of the multiple transactions when performing the selection. Adaptive priority circuitry is associated with at least one of the sources, the adaptive priority circuitry monitoring throughput indication data for previously issued transactions from the associated source, and for each new transaction from the associated source, setting the priority level to one of a plurality of predetermined priority levels dependent on the throughput indication data. Through such a mechanism, the adaptive priority circuitry sets the lowest priority level from amongst the plurality of predetermined priority levels that will enable a specified target throughput to be achieved. The adaptive priority circuitry hence uses a feedback mechanism to control the priority level assigned to each new transaction from a source in order to target a specified throughput for the source, and through this mechanism finds the lowest priority necessary to achieve the throughput objectives independent of the activity of other sources within the system. | 03-24-2011 |
| 20110068842 | Providing additional inputs to a latch circuit - A latch circuit for retaining and transmitting an input data value is disclosed, along with a memory, and a method for retaining and transmitting data. | 03-24-2011 |
| 20110066922 | Error correction for multilevel flash memory - An integrated circuit is provided with an array of multilevel flash memory cells. In one embodiment these flash memory cells have a storage signal level which is Gray coded to output data bits thereby increasing the independence between bit errors. The error correction circuitry targets independent identical distributed error patterns. In another embodiment, the storage signal levels are read to generate n-bit symbols which are then subject to error correction with an error correction mechanism targeted at the error properties of those n-bit symbols. The data is read in sets of symbols such that the error correction targeted at those symbols will be more efficient. | 03-17-2011 |
| 20110051487 | Read only memory cell for storing a multiple bit value - A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value. | 03-03-2011 |
| 20110047411 | Handling of errors in a data processing apparatus having a cache storage and a replicated address storage - A data processing apparatus and method are provided for handling errors. The data processing apparatus comprises processing circuitry for performing data processing operations, a cache storage having a plurality of cache records for storing data values for access by the processing circuitry when performing the data processing operations, and a replicated address storage having a plurality of entries, each entry having a predetermined associated cache record within the cache storage and being arranged to replicate the address indication stored in the associated cache record. On detecting a cache record error when accessing a cache record of the cache storage, a record of a cache location avoid storage is allocated to store a cache record identifier for the accessed cache record. On detection of an entry error when accessing an entry of the replicated address storage, use of the address indication currently stored in that accessed entry of the replicated address storage is prevented, and a command is issued to the cache location avoid storage. In response to the command, a record of the cache location avoid storage is allocated to store the cache record identifier for the cache record of the cache storage associated with the accessed entry of the replicated address storage. Any cache record whose cache record identifier is stored in the cache location avoid storage is logically excluded from the plurality of cache records of the cache storage for the purposes of subsequent operation of the cache storage. Such an approach enables errors to be correctly handled, prevents errors from spreading in a system, and minimises communication necessary on detection of an error in a data processing apparatus having both a cache storage and a replicated address storage. | 02-24-2011 |
| 20110047408 | Handling of hard errors in a cache of a data processing apparatus - A data processing apparatus and method are provided for handling hard errors. The data processing apparatus comprises processing circuitry for performing data processing operations, and cache storage having a plurality of cache records for storing data values for access by the processing circuitry when performing the data processing operations. A cache record error storage having at least one error record, and a hard error storage having at least one hard error record, are provided for keeping track of errors detected when accessing cache records of the cache storage. In particular, when an error is first detected for a particular cache record, one of the error records in the cache record error storage is allocated to store a cache record identifier for that cache record, and an associated count value is set to a first value. Further, if an error is detected when accessing a cache record, a correction operation is performed in respect of that currently accessed cache record, and access to that currently accessed cache record is then re-performed. Each time an error is detected for subsequent accesses to that cache record, the count value is incremented, and each time an error is not detected when that cache record is accessed, the count value is decremented. If the count value reaches a predetermined threshold value, then the cache record identifier is moved from the cache record error storage to an error record of the hard error storage. Any cache record whose cache record identifier is stored in the hard error storage is logically excluded from the plurality of cache records of the cache storage for the purposes of subsequent operation of the cache storage. Such an approach provides a hardware mechanism that automatically identifies and corrects hard and soft errors, but only masks from further use those cache records affected by hard errors. | 02-24-2011 |
| 20110040815 | Apparatus and method for performing fused multiply add floating point operation - A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus | 02-17-2011 |
| 20110035589 | Content usage monitor - A trusted content usage monitor for monitoring content usage is provided. A unique identifier generation unit generates a unique identifier indicative of content being rendered and a packet generator generates a trusted packet comprising the unique identifier. The trusted packet is trust signed by the trusted content usage monitor, so that it can be trusted by its recipient. The trusted content usage monitor has at least one mode of operation in which content rendering cannot be decoupled from operation of the unique identifier generation unit, so that generated packets can be trusted as truly indicative of content usage. | 02-10-2011 |
| 20110029823 | Techniques for generating a trace stream for a data processing apparatus - A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles. | 02-03-2011 |
| 20110022802 | Controlling data accesses to hierarchical data stores to retain access order - Data storage circuitry for controlling access to data stored in a memory is disclosed. The data storage circuitry comprises: a data store for storing a subset of the data stored in the memory; access circuitry for receiving access requests and for outputting the requested data, at least some of the received access requests being ordered access requests requiring the accessed data to be output in a same order as the access requests are received in; control circuitry for controlling access to the data; and retrieval circuitry for retrieving the data from the memory; wherein the control circuitry is responsive to an access request received from the access circuitry to access the data store and in response to detecting a miss in the data store when the requested data is not stored in the data store to transmit the access request to the retrieval circuitry; the retrieval circuitry being configured to retrieve requested data from the memory in response to the access request and to store the data in the data store and being responsive to no asserted output inhibit signal associated with the data access request to transmit the retrieved data to the access circuitry for output and being responsive to an asserted output inhibit signal associated with the data access request not to transmit the retrieved data to the access circuitry; the data storage circuitry further comprising detection circuitry for detecting an earlier ordered access request that misses in the data store and a later ordered access request that hits while the earlier ordered access request is pending, the data storage circuitry being configured to halt the later ordered access request and in response to receipt of a subsequent ordered access request while the earlier ordered request is still pending to assert an output inhibit signal associated with the subsequent ordered access request and in response to detection of completion of the earlier ordered access request to deassert the output inhibit signal. | 01-27-2011 |
| 20110013699 | Video processing apparatus and a method of processing video data - A video processing apparatus and method are provided, the video processing apparatus comprising first stage video processing circuitry and second stage video processing circuitry. The first stage video processing circuitry receives input video data and performs one or more processing operations on the input video data to generate an intermediate representation of the input video data. The intermediate representation comprises first and second separate data portions, with the first data portion containing transient data derived from the input video data and the second data portion containing long term data derived from the input video data. Transient data is only required for processing of a single video frame, whilst the long term data is required for processing of at least two video frames. The first stage video processing circuitry is arranged to output the first and second separate data portions for storing in a buffer, and the second stage video processing circuitry then retrieves the first and second data portions from the buffer and performs one or more further processing operations on those data portions in order to generate output video data. The transient data is compressed prior to being stored in the buffer, and then decompressed when retrieved from the buffer by the second stage video processing circuitry. Such an approach enables the operations of the second stage video processing circuitry to be decoupled from the operations of the first stage video processing circuitry, whilst reducing the storage capacity requirements of the buffer. | 01-20-2011 |
| 20110004743 | Pipe scheduling for pipelines based on destination register number - A data processing apparatus | 01-06-2011 |
| 20110001538 | Voltage level shifter - A voltage level shifter is provided for receiving an input signal from an input voltage domain and converting said signal to a shifted signal in a shifted voltage domain. The voltage level shifter has an input, switching circuitry, a pass transistor and an output. The switching circuitry is configured to isolate an output of said pass transistor from said supply voltage rail when said input voltage domain corresponds to a logical zero. | 01-06-2011 |
| 20100332942 | Memory controller for NAND memory using forward error correction - A memory controller | 12-30-2010 |
| 20100332805 | Remapping source Registers to aid instruction scheduling within a processor - An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard. | 12-30-2010 |
| 20100329345 | Motion vector estimator - A data processing apparatus is provided which is configured to receive a down-sampled source block and a down-sampled reference frame portion. The data processing apparatus comprises interpolation circuitry configured to interpolate between pixels of the down-sampled reference frame portion to generate a set of interpolated down-sampled reference frame blocks. Cost function calculation circuitry calculates a cost function value indicative of a difference between the down-sampled source block and each interpolated down-sampled reference frame block. Minimisation circuitry identifies the lowest cost function value and estimation motion vector generation circuitry generates an estimate motion vector independence thereon. | 12-30-2010 |
| 20100329044 | Assisting write operations to data storage cells - A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the higher voltage for a period determined by the pulse width and the high voltage level at other times; and pulse signal generation circuitry for generating said pulse signal. | 12-30-2010 |
| 20100325358 | Data storage protocols to determine items stored and items overwritten in linked data stores - A storage apparatus and method for storing a plurality of items is disclosed. The storage apparatus is configured to receive a first access request and a second access request for accessing respective items in a same clock cycle. The storage apparatus comprises: two stores each for storing a subset of the plurality of items, the first access request being routed to a first store and said second access request to a second store; miss detecting circuitry for detecting a miss where a requested item is not stored in the accessed store; item retrieving circuitry for retrieving an item whose access generated a miss from a further store; updating circuitry for selecting an item to overwrite in a respective one of the two stores in dependence upon an access history of the respective store, the updating circuitry being responsive to the miss detecting circuitry detecting the miss in an access to the first store and to at least one further condition to update both of the two stores with the item retrieved from the further store by overwriting the selected items. | 12-23-2010 |
| 20100325317 | Controlling complex non-linear data transfers - A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data. | 12-23-2010 |
| 20100312988 | Data processing apparatus and method for handling vector instructions - A data processing apparatus and method and provided for handling vector instructions. The data processing apparatus has a register data store with a plurality of registers arranged to store data elements. A vector processing unit is then used to execute a sequence of vector instructions, with the vector processing unit having a plurality of lanes of parallel processing and having access to the register data store in order to read data elements from, and write data elements to, the register data store during the execution of the sequence of vector instructions. A skip indication storage maintains a skip indicator for each of the lanes of parallel processing. The vector processing unit is responsive to a vector skip instruction to perform an update operation to set within the skip indication storage the skip indicator for a determined one or more lanes. The vector processing unit is responsive to a vector operation instruction to perform an operation in parallel on data elements input to the plurality of lanes of parallel processing, but to exclude from the performance of the operation any lane whose associated skip indicator is set. This allows the operation specified by vector instructions to be performed conditionally within each of the lanes of parallel processing without any modification to the vector instructions that are specifying those operations. | 12-09-2010 |
| 20100306504 | Controlling issue and execution of instructions having multiple outcomes - At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one operand is a value generated by a preceding instruction in the sequence. The instruction is issued for execution independently of when the at least one operand is generated by the preceding instruction. Recovery circuitry is provided to perform a recovery operation in the event that the second outcome is executed for the at least one instruction and the at least one operand has not been generated by the preceding instruction when the at least one instruction is to be executed by said instruction execution circuitry. | 12-02-2010 |
| 20100299562 | Reducing bandwidth required for trace data - A data processing apparatus is disclosed including trace logic for monitoring behaviour of a portion of said data processing apparatus and prediction logic for providing at least one prediction as to at least one step of the behavior of the portion of the data processing apparatus. The trace logic monitors behavior of the portion of the data processing apparatus, determines from the monitored behaviour whether the at least one prediction is correct, and outputs a prediction indicator indicating whether the at least one prediction is correct. | 11-25-2010 |
| 20100299548 | Blade server - A blade server | 11-25-2010 |
| 20100269004 | State Retention using a variable retention voltage - A data processing apparatus is provided with state retention circuits 14 into which state values are saved from nodes within the data processing circuitry when entering a sleep mode from an active mode. Error management circuitry | 10-21-2010 |
| 20100265259 | Generating and resolving pixel values within a graphics processing pipeline - A graphics processing apparatus | 10-21-2010 |
| 20100265254 | Graphics filled shape drawing - A filled shape is defined by edge data forming one or more boundaries thereof. Local shape data is generated from the edge data for each graphics region overlapped by the filled shape. The local shape data separately represents for each graphic region at least any edge of the filled shape within the graphics region and an overlap value indicative of a difference between a number of times the boundaries of the filled shape surround the region in a clockwise direction and the number of times the boundaries surround the region in a counter-clockwise direction. For each graphics region having local shape data, the local shape data is used to generate pixel values for pixels within that graphics region that are within the filled shape to be drawn. | 10-21-2010 |
| 20100264977 | Cascoded level shifter protection - A cascoded level shifter for receiving an input signal in a low voltage range and for generating an output signal in a high voltage range is disclosed. The cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first voltage section having a lower voltage supply than the second voltage section, and a combined voltage across the first voltage section and the second voltage section corresponding to the high voltage range, the cascoded level shifter comprising: an input node configured to receive an input signal; a cascoded device disposed in one of the first voltage section and the second voltage section, the cascoded device comprising a driver switch connected in series with a cascode switch at a midpoint node, the cascode switch switching in dependence on a reference voltage of a reference node and the input signal; and reference voltage perturbation circuitry, configured to cause a transient perturbation to the reference voltage in response to a transition of the input signal to cause the cascode switch to switch. | 10-21-2010 |
| 20100250802 | Data processing apparatus and method for performing hazard detection - A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers. | 09-30-2010 |
| 20100246278 | Accessing data within a memory formed of memory banks - A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located closer to an input and output of said memory than it is to at least one array located further from an input and output of said memory. | 09-30-2010 |
| 20100244564 | Distributing power to an integrated circuit - A power supply cell for distributing power supplied from a first voltage supply to an integrated circuit is disclosed. The power supply cell comprises: a layer comprising conductive material, the conductive material providing a conduction path for current flowing from the first voltage supply to a portion of the integrated circuit to be powered and further providing a protection path for surge current flowing between the first voltage supply and an electrostatic discharge protection device and between the electrostatic discharge protection device and the second voltage supply; the conductive material forming a first conduction path for providing a path for current flowing between the first voltage supply and the portion of the integrated circuit to be powered and for providing a portion of the protection path for surge current flowing between the first voltage supply and the electrostatic discharge protection device and a second conduction path for providing a further portion of the protection path for surge current flowing between the second voltage supply and the electrostatic discharge protection device; wherein the conductive material is arranged such that the first conduction path has a significantly lower resistance than the second conduction path. | 09-30-2010 |
| 20100242010 | Propagation delay time balancing in chained inverting devices - A circuit comprising a plurality of semiconductor inverting devices arranged in series is disclosed. Each of the semiconductor inverting devices comprise at least one NMOS transistor and at least one PMOS transistor and alternate ones of the inverting devices in the series comprise transistors having a first ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; and alternate ones of said inverting devices in the series comprise transistors having a second ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; wherein the first ratio and the second ratio are not equal and in some case, the first and second ratios are such that a sum of a delay in a rise time of a signal propagated by a first inverting device and a fall time of a signal propagated by a second inverting device is substantially equal to a delay in a fall time of a signal propagated by the first inverting device. | 09-23-2010 |
| 20100241832 | Instruction fetching following changes in program flow - This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an instruction to be processed by said data processor; a fetch unit responsive to an address input to said fetch unit to fetch an instruction stored at said address; an adder for adding a predetermined amount to said address stored in said register prior to sending said address to said fetch unit, said predetermined amount determining a position in a program flow said fetched instruction has with respect to said instruction addressed in said register; said adder being responsive to detection of a change in program flow to reset said predetermined amount to an initial value, and to increase said predetermined amount for subsequent fetches by an amount equal to the separation between addresses such that consecutive addresses are fetched up to a maximum predetermined amount. | 09-23-2010 |
| 20100241777 | Power efficient interrupt detection - Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from the processor indicating whether the processor is currently processing an interrupt; a detection circuit for detecting an interrupt request and outputting an interrupt request signal to a data processing apparatus; disabling logic for disabling at least a portion of the detection circuitry; wherein in response to detecting the processor is currently processing an interrupt; the detection circuit is configured to detect a change in value of the interrupt signal caused by assertion of the interrupt signal indicating an interrupt request and to output an interrupt request signal to output circuitry in response to detecting the interrupt signal assertion; and in response to detecting the processor is not currently processing an interrupt; the disabling logic is configured to disable at least a portion of the detection circuit; and the detection circuit with the at least a portion disabled, is configured to output the interrupt signal as the interrupt request signal to the output circuitry. | 09-23-2010 |
| 20100235697 | Error detection in precharged logic - An integrated circuit | 09-16-2010 |
| 20100232250 | Interface circuit and method for coupling between a memory device and processing circuitry - Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder circuitry that is responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry. Further, read address latch circuitry is provided for storing a read address signal issued by the processing circuitry, and read address decoder circuitry is responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry. Decoder select latch circuitry is responsive to an access type indication signal from the processing circuitry to generate the first and second enable signals in dependence on that access type indication signal. In the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry is arranged not to set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of such metastability. Such an approach prevents metastable signals being used in the arbitration of data accesses in a manner which could corrupt the state of the memory device. | 09-16-2010 |
| 20100232241 | Redundancy architecture for an integrated circuit memory - An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group | 09-16-2010 |
| 20100231268 | Low voltage differential signalling driver - A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect the first output node to a voltage supply via a current source, whilst second differential steering circuitry is switched in dependence on an inverse version of the differential input signal to connect the second output node to the voltage supply via the current source. Slew control circuitry is provided, configured to establish a current discharge path for the current source during the polarity transition of the differential input signal, thus maintaining a symmetric slew rate of the output signals at the first output node and second output node. | 09-16-2010 |
| 20100217958 | Address calculation and select-and-insert instructions within data processing systems - A data processing system | 08-26-2010 |
| 20100217937 | Data processing apparatus and method - A data processing apparatus is described which comprises a processor operable to execute a sequence of instructions and a cache memory having a plurality of cache lines operable to store data values for access by the processor when executing the sequence of instructions. A cache controller is also provided which comprises preload circuitry operable in response to a streaming preload instruction received at the processor to store data values from a main memory into one or more cache lines of the cache memory. The cache controller also comprises identification circuitry operable in response to the streaming preload instruction to identify one or more cache lines of the cache memory for preferential reuse. The cache controller also comprises cache maintenance circuitry operable to implement a cache maintenance operation during which selection of one or more cache lines for reuse is performed having regard to any preferred for reuse identification generated by the identification circuitry for cache lines of the cache memory. In this way, a single streaming preload instruction can be used to trigger both a preload of one or more cache lines of data values into the cache memory, and also to mark for preferential reuse another one or more cache lines of the cache memory. | 08-26-2010 |
| 20100200996 | Structural feature formation within an integrated circuit - An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts | 08-12-2010 |
| 20100199072 | Register file - A register file comprising a plurality of register entries for storing data values for use in the execution of data processing instructions is provided, and comprises at least one write port and at least one read port, and circuitry responsive to a write request received at said at least one write port to update one of said plurality of register entries identified by an address specified by said write request with a data value specified by said write request. The register file also comprises further circuitry responsive to a received control signal to set at least a portion of a predetermined register entry to a predetermined value. In this way, certain register file updating instructions can be executed in parallel with other instructions without the need for additional full write-ports as would be required for typical dual-issue, thereby reducing area and routing complexity and cost compared with the use of an additional write-port due to the lower gate count required by the proposed further circuitry. | 08-05-2010 |
| 20100195365 | ROM array - A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design. | 08-05-2010 |
| 20100185821 | Local cache power control within a multiprocessor system - A data processing system including a plurality of processors | 07-22-2010 |
| 20100180085 | HANDLING OF MEMORY ACCESS REQUESTS TO SHARED MEMORY IN A DATA PROCESSING APPARATUS - A data processing apparatus and method are provided for handling memory access requests to shared memory. The data processing apparatus has a plurality of processing units, at least one of which is configured to be switchable between an active power state and a dormant power state. The processing units share a memory, and at least one local storage unit is configured to store a local copy of a data item stored in the memory for access by an associated processing unit. A snoop control unit is configured to monitor memory access requests issued by the processing units and to store in the snoop control unit indications of local copies of data items stored in each local storage unit. When a memory access request for a requested data item is issued by one processing unit, if the snoop control unit has a stored indication that a local storage unit belonging to another dormant processing unit has a local copy of that data storage item and a cache coherency protocol required that the local copy of the requested data item stores in the local storage unit associated with the other processing unit be invalidated, the snoop control unit stores a marker indicating that that other local copy should later be invalidated. This approach ensures that the correct behaviour according to a cache coherency protocol for a shared memory is carried out, without losing the benefits of being able to put one of the processors of the multi-processor system into a dormant power state and avoiding the latency of repeated power state switching. | 07-15-2010 |
| 20100177575 | Apparatus and method for controlling write access to a group of storage elements - An apparatus and method for controlling write access to a group of storage elements is provided. Each storage element within the group is identified by an n-bit address, and the total number of storage elements in the group is less than 2 | 07-15-2010 |
| 20100177544 | Generating ROM bit cell arrays - A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area. Thus the system designer can reuse an existing memory architecture, yet still retain an advantageous degree of flexibility with regard to performance characteristic selection of the final ROM bit cell array. | 07-15-2010 |
| 20100177105 | METHODS OF AND APPARATUS FOR PROCESSING GRAPHICS - In a tile-based graphics processor, primitive lists (bins) are prepared for 2×2 blocks of tiles | 07-15-2010 |
| 20100162063 | Control of clock gating - Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value. | 06-24-2010 |
| 20100161901 | Correction of incorrect cache accesses - The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache. | 06-24-2010 |
| 20100149185 | Apparatus and method for tracing activities of a shader program executed on shader circuitry of a data processing apparatus - A data processing apparatus and method are provided for tracing activities of a shader program executed on shader circuitry of a data processing apparatus. The data processing apparatus comprises shader circuitry which is responsive to input data for a pixel to execute a shader program to generate a colour value for the pixel. The shader program has multiple execution paths via which the colour value may be generated, and which execution path is taken is dependent on the input data. An image buffer having a plurality of storage locations is provided, with each storage location being used to store the colour value generated by the shader circuitry for an associated pixel. In a trace mode of operation, execution of the shader program by the shader circuitry causes a trace vector to be generated containing a plurality of items of execution path information indicative of the execution path taken, the trace vector comprising a plurality of fields, each field being used to store one item of execution path information. The trace vector as output is constrained to be of the same size as the colour value, and in the trace mode of operation the trace vector is stored in one of the storage locations of the image buffer in place of the colour value generated by the shader program. This has been found to provide an efficient mechanism for obtaining execution path data useful when performing a variety of debugging activities in respect of a shader program. | 06-17-2010 |
| 20100138640 | Reset synchronisation - Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal. | 06-03-2010 |
| 20100134331 | Dynamic selection of suitable codes for variable length coding and decoding - A data compressor for compressing a data signal and a corresponding data decompressor are disclosed. The data compressor comprises: compression circuitry for compressing said data signal using a plurality of variable length compression codes; a digital code select signal generator for generating a digital code select signal from an indicator signal indicative of a preferred compression distribution, a frequency of said digital code select signal being higher than a frequency of said indicator signal and an average value of said digital code select signal corresponding to an average value of said indicator signal; said compression circuitry being responsive to said digital code select signal to select between one of said plurality of compression codes in dependence upon a current value of said digital code select signal and to compress said data signal using said selected compression code. | 06-03-2010 |
| 20100134148 | Detecting transitions in circuits during periodic detection windows - Transition detection circuitry for detecting during multiple clock cycles, transitions occurring within a detection period in each of said multiple clock cycles at a plurality of nodes within a circuit is disclosed. The transition detection circuitry comprises: a clock signal generator for generating a detection clock signal from a clock signal clocking a sampling element within said circuit, said detection clock signal defining said detection period; a plurality of transition detectors for detecting transitions at respective ones of said plurality of nodes during said detection period, each of said plurality of transition detectors being clocked by said detection clock signal; and combining circuitry for combining said detected transitions output by said plurality of transition detectors to generate a composite transition detection signal. | 06-03-2010 |
| 20100115484 | Standard cell placement - A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries. | 05-06-2010 |
| 20100110102 | Methods of and apparatus for processing computer graphics - In a graphics processing system, when a 16× sampling mask is used for sampling the image to be displayed, fragments are generated and rendered to generate rendered fragment data for each covered sampling position. However, the 16× sampling mask ( | 05-06-2010 |
| 20100106944 | Data processing apparatus and method for performing rearrangement operations - A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements. An instruction decoder is responsive to at least one but no more than N rearrangement instructions, where N is an odd plural number, to generate control signals to control the processing circuitry to perform a rearrangement process at least equivalent to: obtaining as source data elements the data elements stored in N registers of said register data store as identified by the at least one re-arrangement instruction; performing a rearrangement operation to rearrange the source data elements between a regular N-way interleaved order and a de-interleaved order in order to produce a sequence of result data elements; and outputting the sequence of result data elements for storing in the register data store. This provides a particularly efficient technique for performing N-way interleave and de-interleave operations, where N is an odd number, resulting in high performance, low energy consumption, and reduced register use when compared with known prior art techniques. | 04-29-2010 |
| 20100103747 | Memory device and method of operating such a memory device - A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column. Each sub-array access circuitry comprises propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the associated sub-array during a read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array nearer the second end of the sub-array column. The propagation circuitry receives a control signal for identifying which of its first or second inputs should be used to produce the output read data value. As a result, an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry. This provides a particularly simple technique for propagating the read data value to the global access circuitry, which has both predictable timing, and consumes low power. | 04-29-2010 |
| 20100100861 | Modifying integrated circuit layout - A layout for an integrated circuit includes standard cells | 04-22-2010 |
| 20100100704 | Integrated circuit incorporating an array of interconnected processors executing a cycle-based program - An integrated circuit | 04-22-2010 |
| 20100097388 | Graphics processing systems - A smooth curve is represented in a graphics texture by setting the texels that are inside the curve | 04-22-2010 |
| 20100097383 | Graphics processing systems - An input stroked curve | 04-22-2010 |
| 20100095263 | Post-routing power supply modification for an integrated circuit - A technique for generating the layout of an integrated circuit | 04-15-2010 |
| 20100094613 | Device emulation support within a host data processing apparatus - A data processing apparatus | 04-15-2010 |
| 20100091581 | Memory device and method of operating such a memory device - A memory device, and method of operation of such a device, are provided. The memory device comprises an array of memory cells arranged in a plurality of rows and a plurality of columns, at least one bit line being associated with each column. Column multiplexer circuitry is coupled to the plurality of columns, for inputting write data into a selected column during a write operation and for outputting an indication of read data sensed from a selected column during a read operation. The column multiplexer circuitry comprises a single pass gate transistor per bit line, and latch circuitry is then used to detect the read data from the indication of read data output by the column multiplexer circuitry during the read operation, and to store that detected read data. Such an approach provides a particularly area efficient construction for the column multiplexer circuitry whilst enabling correct evaluation of the read data held in the addressed memory cell. | 04-15-2010 |
| 20100090260 | Integrated circuit layout pattern for cross-coupled circuits | 04-15-2010 |
| 20100088659 | Compensating for non-uniform boundary conditions in standard cells - A method of design of a standard cell and a standard cell is disclosed. The method design comprising the steps of: identifying a non-uniformity in a boundary condition of said standard cell that would affect a characteristic of a neighbouring standard cell; introducing a further non-uniformity into said cell to mitigate the effect of said identified non-uniform boundary condition on said characteristic of said neighbouring standard cell. | 04-08-2010 |
| 20100088565 | Correction of single event upset error within sequential storage circuitry of an integrated circuit - Sequential storage circuitry for an integrated circuit is disclosed that comprises storage circuitry comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry; a second storage element coupled to an output of said first storage element, for storing a second indication of said input data value during a second phase of said clock signal; and error detection circuitry for detecting a single event upset error in any of said first and second storage elements comprising: two additional storage elements for storing third and fourth indications of said input data value respectively in response to a pulse signal derived from said clock signal; comparison circuitry for comparing said third and fourth indications of said input data value; and further comparison circuitry for comparing during a first phase of said clock signal said first indication and at least one of said third and fourth indications, and for comparing during a second phase of said clock signal said second indication and at least one of said third and fourth indications; and output circuitry for correcting any detected errors in said storage circuitry and for outputting an output value; said output circuitry being responsive to no match by said comparison circuitry to output said first indication during a first phase of said clock signal and said second indication during said second phase of said clock signal, and said output circuitry being responsive to a match by said comparison circuitry to output a value in dependence upon comparisons performed by said further comparison circuitry; said output circuitry being responsive to a match by said further comparison circuitry during a first phase of said clock signal to output said first indication during said first clock cycle and to a no match to output an inverted value of said first indication; and said output circuitry being responsive to a match by said further comparison circuitry during a second phase of said clock signal to output said second indication during said second phase of said clock signal and to a no match to output an inverted value of said second indication. | 04-08-2010 |
| 20100088524 | Data processing on a non-volatile mass storage device - A non-volatile mass storage device is provided comprising memory circuitry accessible to a host data processing device via a communication link. The non-volatile mass storage device comprises processing circuitry for locally accessing the memory circuitry of the file system and is capable of triggering generation of a file for storage on the memory circuitry by connection of the non-volatile mass storage device to the host data processing device. The generated file comprises information dependent upon a state of the non-volatile mass storage device. A corresponding method of operating a non-volatile mass storage device is provided and a computer program is provided for obtaining the information dependent upon the state of the non-volatile mass storage device, for locally accessing the memory circuitry and for generating the file for storage on the memory circuitry. | 04-08-2010 |
| 20100088443 | Data processing apparatus and method for arbitrating access to a shared resource - A data processing apparatus and method are provided for arbitrating access to a shared resource. The data processing apparatus includes a plurality of requester elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests asserted by one or more of the requester elements for access to the shared resource, to perform a priority determination operation to select one of the asserted requests as a winning request. Each of the asserted requests has a priority level associated therewith, and the apparatus further comprises relative priority ordering circuitry for attributing relative priorities to the plurality of requester elements. The arbitration circuitry is responsive to the asserted requests to perform the priority determination operation in order to select as the winning request the request asserted by the requester element with the highest relative priority whose asserted request has a priority level not exceeded by any other asserted request. This provides a very flexible mechanism for performing arbitration, whilst allowing priority levels to be set on a request-by-request basis, thereby facilitating use of the arbitration circuitry with various quality of service mechanisms. | 04-08-2010 |
| 20100083237 | Reducing trace overheads by modifying trace operations - A method of compiling a computer program to improve trace efficiency is disclosed. The computer program comprises a plurality of trace operations for triggering output of trace data generated by said computer program, and the method of compiling comprises the steps of: transforming said computer program into code forming an intermediate version of said computer program; analysing said transformed code; replacing at least some of said trace operations with modified trace operations; transforming said code into code suitable for execution on a data processing system; and generating translation data relating said modified trace operations to said trace operations they replaced. | 04-01-2010 |
| 20100083062 | High performance pulsed storage circuit - The application discloses state storage circuitry comprising: an operational data input for receiving input data, a diagnostic data input for receiving diagnostic data and a diagnostic select signal input; a storage element for storing a value indicative of data received from one of said operational data input and said diagnostic data input; an output for outputting said value stored in said storage element; a pulse generator for generating pulses in response to a clock signal, said pulse generator comprising a diagnostic output and a functional output and being responsive to receipt of a diagnostic enable signal at said diagnostic select signal input to output said generated pulses at said diagnostic output and being responsive to receipt of a diagnostic disable signal at said diagnostic select signal input to output said generated pulses at said functional output; an operational path switch for receiving said pulses from said functional output and being responsive to receipt of each of said pulses to provide a transmission path from said operational data input to said storage element and being responsive to receipt of no pulse to isolate said storage element from said operational data input; and a diagnostic path switch for receiving said pulses from said diagnostic output and being responsive to receipt of each of said pulses to provide a transmission path from said diagnostic data input to said storage element and being responsive to receipt of no pulse to isolate said storage element from said diagnostic data input. | 04-01-2010 |
| 20100077143 | Monitoring a data processing apparatus and summarising the monitoring data - A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store. | 03-25-2010 |
| 20100064287 | Scheduling control within a data processing system - A processor | 03-11-2010 |
| 20100064109 | Managing storage units in multi-core and multi-threaded systems - A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item. | 03-11-2010 |
| 20100060321 | Clock control of state storage circuitry - State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry | 03-11-2010 |
| 20100045682 | Apparatus and method for communicating between a central processing unit and a graphics processing unit - The present invention provides an improved technique for communicating between a central processing unit and a graphics processing unit of a data processing apparatus. Shared memory is provided which is accessible by the central processing unit and the graphics processing unit, and via which data structures are shareable between the central processing unit and the graphics processing unit. A bus is also provided via which the central processing unit, graphics processing unit and shared memory communicate. In accordance with a first mechanism of controlling the graphics processing unit, the central processing unit routes control signals via the bus. However, in addition, an interface is provided between the central processing unit and the graphics processing unit, and in accordance with an additional mechanism for controlling the graphics processing unit, the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, whilst through use of the additional mechanism it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU. | 02-25-2010 |
| 20100023666 | Interrupt control for virtual processing apparatus - A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware | 01-28-2010 |
| 20100020090 | Monitoring graphics processing - A graphics processing apparatus 6 is provided with rendering circuitry | 01-28-2010 |
| 20100007662 | Graphics processing systems - In a graphics processing system, a command list reader | 01-14-2010 |
| 20100005269 | Translation of virtual to physical addresses - Address translation circuitry for translating virtual addresses to physical addresses for a data processor in response to access requests from said data processor targeting virtual addresses is disclosed. The address translation circuitry comprises: a data store comprising a plurality of entries for storing a plurality of mappings of ranges of virtual addresses to ranges of physical addresses for said data processor and additional data associated with each of said plurality of mappings within a table; updating circuitry for updating said table in response to an access request for a virtual address that is not mapped by said table, said updating circuitry being responsive to receipt of a mapping for said virtual address to: select a plurality of entries in said table suitable for storing said received mapping; and determine one of said plurality of selected entries to be overwritten by said received mapping in dependence upon at least a portion of said additional data stored in said one of said plurality of selected entries. | 01-07-2010 |
| 20090320048 | TASK FOLLOWING BETWEEN MULTIPLE OPERATING SYSTEMS - A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters. | 12-24-2009 |
| 20090319839 | Repairing memory arrays - A memory array comprising a plurality of rows and a plurality of columns, each row comprising at least one addressable word, said memory array comprising at least one redundant row and at least one redundant column; error detection circuitry for analysing said memory array, by addressing words within said memory array and detecting errors within said addressed words; error repair circuitry for selecting for a detected error either a redundant row or a redundant column to replace one of said row or column containing said error; wherein said error repair circuitry is configured to determine for said detected error whether said error is a single error bit in said addressed word or whether it is one of a plurality of error bits within said word, and if said error is said one of said plurality of errors, said error repair circuitry is configured to preferentially select a redundant row rather than a redundant column to repair said error. | 12-24-2009 |
| 20090319718 | MEMORY CONTROLLER ADDRESS MAPPING SCHEME - A data processing system is provided with a memory controller ( | 12-24-2009 |
