| Arizona Board of Regents ,a body Corporate of the State of Arizona, Acting for and on Behalf of Ariz Patent applications |
| Patent application number | Title | Published |
|---|
| 20110189838 | Zirconium and Hafnium Boride Alloy Templates on Silicon for Nitride Integration Applications - Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation. | 08-04-2011 |
| 20100197570 | Cyclodepsipeptides with Antineoplastic Activity and Methods of Using to Inhibit Cancer and Microbial Growth - The present invention is directed to cyclodepsipeptide compounds having antineoplastic and/or antimicrobial activity, preferably Kitastatin 1. The present invention is further directed to methods of inhibiting cancer cell growth and/or microbial growth in a host inflicted therewith by administering cyclodepsipeptide compounds to the inflicted host. | 08-05-2010 |
| 20090235216 | Combinational Equivalence Checking for Threshold Logic Circuits - Aspects of a method and system for combinational equivalence checking for threshold logic circuits are provided. In this regard, one or more inputs may be received at a threshold logic gate. The threshold function of the threshold logic gate may be recursively decomposed into a first function and a second function using cofactors of the threshold function. A Boolean function representation of the threshold logic gate may be generated based on the recursive decomposition of the threshold function. The generated Boolean function representation of the threshold logic gate may be a maximally factored form representation of a minimal sum of products (SOP) for the threshold logic gate. A logical equivalence of the threshold logic gate may be verified with one or more other logic circuits based on the generated Boolean function representation of the threshold logic gate. | 09-17-2009 |
