| Applied Micro Circuits Corporation Patent applications |
| Patent application number | Title | Published |
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| 20120128049 | Confirmation of Presence of Narrowband Interference By Harmonic Analysis - One or more processing units confirm existence of narrow band interference in a signal by using an estimate f of the frequency, to check for one or more harmonics. In illustrative embodiments, the estimate f is automatically identified as a second harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at either of two frequencies namely (A) frequency f/2 and (B) frequency (M−f)/2 and whichever of these two frequencies is stronger is identified as the fundamental frequency. In several such embodiments, the estimate f is automatically identified as a third harmonic if a predetermined criterion is satisfied by the signal (in the frequency domain) at any of three frequencies namely (C) frequency f/3 and (D) frequency (M−t)/3 and (E) frequency (M+f)/3. If the predetermined criteria are not met at all five frequencies (A)-(E) then f is identified as the fundamental frequency. | 05-24-2012 |
| 20120128048 | Detection and Estimation of Narrowband Interference By Matrix Multiplication - One or more processing units are programmed to select from among M tones in a frequency domain representation of a signal, a set of tones including at least a strongest tone (relative to background noise) and a tone adjacent thereto. From among M complex numbers in the frequency domain representation of the signal, a set of complex numbers are identified and denoted as a vector Z, corresponding to the selected set of tones. Vector Z is then multiplied with each of M columns of a matrix G which is predetermined to identify a sub-resolution maxima in Z. The M products that result from the vector multiplication of Z and G are used to determine and store in memory at least one or both of: (A) a flag indicating presence or absence of narrowband interference in the signal; and (B) an estimate of a frequency of the narrowband interference. | 05-24-2012 |
| 20120126903 | Stabilized Digital Quadrature Oscillator - A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively. | 05-24-2012 |
| 20120014487 | Adaptive Narrowband Interference Prediction Circuit and Method - An input signal that includes narrowband interference is spectrally enhanced by an adaptive circuit that supplies as output signal(s), portion(s) of NBI at one or more frequencies that change adaptively. The output signal(s) are used in one or more tone predictor(s) to generate, based on prior values of the NBI portion, one or more predicted tone signals that are subtracted from a received signal containing the NBI, and the result is used in the normal manner, e.g. decoded. The adaptive circuit and the one or more tone predictor(s), form a feed-forward NBI predictor wherein the received signal is supplied as the input signal of the adaptive circuit. The result of subtraction may be supplied to a slicer that slices the result, yielding a sliced signal which is subtracted from the received signal to generate a signal can be used as the input signal, to implement a feedback NBI predictor. | 01-19-2012 |
| 20120014416 | Narrowband Interference Cancellation Method and Circuit - A narrowband interference (NBI) canceller is coupled to an A/D converter to receive an input signal and supply an NBI-canceled signal to an error correcting decoder. In the NBI canceller, a first arithmetic unit receives the input signal and a predicted-interference signal, and supplies a difference thereof as the interference-canceled signal. A slicer receives the interference-canceled signal and supplies a decision signal. A second arithmetic unit subtracts the decision signal from the input signal to generate a noise signal. A coarse frequency estimator receives the noise signal and analyzes the frequency spectrum to generate a coarse estimate of a fundamental frequency of the NBI. The coarse estimate is used by an adaptive narrowband interference predictor to generate the predicted-interference signal while adaptively tracking the narrowband interference. Use of the NBI canceller in a transceiver can eliminate link drop caused by operation of wireless devices that generate EMI in a cable. | 01-19-2012 |
| 20120013398 | Adaptive Spectral Enhancement and Harmonic Separation - A circuit and method perform adaptive spectral enhancement at a frequency ω | 01-19-2012 |
| 20100244785 | Source Power Limiting Charging System - Methods and systems for charging energy storage devices are disclosed. Often the charging circuit may have different levels of power available to charge the energy storage device depending on the state of other subsystems of the electronic system. The present invention provides a source power limiting charging system. Often the losses of the charging system and losses due to the power requirements of support systems are not well known and/or are variable. Controlling source power to the charging system maximizes the amount of power delivered to the energy storage device for a given value of these losses and avoids power contention with the other elements of the electronic system. Therefore, the power drawn from the power source by a controllable power limiting charging circuit is controlled to be less than a source power limit. | 09-30-2010 |
| 20100100569 | Method of Accelerating the Shortest Path Problem - The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance. | 04-22-2010 |
| 20090148161 | 10 GBE LAN SIGNAL MAPPING TO OTU2 SIGNAL - A high-capacity digital communications system and method of transporting 10 GbE LAN packets between user devices over an OTN network that allows the packets to be transported in a manner that is transparent to the destination device(s) on the network. The digital communications system includes an OTN network, and at least one source device and at least one destination device connected to the network via respective 10Gbase-R interfaces. The system transports 10 GbE LAN data packets over the OTN network by performing decoding on the packets to recover the preamble and variable length data contained in each packet, removing the IPG between successive packets in the stream, encapsulating the packets including the respective preambles and data, and mapping the encapsulated packets to the overhead and payload areas of ODUk frames. The packets are then transported over the OTN network from the source device to the destination device. | 06-11-2009 |
| 20090037661 | Cache mechanism for managing transient data - A system and method are provided for managing transient data in cache memory. The method accepts a segment of data and stores the segment in a cache line. In response to accepting a read-invalidate command for the cache line, the segment is both read from the cache line and the cache line made invalid. If, prior to accepting the read-invalidate command, the segment in the cache line is modified, the modified segment is not stored in a backup storage memory as a result of subsequently accepting the read-invalidate command. In one aspect, the segment is initially identified as transient data, and the read-invalidate command is used in response to identifying the segment as transient data. | 02-05-2009 |
| 20090037660 | Time-based cache control - A time-based system and method are provided for controlling the management of cache memory. The method accepts a segment of data, and assigns a cache lock-time with a time duration to the segment. If a cache line is available, the segment is stored (in cache). The method protects the segment stored in the cache line from replacement until the expiration of the lock-time. Upon the expiration of the lock-time, the cache line is automatically made available for replacement. An available cache line is located by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. In one aspect, the cache lock-time is assigned to the segment by accessing a list with a plurality of lock-times having a corresponding plurality of time duration, and selecting from the list. In another aspect, the lock-time durations are configurable by the user. | 02-05-2009 |
| 20080320485 | Logic for Synchronizing Multiple Tasks at Multiple Locations in an Instruction Stream - Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task). | 12-25-2008 |
