| ANDES TECHNOLOGY CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20110252245 | POWER SCALING MODULE AND POWER SCALING UNIT OF AN ELECTRONIC SYSTEM - A power scaling unit (PSU) of an electronic system is provided. The PSU includes a software programming interface (SPI) and a PSM. The SPI receives a transaction through software programming. The PSM receives the transaction from the SPI and controls a power driving element (PDE) of the electronic system to change an output of the PDE provided to a function unit of the electronic system according to the transaction. The output of the PDE is an operating voltage or an operating clock signal of the function unit. The transaction includes a command defining a power scaling operation to be performed by the PSM, a parameter used by the operation, and an event mask specifying an event which triggers the operation. | 10-13-2011 |
| 20110082999 | DATA PROCESSING ENGINE WITH INTEGRATED DATA ENDIANNESS CONTROL MECHANISM - A data processing engine is provided, which includes an endian register, an endian control device, and a byte swapper. The endian register stores a plurality of endian control bits. Each endian control bit indicates the default data endianness of a type of address space accessible to the data processing engine. Each endian control bit is in either a big-endian state or a little-endian state. The endian control device is coupled to the endian register. The endian control device provides an endian signal according to the endian control bits and the instruction executed by the data processing engine. The endian signal is in either the big-endian state or the little-endian state. The byte swapper is coupled to the endian control device. The byte swapper transmits data and changes the byte order of the data when the byte order of the data is inconsistent with the state of the endian signal. | 04-07-2011 |
| 20080301480 | COMPUTER SYSTEM AND METHOD FOR CONTROLLING A PROCESSOR THEREOF - A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided. | 12-04-2008 |
