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Anapass Inc.

Anapass Inc. Patent applications
Patent application numberTitlePublished
20110292020DISPLAY DEVICE AND METHOD - A display device and method are provided. The display device includes a timing controller configured to insert a clock between data and transmit the data in which the clock has been inserted, transmission lines configured to transfer the data in which the clock has been inserted, and data driver integrated circuits (ICs) configured to receive the data in which the clock has been inserted, separate the clock from the data, and drive data lines of a liquid crystal panel on the basis of the clock and the data. The timing controller includes a phase-locked loop (PLL) including an oscillator and an inductor-capacitor (LC) resonant circuit, and a reset signal generator configured to generate a reset signal causing the PLL to start coarse frequency tuning when initial power is applied or a frequency of an applied input clock changes.12-01-2011
20110292011PLL, DISPLAY USING THE SAME, AND METHOD FOR TIMING CONTROLLER TO GENERATE CLOCK USING THE SAME - Provided are a phase-locked loop (PLL) receiving an input clock and generating a clock, a display using the PLL, and a method for a timing controller to generate a clock using the PLL. The display includes a timing controller configured to generate a first clock using a PLL, insert the first clock into data, and transmit the data into which the first clock is inserted, transmission lines configured to transfer the data into which the first clock is inserted, and data-driver integrated circuits (ICs) configured to receive the data into which the first clock is inserted, separate the first clock from the data, and drive data lines of a liquid crystal panel on the basis of the first clock and the data. The PLL includes a phase detector configured to generate a DC error corresponding to a phase difference between an input clock and the first clock, a plurality of voltage-controlled oscillators (VCOs), a VCO selector configured to select a VCO having a frequency operating range, which is a range from the highest oscillation frequency of the VCO to the lowest oscillation frequency, including a frequency of the first clock from among the plurality of VCOs with reference to the DC error, and an inductor/capacitor (LC) resonant circuit connected with the selected VCO, including a plurality of fixed capacitors, and configured to perform coarse frequency tuning of the selected VCO.12-01-2011
20110140797SIGNAL GENERATOR - Provided is a signal generator. The signal generator includes an insulating substrate, a chip disposed on the insulating substrate and including an oscillator including a capacitance element determining a resonant frequency signal, and a plurality of conductive lines disposed on the same surface of the insulating substrate to be spaced apart from each other. At least one of the plurality of conductive lines is electrically connected with the oscillator and provides an inductance element determining the resonant frequency signal to the oscillator.06-16-2011
20100156882Data driving circuit, display apparatus, and data driving method - Provided are a data driving circuit, a display device, and a data driving method. The data driving circuit includes a clock generator configured to generate a clock signal from clock information included in a reception signal including the clock information, mode information and a body, a sampler configured to sample the reception signal according to the clock signal to obtain the mode information and the body that includes at least one of control information and data, a signal controller configured to determine whether or not the body corresponds to the control information with reference to the mode information, and generate a control signal corresponding to the control information according to a result of the determination, and a data driver configured to generate a data signal corresponding to the data according to the control signal.06-24-2010
20100156870Display apparatus and method - Provided are a display device and method. The display device includes a plurality of data driving integrated circuits (ICs) configured to receive reception signals, each of which includes data and load signal information indicating an application starting time point of the data, and apply parallel data signals corresponding to the data at the application starting time points according to the load signal information included in the reception signals, and a display panel configured to display an image according to the parallel data signals, wherein at least two of the data driving ICs apply parallel data signals at different application starting time points.06-24-2010