ALTERA CANADA CO.
|ALTERA CANADA CO. Patent applications|
|Patent application number||Title||Published|
|20140237013||PSEUDO-RANDOM BIT SEQUENCE GENERATOR - The present invention discloses a pseudo-random bit sequence (PRBS) generator which outputs the entire datapath, or entire pseudo-random bit sequence, over one single clock cycle. This is accomplished by removing redundancy, or any redundant exclusive-or gates from linear feedback shift registers; using logic to identify the critical path and optimal shift for the critical path; and dividing the datapath into several pipeline stages to increase the clock rate (i.e., transmission speed).||08-21-2014|
|20140189446||FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY - A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER.||07-03-2014|
|20130230055||CONTEXT-SENSITIVE OVERHEAD PROCESSOR - An overhead processor for data transmission in digital communications is disclosed. Incoming data is transmitted along a datapath. If there are two or more groups of incoming data, arriving separately, the initial group(s) of received data can be held in an elastic store until the arrival of additional group(s) of data, and upon the arrival of additional group(s) of data, all received data are combined and transmitted into flip-flop(s). The data is transmitted from said flip-flop(s) to a logic element to determine the new data context of imminent incoming data prior to any additional incoming bytes arriving along the datapath. Therefore, the number of overhead processors required for multi-byte data transmission is reduced, potentially reducing the number of required overhead processors in digital communications to 1.||09-05-2013|
|20130132794||2D PRODUCT CODE AND METHOD FOR DETECTING FALSE DECODING ERRORS - The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.||05-23-2013|
|20120287927||STRICT-SENSE MINIMAL SPANNING SWITCH NON-BLOCKING ARCHITECTURE - The present invention discloses an apparatus to implement a m=n Non-Blocking Minimal Spanning Switch, where n=the total number of data input signals and m=the total number of data output signals and m=the number of crossbar connections in each switch. Data is input to the switch as a plurality of frames, whereby each crossbar connection contains a framer which detects framing patterns in the data. Skewed data is re-aligned and buffered so that the data output by each crossbar connection is equal and identical, thus any crossbar connection may be used to ensure a connection, eliminating the possibility of data interrupts.||11-15-2012|
|20120275462||METHOD OF ACCESSING STORED INFORMATION IN MULTI-FRAMED DATA TRANSMISSIONS - The present invention discloses a method of accessing stored information in multi-framed data transmissions, comprising at least one control interface and at least one elastic store, wherein the control interface accesses the elastic store through a mailbox communications method. The control interface accesses the elastic store via the mailbox communications method, which comprises: (a) setting a address for a data location within said elastic store; (b) setting a request to read from, or write to, said data location within said elastic store; (c) issuing a “GO ______” signal to retrieve data information from said data location within said elastic store, by writing said “GO ______” signal to said microprocessor, which causes a circuit to read from said requested data location within said elastic store; (d) waiting for a possible, but not to be expected, de-assertion of a busy signal to be issued from said data location within said elastic store, and then; and then (e) reading back the value of said data information to said control interface. Where a busy signal occurs, the microprocessor must wait and issue a subsequent “GO ______” signal to retrieve the data information from the data location; where a busy signal does not occur the “GO ______” signal causes the circuit to read from the requested data location and send the data information hack to the microprocessor, where the data information is stored in a user-accessible register.||11-01-2012|
|20120147905||METHOD OF MULTIPLE LANE DISTRIBUTION (MLD) DESKEW - The present invention discloses a method of detecting and correcting skew across a plurality of transmitting lanes. Through the use of an N framer system, including a frame start signal and a frame synchronization signal, skew can be detected and corrected by writing data from a plurality of framers into offsetting bit locations of a plurality of buffers. The present invention also provides a method of transmitting data in a multiple lane distribution (MLD) transmission system.||06-14-2012|
Patent applications by ALTERA CANADA CO.