| ALTASENS, INC. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110090374 | SUB-FRAME TAPERED RESET - Systems and methods are provided that facilitate employing a plurality of independent reset buses for a column of pixels in a pixel array of a CMOS sensor imager. Utilization of the plurality of independent reset buses for the column of pixels can enable independent reset to be effectuated when employing sub-frame integration. For example, rows to be read and reset during a given readout time interval can be selected based upon one or more criteria. Further, each of the rows selected during the given readout time interval can be associated with a respective distinct reset bus. By leveraging the plurality of independent reset buses, uniformity in pixel operation can be maintained whether operating in full frame integration mode or sub-frame integration mode. Thus, noise resultant from changing between integration modes can be mitigated by using the plurality of independent reset buses. | 04-21-2011 |
| 20100231796 | NOISE REDUCTION FOR ANALOG VIDEO APPLICATIONS - Systems and methods are provided that facilitate reducing noise within sampled video information in a CMOS sensor imager. A multi-capacitor sample and hold can capture multiple samples of video information during at least partially overlapping time intervals. The multi-capacitor sample and hold can include a plurality of capacitors and a plurality of sampling switches, wherein each of the sampling switches can be coupled to a respective one of the plurality of capacitors. The plurality of sampling switches can be closed at a substantially concurrent time to begin capturing samples with the plurality of capacitors. Thereafter, the plurality of sampling switches can each be opened at respective disparate times to collect differing noise samples with each of the plurality of capacitors. A readout component can combine (e.g., average) the samples obtained by the plurality of capacitors, thereby reducing noise levels. | 09-16-2010 |
| 20100149390 | STAGGERED RESET IN CMOS DIGITAL SENSOR DEVICE - Systems and methods are provided that facilitate staggering resets of rows of pixels in a CMOS imaging iSoC sensor. Reset signals and select signals can be provided to pixels in a pixel array in a coordinated manner when employing full frame integration or sub-frame integration. Further, reset signals and select signals can be transferred to a first row of pixels, while reset signals can be transferred to a second row of pixels during a unique readout time interval when utilizing sub-frame integration. Within the unique readout time interval, reset signals can be transferred to the first row of pixels during a first time period, while reset signals can be transferred to the second row of pixels during a second time period, where the first and second time periods are non-overlapping. Accordingly, cross-talk between rows of pixels during reset can be mitigated, which leads to enhanced uniformity. | 06-17-2010 |
| 20100085438 | DIGITAL COLUMN GAIN MISMATCH CORRECTION FOR 4T CMOS IMAGING SYSTEMS-ON-CHIP - Systems and methods are provided that facilitate mitigating column gain mismatch in a CMOS imaging System-on-Chip (iSoC) sensor. Tunable voltages that mimic presence of photo-charge can be provided to test pixels in one or more rows of a pixel array. Moreover, column-specific digital gain corrections can be calibrated based upon input data received from the test pixels. During calibration, actual data can be compared to a target expected to be obtained via an analog readout architecture. The calibrated, column-specific digital gain corrections can be utilized to correct for column gain mismatch to yield output data. Further, correction values corresponding to the column-specific digital gain corrections can be retained in and retrieved from memory. The correction values, for example, can be a function of a scaling parameter that is tuned to match an available memory dynamic to a range of uncorrected gain mismatch. | 04-08-2010 |
| 20090322912 | PIXEL OR COLUMN FIXED PATTERN NOISE MITIGATION USING PARTIAL OR FULL FRAME CORRECTION WITH UNIFORM FRAME RATES - Systems and methods are provided that facilitate mitigating pixel or column fixed pattern noise in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, pixel or column fixed pattern noise can be recognized by gating a pixel array without firing a transfer signal (TX). Inhibiting the transfer signal can cause zero input to be provided to pixels in the pixel array; thus, the sampled output from the pixels under such conditions can be a function of noise. Calibration and correction can thereafter be effectuated. Moreover, uniform frame rates for outputted frames can be yielded irrespective of use of a subset of read out frames for calibration. For example, frames employed for calibration can be replaced in a sequence of outputted frames by copies of stored frames. Further, signal levels can be balanced to account for differences in light integration time, which can result from blocking and unblocking firing of transfer signals. | 12-31-2009 |
| 20090322911 | PIXEL OR COLUMN FIXED PATTERN NOISE MITIGATION USING PARTIAL OR FULL FRAME CORRECTION - Systems and methods are provided that facilitate mitigating pixel or column fixed pattern noise in a CMOS imaging System-on-Chip (iSoC) sensor. Pixel or column fixed pattern noise can be recognized by gating a pixel array without firing a transfer signal (TX). Inhibiting the transfer signal can cause zero input to be provided to pixels in the pixel array; thus, the sampled output from the pixels under such conditions can be a function of noise. Calibration and correction can thereafter be effectuated. Additionally or alternatively, pixel or column fixed pattern noise can be managed by controlling a frame rate; thus, the frame rate can be reduced under low light conditions to enable integrating incident light for longer periods of time as well as providing reference frames of pixels generated from zero input that can be utilized for calibration and correction of pixel or column fixed pattern noise associated with other frames. | 12-31-2009 |
| 20090236500 | DARK CURRENT AND LAG REDUCTION - The claimed subject matter provides systems and/or methods that facilitate reducing dark current and lag in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, a vertical output driver can output a signal upon a node connected to gates of reset transistors and/or gates of transfer transistors of pixels in the pixel array while operating in rolling shutter mode and/or global shutter mode. Further, a pre-charger can transition a voltage of the node to a first voltage level. Moreover, a booster can further adjust the voltage of the node from the first voltage level to a second voltage level. The booster can have variable drive capability that enables varying operation thereof according to at least one degree of freedom (e.g., speed of the booster proceeding to the second voltage level, frequency of yielding charge to the node, the second voltage level, or timing of the booster and the pre-charger, . . . ). | 09-24-2009 |
| 20090185044 | Image Sensor and Method with Multiple Scanning Modes - Multiple scanning modes are provided for an array of electromagnetic radiation sensors. In the preferred implementation both selectable subarrays and the overall array can be read out and reset in any desired order, including interrupting a full array scan for a subarray scan and then resuming the full array scan. | 07-23-2009 |
| 20090173974 | TWO-BY-TWO PIXEL STRUCTURE IN AN IMAGING SYSTEM-ON-CHIP - The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain). | 07-09-2009 |
| 20090141156 | REFERENCE VOLTAGE GENERATION IN IMAGING SENSORS - The claimed subject matter provides systems and/or methods that facilitate generating and/or maintaining low noise reference voltages for CMOS imaging System-on-Chip (iSoC) sensors. A primary reference voltage can be generated utilizing a low noise bandgap. Further, the primary reference voltage can be filtered via a low pass filter. The filtered, primary reference voltage can thereafter be distributed to a plurality of isolated domains. Each of the isolated domains can generate an independent set of reference voltages based upon the filtered, primary reference voltage. Moreover, subsets of these reference voltages can be employed by programmable digital to analog converters (DACs). Each of the reference voltages can be isolated from switching noise and/or clock glitches generated within each domain. Further, each DAC output can be buffered to have adequately low impedance with appropriate drive capability and requisite signal swing. | 06-04-2009 |
| 20090015301 | CONTROLLING TIMING DEPENDENCIES IN A MIXED SIGNAL SYSTEM-ON-A-CHIP (SOC) - The claimed subject matter provides systems and/or methods that facilitate controlling timing dependencies in a mixed signal circuit. Timing performance associated with a horizontal scanner and an analog to digital converter (ADC) can be monitored. Moreover, data related to the monitored timing performance can be leveraged to modify timing parameter(s) of clocks that coordinate operations of the horizontal scanner and the ADC (e.g., and/or digital component(s) included in the mixed signal circuit). For example, the clocks associated with the horizontal scanner and the ADC can be independently tuned to optimize mixed signal circuit performance. | 01-15-2009 |
| 20080316342 | ACCURATE GAIN IMPLEMENTATION IN CMOS SENSOR - The claimed subject matter provides systems and/or methods that facilitate combining analog and digital gain for utilization with CMOS sensor imagers. The analog gain can provide coarse gain steps and the digital gain can provide finer gain steps between adjacent coarse analog gain values. Further, since analog gain can suffer from low precision, dispersion, etc., on-chip calibration can be implemented to calibrate the analog and digital gain. For example, a digital amplifier can be calibrated to compensate for differences between actual and nominal analog gains associated with one or more analog amplifiers. | 12-25-2008 |
