| AGATE LOGIC, INC. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110317720 | System and Method for Parsing Frames - A system for parsing frames including a first cell extraction circuit (CEC) configured to identify a first cell from a first frame, a first parser engine operatively connected to the first CEC, where the first parser engine is configured to generate a result based on the first cell, and a first forwarding circuit operatively connected to the first parser engine and configured to forward the result, where the first CEC, the first parser engine, and the first forwarding circuit are associated with a first frame parser unit. | 12-29-2011 |
| 20110122686 | NON-VOLATILE ELECTROMECHANICAL CONFIGURATION BIT ARRAY - A configuration bit array including a hybrid electromechanical and semiconductor memory cell, and circuitry for addressing and controlling read, write, and erase accesses of the memory. | 05-26-2011 |
| 20110010406 | Programmable Logic Systems and Methods Employing Configurable Floating Point Units - A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z. | 01-13-2011 |
| 20100306429 | System and Method of Signal Processing Engines With Programmable Logic Fabric - A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits. | 12-02-2010 |
| 20100171524 | PROGRAMMABLE INTERCONNECT NETWORK FOR LOGIC ARRAY - The present invention provides an integrated circuit, comprising an array of components and programmable interconnect network for the array of components, said programmable interconnect network comprising a plurality of switch boxes being connected in a tree-based hierarchical architecture and providing selection and connection for the components responsive to configuration bits, switch boxes located at the lowest level of hierarchy are connected to the components; switch boxes in at least one level of hierarchy have different number of children from those in other levels of hierarchy. The present invention provides a hierarchical architecture with a vast variety of cell numbers, which facilitates circuit implementation. The present invention also offers greater layout flexibility. | 07-08-2010 |
| 20090237111 | Integrated Circuits with Hybrid Planer Hierarchical Architecture and Methods for Interconnecting Their Resources - The present invention relates to methods for interconnecting base, switching and interconnect resources for configurable integrated circuits that include the following steps: interconnecting base and switching resources with interconnect resources to form a hierarchical interconnect structure; physically placing the hierarchical interconnect structure in a two dimensional format; and directly interconnecting selected neighboring base and switching resources. The integrated circuits generated include base resources, interconnect resources; and switching resources that are interconnected to form a hierarchical interconnect structure, and, additional interconnect resources that directly interconnect neighboring switching or base resources. Integrated circuits of this invention and integrated circuits with resources interconnected with methods of this invention have improved performance and exhibit the advantages of both integrated circuits with hierarchical interconnect routing architecture and integrated circuits with mesh interconnect routing architecture. | 09-24-2009 |
