| ADVANTEST CORPORATION Patent applications |
| Patent application number | Title | Published |
|---|
| 20120126843 | PROBE CARD HOLDING APPARATUS AND PROBER - A probe card holding apparatus which is provided at a prober and holds a probe card includes: a clamp mechanism which clamps a clamp head which is formed at the probe card; a clamp bar which is laid over an opening of the prober in which the probe card is inserted; and an elevator device which is provided at the clamp bar and moves up and down the clamp mechanism. | 05-24-2012 |
| 20120123726 | TEST APPARATUS, TEST METHOD, AND STORAGE MEDIUM - The time required for timing training is reduced by a test apparatus having an expected value comparing section judging whether a value resulting from sampling input/output data using a strobe signal matches a pre-set expected value a pre-set number of times, and a test section adjusting a phase of a test signal to be supplied to the device under test based on the first relative phase changing from a fail state to a pass state and the second relative phase changing from the pass state to the fail state, and testing the device under test using the test signal whose phase has been adjusted, where the fail state being in which at least one of the pre-set number of judgment results indicates mismatch, and the pass state being in which all the pre-set number of judgment results indicate match. | 05-17-2012 |
| 20120120748 | TEST APPARATUS AND REPAIR ANALYSIS METHOD - A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each block; a row fail counter that, for each row address in a group including a plurality of the blocks in the memory under test, counts the fail cells indicated by the address fail data; and a column fail counter that counts the fails cells for each column address. | 05-17-2012 |
| 20120119752 | TEST APPARATUS AND CIRCUIT MODULE - Provided are a first test substrate and a second test substrate opposing each other, a first test circuit testing a device under test and being disposed on a face of the first test substrate that faces the second test substrate, a second test circuit testing the device under test and being disposed on a face of the second test substrate that faces the first test substrate, and a sealing section that is formed by sealing a space between the first test substrate and the second test substrate to enclose the first test circuit and the second test circuit in a common space that is filled with coolant. | 05-17-2012 |
| 20120117432 | TEST APPARATUS - Provided is a test apparatus that tests a memory under test, comprising a logic comparing section that compares output data output from the memory under test to expected value data, for each address of the memory under test, and outputs fail data when the output data does not match the expected value data; a fail analysis memory section that stores the fail data in association with the addresses of the memory under test; and a masking section that counts the pieces of fail data output from the logic comparing section and, when the count value exceeds a preset upper limit fail value, masks the fail data supplied from the logic comparing section to the fail analysis memory section. | 05-10-2012 |
| 20120112783 | TEST APPARATUS - A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer. | 05-10-2012 |
| 20120112781 | CONTACTOR, CONTACT STRUCTURE, PROBE CARD, AND TEST APPARATUS - A contactor and an associated contact structure, probe card and test apparatus are provided. The contact may include a base part having three or more steps in a stairway state, a support part with a rear end side provided at the base part and a front end side sticking out from the base part, and a conductive part formed on a surface of the support part and electrically contacting a contact of a device under test. | 05-10-2012 |
| 20120112777 | ELECTRONIC DEVICE PUSHING APPARATUS, ELECTRONIC DEVICE TEST APPARATUS, AND INTERFACE DEVICE - An electronic device pushing apparatus includes a pushing unit which has: a plurality of pushers which contact DUTs; and base plate on which the plurality of pushers are provided. A rigidity of the base plate is set to a rigidity which is lower relative to the rigidity of a spacing frame of the HIFIX. | 05-10-2012 |
| 20120109548 | MEASUREMENT APPARATUS, MEASUREMENT METHOD AND RECORDING MEDIUM - A measurement apparatus for measuring a characteristic (for example, EVM) of a device under measurement provided with a quadrature modulator or a quadrature demodulator is provided. The measurement apparatus includes an I-Q error measuring section that measures a frequency characteristic of an I-Q error of the device under measurement, and an error amount calculating section that calculates, based on the frequency characteristic of the I-Q error, an error amount observed when the device under measurement is supplied with a predetermined signal. | 05-03-2012 |
| 20120102353 | DATA PROCESSING APPARATUS, DATA PROCESSING SYSTEM, MEASUREMENT SYSTEM, DATA PROCESSING METHOD, MEASUREMENT METHOD, ELECTRONIC DEVICE AND RECORDING MEDIUM - Provided is a data processing system that processes input data, comprising a data generating apparatus that generates the input data and a data processing apparatus that processes the input data generated by the data generating apparatus. The data processing apparatus includes a time interpolation section that generates time interpolated data, in which level differences between pieces of data adjacent in time are a constant value, based on the input data. | 04-26-2012 |
| 20120100756 | CONNECTOR AND INTERFACE APPARATUS COMPRISING CONNECTOR - [Problems] In a connector to which unbalanced-type lines are connected, providing a connector which prevents crosstalk in the connector and an interface apparatus including the connector. | 04-26-2012 |
| 20120089371 | MEASUREMENT APPARATUS, MEASUREMENT METHOD, TEST APPARATUS AND RECORDING MEDIUM - Provided is a measurement apparatus that measures a signal under measurement having a waveform pattern that repeats with a predetermined cycle, comprising a sampling section that coherently samples the signal under measurement; and a waveform reconstructing section that reconstructs a partial waveform corresponding to a partial region of the waveform pattern, by arranging in a predetermined order pieces of sampling data corresponding to the partial region of the waveform pattern from among sampling data acquired by the sampling section. | 04-12-2012 |
| 20120088410 | CONNECTOR AND SEMICONDUCTOR TESTING DEVICE INCLUDING THE CONNECTOR - Each of the signal terminal and the ground terminal includes a first extending portion extending toward its tip end, and a second extending portion extending in a direction opposite to the first extending portion. The first extending portion is formed such that a width thereof is smaller than a width of the second extending portion. The housing includes a first housing into which the first extending portions are inserted, and a second housing into which the second extending portions are inserted. The second housing is formed separately from the first housing, and the first housing includes a wall portion located between the first extending portion of the signal terminal and the first extending portion of the ground terminal. | 04-12-2012 |
| 20120086462 | TEST APPARATUS - A power supply compensation circuit generates a compensation pulse current when a switch element is turned on. A pattern generator generates a test pattern that specifies a test signal to be output from a driver and a control signal to be output from the driver. In a calibration step, a voltage measurement unit measures the power supply voltage. A current adjustment unit adjusts the compensation pulse current to be generated in a test step after the calibration step. | 04-12-2012 |
| 20120081129 | TEST APPARATUS - Delay circuits apply a delay to set and reset pulses, respectively. An RS flip-flop is set according to the set pulse that has passed through the set delay circuit, and is reset according to the reset pulse received from the reset delay circuit. A demultiplexer receives the reset pulse that has passed through the reset delay circuit. In a first state, the demultiplexer outputs the reset pulse to the reset terminal of the RS flip-flop. In a second state, the demultiplexer outputs the reset pulse signal to the reset delay circuit again, thereby forming a closed loop. A loop control unit counts the number of times a pulse is passed through the loop. When the number of passes through the closed loop reaches a predetermined value, the demultiplexer is set to the first state. | 04-05-2012 |
| 20120074577 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE, AND SWITCHING CIRCUIT - It is an objective to provide a semiconductor device with low leak current. The semiconductor device includes a plurality of ground side electrodes and a plurality of signal side electrodes arranged on a semiconductor substrate in an alternating manner; a plurality of control electrodes arranged respectively between each pair of a ground side electrode and a signal side electrode; a ground side electrode connecting section that connects the ground side electrodes to each other; a signal side electrode connecting section that connects the signal side electrodes to each other; and ground side lead wiring and signal side lead wiring that extend respectively from a region near one end and a region near another end of an arranged electrode section, in which the ground side electrodes and the signal side electrodes are arranged in an arrangement direction, away from the arranged electrode group in the arrangement direction. | 03-29-2012 |
| 20120068548 | WIRELESS POWER SUPPLY APPARATUS - A wireless power supply apparatus transmits an electric power signal including any one of an electric field, a magnetic field, and an electromagnetic field. A bridge circuit includes multiple switches. A control unit performs switching control of the multiple switches of the bridge circuit at a first frequency configured as a transmission frequency. A transmission coil and a resonance capacitor form a resonance antenna, which is connected to the bridge circuit. The resonance frequency of the resonance antenna thus formed is a second frequency that is equal to or higher than the first frequency. A control unit is configured to be capable of adjusting the length of the dead time during which the multiple switches are all turned off at the same time. | 03-22-2012 |
| 20120062256 | TEST APPARATUS, CALIBRATION METHOD AND RECORDING MEDIUM - A test apparatus that tests a device under test, comprising first and second terminal groups including a plurality of drivers that output signals to the device under test; a first common setting section that sets a common delay amount for the signals output from one driver in the first terminal group and one driver in the second terminal group; and an inter-group adjusting section that causes reference phases of the signals output from the drivers in the first terminal group and reference phases of the signals output from the drivers in the second terminal group to draw near each other, based on a delay amount setting value set by the first common setting section when the reference phases in the first terminal group were adjusted and a delay amount setting value set by the first common setting section when the reference phases in the second terminal group were adjusted. | 03-15-2012 |
| 20120056486 | WIRELESS POWER RECEIVING APPARATUS - In a wireless power supply system, a first capacitor is arranged in series with an antenna. A second capacitor and a switch are arranged in series on a path arranged in parallel with the first capacitor. A control unit adjusts the duty ratio of the switch according to the frequency of an electric power signal. | 03-08-2012 |
| 20120043968 | VARIABLE EQUALIZER CIRCUIT - A variable equalizer circuit equalizes a signal received via a transmission line from a device which is a communication partner device. A first resistor is arranged between an output terminal and a fixed voltage terminal, and is configured to have a variable resistance. A first capacitor is arranged between an output terminal and the fixed voltage terminal, and is arranged in parallel with the first resistor, and is configured to have a variable capacitance. A second resistor is arranged between an input terminal and the output terminal. A second capacitor is arranged in parallel with the second resistor between the input terminal and the output terminal. A shunt resistor is arranged on a path including the first capacitor and the second capacitor between the input terminal and the fixed voltage terminal. | 02-23-2012 |
| 20120038382 | PROBE AND METHOD OF MANUFACTURING SAME - A probe includes a plurality of boards each of which has a plurality of magnets, a plurality of the boards include a first board and a second board laid on the first board, a plurality of the magnets include a plurality of first magnets provided with the first board and a plurality of second magnets provided with the second board and arranged so as to respectively face a plurality of the first magnets, and the first magnet and the second magnet facing each other are provided so that mutually different magnetic poles face each other. | 02-16-2012 |
| 20120036404 | CONTROL APPARATUS AND CONTROL METHOD - A control apparatus controlling testing of a memory under test that includes one or more row repair memory blocks and column repair memory blocks. The control apparatus comprises a counting section that sequentially receives test results respectively indicating pass/fail of a plurality of test blocks of the memory under test, and sequentially counts, for each first-type memory block, which is a row-oriented memory block or a column-oriented memory block, a fail memory block number among second-type memory blocks; a selecting section that selects memory blocks first-type memory blocks for which the fail memory block number exceeds a reference value, such that the number of selected memory blocks is no greater than the number of first-type repair memory blocks of the memory under test; and a test control section that masks test blocks among the memory blocks selected by the selecting section and causes further testing of the memory under test. | 02-09-2012 |
| 20120033208 | DEVICE INTERFACE APPARATUS AND TEST APPARATUS - It is an object of the present invention to test a device under test including an optical interface. Provided is a device interface apparatus on which is loaded a device under test including an optical interface. The device interface apparatus comprises a device loading section on which the device under test is loaded; an optical connector that is to be connected to the optical interface of the device under test; and an optical connector moving section that moves the optical connector toward the optical interface of the device under test loaded on the device loading section, to optically connect the optical connector and the optical interface. | 02-09-2012 |
| 20120025858 | PROBE CARD HOLDING APPARATUS - A probe card holding apparatus is provided and may be configured to hold a probe card in a test head. The probe card may include a clamp head formed at a center part of a back surface of the probe card, and a holding device provided at the test head and configured to engage with the clamp head. | 02-02-2012 |
| 20120019272 | PIN CARD AND TEST APPARATUS USING THE SAME - A DUT is connected to an I/O terminal. An AC test unit performs an AC test operation for the DUT. A DC test unit performs a DC test operation for the DUT. An optical semiconductor switch is arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the I/O terminal. The optical semiconductor switch | 01-26-2012 |
| 20120013343 | RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD, AND TEST METHOD - A receiving apparatus that acquires a reception signal using a recovered clock that is recovered from an edge of the reception signal. The receiving apparatus comprises a recovered clock generating section that generates the recovered clock; a multi-strobe generating section that generates a plurality of strobes having different phases from each other, according to a pulse of the recovered clock; a detecting section that detects an edge position of the reception signal relative to the strobes, based on a value of the reception signal at timings of each of the strobes; an adjusting section that adjusts a phase of the recovered clock according to the edge position of the reception signal; and an acquiring section that acquires the reception signal at a timing shifted by a set phase difference, which is set in advance, from the recovered clock. | 01-19-2012 |
| 20120010857 | METHOD AND APPARATUS FOR COMPLEX TIME MEASUREMENTS - Apparatus used in an automatic test equipment, comprising a plurality of system modules. Each system module comprises a Time Measurement Unit. The Time Measurement Unit comprises a Global Time Stamping Module. The Global Time Stamping Module comprises a plurality of Global Time Stamping Cores that comprising: an information receiving section for receiving at least two information, an event receiving section for receiving at a Core Input events, an event determining section for determining events of interest from said received events appearing on said Core Input, and an instructing section for instructing a Time Stamp Memory to record a current status of a Time Stamp Counter corresponding to the Clock Information, if an event of interest is determined. The Global Time Stamping Module further comprises a supplying section for supplying said plurality of Global Time Stamping Cores with a common time base. | 01-12-2012 |
| 20120007574 | SWITCHING CIRCUIT AND TEST APPARATUS - Provided is a switching circuit with high withstand voltage. The switching circuit switches whether two terminals are electrically connected to each other, according to a switching signal input thereto. The switching circuit comprises a first switching section that switches whether the two terminals are electrically connected to each other; a first control section that is electrically insulated from the first switching section and controls the first switching section according to an input current; a second switching section that switches whether the input current is input to the first control section; and a second control section that is electrically insulated from the second switching section and controls the second switching section according to the switching signal. | 01-12-2012 |
| 20110316645 | STEP ATTENUATOR APPARATUS - A step attenuator apparatus is provided, having an attenuation ratio which is switchable according to a control signal. Multiple variable attenuators are connected in series. Each variable attenuator includes a first terminal, a second terminal, multiple paths having different attenuation ratios, a first switch that can be connected to one end of a desired path selected from among the multiple paths, and a second switch that can be connected to the other end of a desired path selected from among the multiple paths. When a control signal is an instruction to set the step attenuator apparatus to a disconnected state, a control unit connects the first switch of the first-stage variable attenuator to one of the multiple paths, and connects the second switch of the first-stage variable attenuator to a different one of the multiple paths. | 12-29-2011 |
| 20110316575 | PIN ELECTRONICS CIRCUIT - An I/O pin is connected to a DUT via a transmission line. A driver generates a test signal to be supplied to the DUT. A driver-side switch and an output resistor are arranged in series between the driver and the I/O pin. A comparator is arranged such that the input terminal thereof is connected to the I/O pin, and configured to judge the level of a signal output from the DUT. A short-circuit switch is arranged between the I/O pin and the ground terminal. | 12-29-2011 |
| 20110316571 | SEMICONDUCTOR WAFER TEST APPARATUS - An apparatus includes a plurality of test heads to which probe cards are electrically connected; a wafer tray which is able to hold a semiconductor wafer; and an alignment apparatus which positions the semiconductor wafer held on the wafer tray relatively with respect to the probe card so as to make the wafer tray face the probe card. The wafer tray has a pressure reducing mechanism which pulls the wafer tray toward the probe card. The alignment apparatus is configured to be able to move along the array direction of the test heads. | 12-29-2011 |
| 20110316557 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test, comprising a signal output section that outputs a test signal for testing the device under test; a signal acquiring section that acquires a device signal output by the device under test; and an adjusting section that adjusts a signal output timing at which the signal output section outputs the test signal, according to a delay caused by a transmission path that connects the signal output section and the signal acquiring section to the device under test. The adjusting section includes a rising edge adjusting section that adjusts the signal output timing of a rising edge of the test signal based on a timing at which the signal acquiring section acquires a rising edge of a reflected signal resulting from a rising edge of an adjustment test signal output from the signal output section being reflected at an end of the transmission path on the device under test side; and a falling edge adjusting section that adjusts the signal output timing of a falling edge of the test signal based on a timing at which the signal acquiring section acquires a falling edge of a reflected signal resulting from a falling edge of the adjustment test signal output from the signal output section being reflected at the end of the transmission path on the device under test side. | 12-29-2011 |
| 20110316554 | SWITCHING APPARATUS AND TEST APPARATUS - To perform a forcible disconnection when voltage outside a reference range is applied to a terminal, provided is a switching apparatus comprising a main switch provided between a first terminal and a second terminal; a voltage detection section that detects whether voltage of the second terminal is within a reference range; and a control section that controls the main switch according to a control signal received from a control terminal and turns OFF the main switch when the voltage of the second terminal is outside the reference range. The voltage detection section includes a detection switch that disconnects the second terminal and the control section from each other when the voltage of the second terminal is within the reference range and connects the second terminal and the control section to each other when the voltage of the second terminal is outside the reference range. | 12-29-2011 |
| 20110316347 | WIRELESS POWER RECEIVING APPARATUS - A wireless power receiving apparatus receives an electric power signal including any one of an electric field, magnetic field, or electromagnetic field, transmitted from a wireless power supply apparatus. A resonance capacitor is arranged together with a reception coil to form a resonance circuit. A switch is provided in order to switch the state between a first state in which the load circuit is connected in series with the resonance circuit including the reception coil and the resonance capacitor and a second state in which the load circuit is disconnected from the resonance circuit. A control unit controls the switch so as to alternately switch the state between the first state and the second state in a time sharing manner. | 12-29-2011 |
| 20110309960 | POWER SUPPLY APPARATUS FOR TEST APPARATUS - A power supply apparatus is provided for a test apparatus configured to supply a power supply signal to a DUT. An A/D converter performs analog/digital conversion of an analog observed value that corresponds to a power supply signal so as to generate a digital observed value. A digital signal processing circuit generates, by means of digital processing, a control value adjusted such that the digital observed value received from the A/D converter matches a predetermined reference value. A D/A converter performs digital/analog conversion of the control value, and supplies the resulting value to the DUT as the power supply signal. A digital signal processing circuit is configured to be capable of changing the content of its signal processing. | 12-22-2011 |
| 20110309427 | SWITCHING DEVICE AND TESTING APPARATUS - There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drain electrode is connected to the first terminal, a source electrode that is formed in the semiconductor layer, where the source electrode is connected to the second terminal, a gate insulator that is formed on the semiconductor layer between the drain electrode and the source electrode, a floating gate that is formed on the gate insulator, where the floating gate retains a charge therein, and a tunnel gate that is formed on the floating gate, the tunnel gate supplying a tunnel current determined by a driving voltage applied thereto to charge or discharge the floating gate. | 12-22-2011 |
| 20110298630 | TEST APPARATUS AND TEST METHOD - A test apparatus comprising a plurality of test units that test a device under test; a plurality of housing sections that respectively house the test units therein; a plurality of opening/closing sections that are disposed respectively in the housing sections and that expose the test units to the outside or isolate the test units from the outside; and a control section that independently controls whether each of the opening/closing sections is allowed to be opened. The control section may allow test units that are not supplied with power to be exposed to the outside. For at least one of (i) a period during which one of the test units is performing a predetermined operation, (ii) a predetermined period before the period during which one of the test units is performing the predetermined operation, and (iii) a predetermined period after the period during which one of the test units is performing the predetermined operation, the control section may prohibit other test units from being exposed to the outside. | 12-08-2011 |
| 20110298557 | MODULATION APPARATUS, PHASE SETTING METHOD AND TEST APPARATUS - A modulation apparatus comprising a first modulating section that outputs a first modulated signal having a fixed amplitude and a set phase; a second modulating section that outputs a second modulated signal having the fixed amplitude and a set phase; an adding section that outputs the output signal as the sum of the first and second modulated signals; a calculating section that calculates two phases to be set respectively in the first and second modulating sections, based on designated amplitude and phase; an allocating section that allocates, for the first and second modulated signals, the two phases calculated by the calculating section such that the first and second modulated signals are each connected more smoothly; and a setting section that sets the phase allocated for the first modulated signal in the first modulating section and sets the phase allocated for the second modulated signal in the second modulating section. | 12-08-2011 |
| 20110298522 | OUTPUT APPARATUS AND TEST APPARATUS - Provided is an output apparatus that outputs an output signal corresponding to an input signal, comprising a plurality of drivers that each output an intermediate signal having a waveform corresponding to the input signal; an adding section that adds together the intermediate signals output from the drivers and outputs the result as the output signal; and a control section that controls a difference in delay amount, which is from when the input signal begins to change to when the intermediate signal begins to change, among the drivers according to a designated slew rate. | 12-08-2011 |
| 20110291682 | PIN CARD AND TEST APPARATUS USING THE SAME - A first switch is arranged such that a first terminal thereof is connected to an AC test unit and a second terminal thereof is connected to an I/O terminal and a DC test unit. A first switch is configured so as to be capable of switching states between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A bypass capacitor is arranged between the first terminal and the second terminal, and is configured to bypass the frequency component which is cut off by the first switch. | 12-01-2011 |
| 20110288810 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal. | 11-24-2011 |
| 20110285443 | DATA LATCH CIRCUIT - A serial-format data signal is input to a data input terminal. Each of n (n represents an integer of two or more) multiple clock input terminals is configured to receive a clock signal as an input signal. An input flip-flop latches the data signal at each timing that corresponds to the corresponding clock signal. A serial/parallel converter converts the serial-format data signal into a parallel-format intermediate data signal using the corresponding clock signal. A data selector selects one from among the n intermediate data signals according to a selection signal. | 11-24-2011 |
| 20110285435 | PLL FREQUENCY SYNTHESIZER - A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof. | 11-24-2011 |
| 20110285415 | Connector And Semiconductor Testing Device Using The Same - A ground terminal has a cylindrical main body. A signal terminal has a terminal main body that is disposed on the inside of the cylindrical main body, and a connecting plate portion that extends from an end portion of the terminal main body. Additionally, a ground terminal has at least three connecting plate portions that are disposed so as to encompass the connecting plate portion of the ground terminal, each extending from mutually different positions on an edge of the cylindrical main body. | 11-24-2011 |
| 20110285211 | WIRELESS POWER SUPPLY SYSTEM - A wireless power receiving apparatus comprises a bridge circuit and a control unit configured to control the bridge circuit. A wireless power supply apparatus transmits, to the wireless power receiving apparatus, an electric power signal and a control signal which indicates a control timing for the bridge circuit. A receiver receives the control signal transmitted from the wireless power supply apparatus. A control unit controls the bridge circuit according to the control signal. | 11-24-2011 |
| 20110285207 | SWITCHING APPARATUS - A switching apparatus that switches a connection state between two terminals, comprising a switch that switches the connection state between the two terminals according to a control voltage supplied thereto; a first power supply section that generates power supply voltage with a first voltage value; a second power supply section that generates power supply voltage with a second voltage value; and a driving section that, upon receiving switching instructions to switch the switch from a first state to a second state, uses power generated by the first power supply section to change the control voltage to be the first voltage value, and then uses power generated by the second power supply section to further change the control voltage from the first voltage value to the second voltage value, in the same direction and with a rate of change over time that is less than a rate of change over time used when changing to the first voltage value. | 11-24-2011 |
| 20110283153 | TEST APPARATUS, TEST MODULE AND TEST METHOD - A test module comprising a compression information storage section that stores a plurality of pieces of compression information that each associate a pattern sequence with a piece of pattern sequence identification information; a basic pattern storage section that stores, as a group of basic patterns, a plurality of pieces of pattern sequence data that each include the pattern sequence or the pattern sequence identification information in association with a command; an instruction information storage section that stores instruction information indicating a processing order for the basic patterns; a selecting section that selects, from among the pieces of compression information stored in the compression information storage section, compression information to be used for the basic pattern to be processed according to the processing order indicated by the instruction information; a basic pattern reading section that reads, from the basic pattern storage section, the pattern sequence data included in the basic patterns to be processed; and a pattern sequence reading section that, when the pattern sequence identification information is included in the pattern sequence data read by the basic pattern reading section, references the compression information selected by the selecting section and reads the pattern sequence corresponding to the pattern sequence identification information. | 11-17-2011 |
| 20110282617 | TEST APPARATUS, TEST METHOD AND SYSTEM - A test apparatus for testing a device under test includes a control apparatus, a plurality of test modules, and a plurality of relay apparatuses that connect the control apparatus and the plurality of test modules, each relay apparatus including (1) an upper port section connected either to the control apparatus or to a relay apparatus nearer the control apparatus; and (2) at least one lower port section connected either to a relay apparatus nearer the plurality of test modules or to a corresponding test module, where each relay apparatus receives, at one of the at least one lower port section, a packet transmitted from the corresponding test module to the control apparatus, and transmits, from the upper port section, the received packet after adding thereto port identification information of the one of the at least one lower port section. | 11-17-2011 |
| 20110282616 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls testing of the device under test; a test unit that sends and receives signals to and from the device under test; and a buffer section that buffers access requests transmitted from the control apparatus to the test unit and, prior to completion of a write request to a predetermined buffer control address from the control apparatus, issues previously buffered access requests to the test unit side. | 11-17-2011 |
| 20110282615 | TEST MODULE, TEST APPARATUS AND TEST METHOD - A test module comprising a compression information storage section that stores compression information associating pattern sequences, pattern sequence identification information, and repetition information with each other; a basic pattern storage section that stores, as a group of basic patterns, pattern sequence data that includes a pattern sequence or pattern sequence identification information in association with a command; an instruction information storage section that stores instruction information; a basic pattern reading section that reads pattern sequence data; a pattern sequence reading section that, when the pattern sequence identification information is included in the pattern sequence data, references the compression information and reads the pattern sequence corresponding to the pattern sequence identification information; and a pattern output section that repeatedly outputs, according to the number of repetitions designated by the repetition information, the pattern sequence corresponding to the pattern sequence identification information or the pattern sequence included in the pattern sequence data. | 11-17-2011 |
| 20110279812 | TEST APPARATUS, TEST METHOD, AND DEVICE INTERFACE - Provided is a test apparatus that tests a device under test including an optical coupler transmitting optical signals in a direction perpendicular to a device surface. The test apparatus comprises a substrate on which the device under test is to be loaded; an optical transmission path that transmits the optical signals: and a lens section that is provided facing the optical coupler on the substrate and that focuses the optical signals from an end of one of the optical coupler and the optical transmission path to an end of the other. | 11-17-2011 |
| 20110279811 | TEST APPARATUS, TEST METHOD, AND DEVICE INTERFACE - Provided is a test apparatus that tests a device under test including an optical coupler for transmitting optical signals in a surface direction and a first groove for holding an optical transmission path connected to the optical coupler. The test apparatus comprises a substrate on which the device under test is to be loaded; an optical transmission path to be connected to the optical coupler; and a pressing section that presses the optical transmission path from the substrate side toward the first groove. Also provided is a test method. | 11-17-2011 |
| 20110279140 | Connector And Semiconductor Testing Device Having The Same - To provide a connector wherein ground terminals can be designed easily, which not only suppresses the occurrence of impedance mismatch and crosstalk, but which does not lead to interferences between contacting portions. A ground terminal for a connector has a cylindrical main body. A plurality of contacting portions, for contacting a circuit board, are formed on the bottom edge of the cylindrical main body. The ground terminal has, as contacting portions, inner contacting portions and outer contacting portions. The inner contacting portions extend toward the inside of the cylindrical main body and in the downward direction, and the outer contacting portions extend toward the inside of the cylindrical main body and in the downward direction. | 11-17-2011 |
| 20110279109 | TEST APPARATUS AND TEST METHOD - There is provided a test apparatus for testing a device under test, including a test signal generator that generates a test signal to test the device under test, an electric-photo converter that converts the test signal into an optical test signal, an optical interface that (i) transmits the optical test signal generated by the electric-photo converter to an optical receiver of the device under test and (ii) receives and outputs an optical response signal output from the device under test, a photo-electric converter that converts the optical response signal output from the optical interface into an electrical response signal and transmits the electrical response signal, and a signal receiver that receives the response signal transmitted from the photo-electric converter and a test method. | 11-17-2011 |
| 20110277293 | CARRIER DISASSEMBLING APPARATUS AND CARRIER DISASSEMBLING METHOD - A carrier disassembling apparatus | 11-17-2011 |
| 20110276830 | TEST MODULE AND TEST METHOD - There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers. | 11-10-2011 |
| 20110274127 | PULSE LASER, OPTICAL FREQUENCY STABILIZED LASER, MEASUREMENT METHOD, AND MEASUREMENT APPARATUS - The object is to measure the carrier envelope offset frequency of a mode-locked laser. Provided is a pulse laser that measures a carrier envelope offset frequency of a mode-locked laser, pulse laser comprising a mode-locked laser that generates an optical pulse; a band expanding section that expands an oscillated frequency range of the mode-locked laser; a harmonic generating section that generates a harmonic component of the mode-locked laser; a light transmitting section that inputs light to the harmonic generating section without changing relative timings of a predetermined frequency component of the mode-locked laser output from the band expanding section and a frequency component that is at least double the predetermined frequency component; a detecting section that detects a beat signal of the harmonic component and the component passed through the harmonic generating section by the mode-locked laser; and a calculating section that calculates a carrier envelope offset frequency and a repeating frequency based on the beat signal. | 11-10-2011 |
| 20110271774 | TEST CARRIER - [Problem] A test carrier able to secure a high air-tightness is provided. | 11-10-2011 |
| 20110260745 | CONNECTOR ATTACHING/DETACHING APPARATUS AND TEST HEAD - The connector attaching/detaching apparatus includes a plurality of fitting members that causes connectors to fit with or separate from one another by sliding, guiding members that sequentially causes the plurality of fitting members to slide by moving in an arrangement direction of the fitting means, and a moving apparatus that causes the guiding members to move in the arrangement direction of the fitting members. | 10-27-2011 |
| 20110258491 | TEST APPARATUS AND TEST METHOD - A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory. | 10-20-2011 |
| 20110254945 | ELECTRONIC COMPONENT HANDLING APPARATUS, ELECTRONIC COMPONENT TESTING APPARATUS, AND ELECTRONIC COMPONENT TESTING METHOD - An electronic device handling apparatus, which handles an electronic device under test having a first main surface provided thereon with first device terminals and a second main surface provided thereon with second device terminals, includes: a contact arm having a holding-side contact arm to which a first socket is attached and a suction pad which holds the electronic device under test; an alignment apparatus which positions the first socket and the electronic device under test; and the alignment apparatus which positions, with respect to a second socket, the electronic device under test being held by the suction pad and contacting the first socket, wherein the contact arm presses the second device terminals of the electronic device under test to the second socket. | 10-20-2011 |
| 20110248737 | TEST APPARATUS AND CONNECTION DEVICE - It is an object to use an additional circuit to increase speed and functioning of an existing test apparatus at a low cost. Provided is a test apparatus that is connected to a socket board corresponding to a type of device under test and tests the device under test. The test apparatus comprises a test head including therein a test module that tests the device under test; a function board that is connected to the test module in the test head via a cable and also connected to the socket board; and an additional circuit that is loaded on the function board and connected to the test module and the device under test. | 10-13-2011 |
| 20110248734 | ELECTRONIC DEVICE TEST APPARATUS - An electronic device test apparatus which can optimize throughput and costs is provided. | 10-13-2011 |
| 20110248733 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test having a plurality of blocks operating asynchronously, based on a signal received from outside, the test apparatus comprising a plurality of domain test units corresponding respectively to the blocks; and a main body unit that controls the domain test units. The main body unit includes a reference operation clock generating section that generates a reference operation clock supplied to each domain test unit, and a test start signal generating section that generates a test start signal instructing each domain test unit to start the testing. Each domain test unit includes a test clock generating section that generates a test clock based on the reference operation clock, and generates a test signal for testing the corresponding block based on the test clock obtained by the test clock generating section, and each domain test unit starts generating the test signal on a condition that the test start signal is received. | 10-13-2011 |
| 20110242895 | MEMORY DEVICE, MANUFACTURING METHOD FOR MEMORY DEVICE AND METHOD FOR DATA WRITING - A memory device to which an electron beam is irradiated to store data therein is provided. The memory device includes a plurality of floating electrodes that store data through irradiation of the electron beam thereto, a charge amount detecting section that detects data stored in each of the floating electrodes based on a charge amount accumulated in each of the floating electrode. | 10-06-2011 |
| 20110241716 | TEST HEAD AND SEMICONDUCTOR WAFER TEST APPARATUS COMPRISING SAME - [Object] Providing a test head capable of suppressing a probe card from bending. | 10-06-2011 |
| 20110241436 | WIRELESS POWER RECEIVING APPARATUS AND WIRELESS POWER SUPPLY SYSTEM - A wireless power receiving apparatus receives an electric power signal including any one of an electric, magnetic, or electromagnetic field transmitted from a wireless power supply apparatus. A reception coil is configured to receive the electric power signal. A power storage capacitor is arranged having a first terminal set to a fixed electric potential. First and second switches are connected in series to form a closed loop including the reception coil. A connection node that connects these switches is connected to a second terminal of the power storage capacitor. Third and fourth switches are sequentially arranged in series to form a path arranged in parallel with a path comprising the first and second switches. A connection node that connects these switches is set to a fixed electric potential. | 10-06-2011 |
| 20110238337 | MEASUREMENT APPARATUS, MEASUREMENT METHOD, TEST APPARATUS AND RECORDING MEDIUM - Provided is a measurement apparatus for measuring an error of a modulation apparatus that outputs an output signal obtained as a sum of a first modulated signal output from a first modulating section and a second modulated signal output from a second modulating section. The measurement apparatus comprises a control section that causes the modulation apparatus to output an output signal having at least three different signal points; a measuring section that measures power of the output signal for each of the at least three signal points; and a calculating section that calculates at least one of an amplitude error and a phase error between the first modulated signal and the second modulated signal, based on the power of the output signal for each of the at least three signal points. | 09-29-2011 |
| 20110235800 | WIRELESS POWER SUPPLY APPARATUS - A wireless power supply apparatus generates an electric signal frequency-modulated or otherwise phase-modulated according to a transmission-side code that is determined beforehand with a wireless power reception apparatus. The electric signal thus generated is transmitted via a transmission coil so as to generate an electric power signal including any one of an electric field, a magnetic field, and an electromagnetic field. The wireless power reception apparatus receives the electric power signal using a reception coil. A control unit changes the impedance of a resonance circuit that comprises the reception coil and a resonance capacitor, according to a reception-side code that is to correspond to the transmission-side code. | 09-29-2011 |
| 20110234317 | DIFFERENTIAL DRIVER CIRCUIT - A first current source supplies a tail current It to a plurality of differential pairs. A pre-driver outputs gate signals to the gates of transistors of the corresponding differential pair. A pre-driver is configured to switch the state between the enable state and the disable state. In the enable state, the pre-driver outputs the gate signals that correspond to the differential signals. In the disable state, the pre-driver outputs the gate signals having levels which instruct the transistors of the corresponding differential pair to switch off. | 09-29-2011 |
| 20110234252 | WAFER UNIT FOR TESTING AND TEST SYSTEM - Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals. | 09-29-2011 |
| 20110231128 | TEST APPARATUS, MEASUREMENT APPARATUS, AND ELECTRONIC DEVICE - A test apparatus that judges pass/fail of a signal under measurement, comprising a frequency counter that repeatedly performs a counting step of counting the number of pulses of a reference signal whose period is known and the number of pulses of the signal under measurement in parallel within the same measurement period; an average period calculating section that calculates, for each counting step, an average period of the signal under measurement within the measurement period, based on a period of the reference signal and a ratio between the number of pulses of the signal under measurement and the number of pulses of the reference signal counted within the same measurement period; a noise calculating section that calculates spread of the average periods calculated by the average period calculating section; and a judging section that judges pass/fail of the signal under measurement based on the spread of the average periods. | 09-22-2011 |
| 20110228806 | FIBER LASER - In a fiber laser, a stable laser oscillation is easily realized. A fiber laser includes an optical amplification unit which has a first end and a second end, receives pump light, and emits spontaneous emission light from the first end, and receives the spontaneous emission light at the second end, and emits stimulated emission light from the first end, and a light passing unit (PM fibers, single mode fiber) which connects the first end and the second end with each other, and passes the spontaneous emission light and the stimulated emission light, where the light passing unit includes the PM fibers (polarization plane maintaining units) which present a small change in the polarization plane of passing light and a single mode fiber (polarization plane changing unit) which presents a large change in the polarization plane of passing light. | 09-22-2011 |
| 20110227595 | INTERFACE MEMBER, TEST SECTION UNIT AND ELECTRONIC DEVICE HANDLING APPARATUS - An interface member | 09-22-2011 |
| 20110222592 | MEASUREMENT APPARATUS, MEASUREMENT METHOD AND RECORDING MEDIUM - A measurement apparatus that measures at least one of phase error and gain error between I and Q of a quadrature modulator, comprising a supplying section that shifts a reference I signal corresponding to an I component in an IQ signal causing a tone signal and/or a reference Q signal corresponding to a Q component in the IQ signal to have a time difference therebetween, and supplies the resulting signals to the quadrature modulator; and a calculating section that calculates at least one of the phase error and the gain error, based on an I-signal frequency component corresponding to a tone signal in a modulated signal output from the quadrature modulator in response to the reference I signal being supplied thereto and a Q-signal frequency component corresponding to a tone signal in a modulated signal output from the quadrature modulator in response to the reference Q signal being supplied thereto. | 09-15-2011 |
| 20110221464 | CONTACT PROBE AND SOCKET, AND MANUFACTURING METHOD OF TUBE PLUNGER AND CONTACT PROBE - A contact probe has a tubular plunger which is not made by press working and rounding so that quality control of gold plating or the like is not necessary or not difficult. The tubular plunger is made of a metal tube with a tip that has a reduced outside diameter and notches spaced from the tip. The tip is bent inside the tube and an outer surface of the metal tube, from a bent part to a bottom side, with a small diameter defining a convex part having a larger diameter. The small diameter part of the metal tube is cut off at the end of the small diameter. | 09-15-2011 |
| 20110218752 | TEST APPARATUS AND MANUFACTURING METHOD - Provided is a test apparatus that tests a plurality of devices under test formed on a wafer under test. The test apparatus comprises a test substrate that faces the wafer under test and is electrically connected to the devices under test; a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto; a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device; and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal. | 09-08-2011 |
| 20110216791 | PHASE CONTROL DEVICE FOR LASER LIGHT PULSE - According to the present inventions, a phase control device for laser light pulse includes a laser, a reference comparator, a measurement comparator, a phase difference detector and a loop filter. The laser outputs a laser light pulse. The reference comparator compares a voltage of a reference electric signal having a predetermined frequency and a predetermined voltage with each other, thereby outputting a result thereof. The measurement comparator compares a voltage based on a light intensity of the laser light pulse and a voltage of a measurement electric signal having the predetermined frequency, with a voltage of a phase control signal, thereby outputting a result thereof. The phase difference detector detects a phase difference between the output from the reference comparator and the output from the measurement comparator. The loop filter removes a high frequency component of an output from the phase difference detector. Further, the voltage of the phase control signal is different from the predetermined voltage. Furthermore, the laser changes the phase of the laser light pulse according to the output from the loop filter. | 09-08-2011 |
| 20110208465 | TEST APPARATUS AND INFORMATION PROCESSING SYSTEM - Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a first communicating section that receives a command from the control apparatus to the relay apparatus and transmits the command to the test unit; a second communicating section that receives a return command that is transmitted back to the relay apparatus by the test unit that received the command; and an executing section that executes a process designated by the return command, in response to the second communicating section receiving the return command. | 08-25-2011 |
| 20110208448 | TEST APPARATUS AND INFORMATION PROCESSING SYSTEM - Provided is a test apparatus that tests a device under test, comprising a plurality of processing sections that each send and receive signals to and from the device under test; a control apparatus that controls the processing sections; and an interrupt control section that notifies the control apparatus concerning interrupt requests generated by the processing sections, wherein, when an interrupt request is received from a processing section while the interrupt control section is in an interrupt enable state, the interrupt control section notifies the control apparatus concerning the interrupt and transitions to an interrupt disable state; when an interrupt request is received from the processing section while the interrupt control section is in the interrupt disable state, the interrupt control section does not notify the control apparatus concerning the interrupt; and when instructions are received from the control apparatus while the interrupt control section is in the interrupt disable state, the interrupt control section transitions to the interrupt enable state. | 08-25-2011 |
| 20110202296 | TEST APPARATUS AND TEST METHOD - A data signal is transmitted synchronously with a clock signal, and contains n phases (n represents an integer of 2 or more) of data for each cycle of the clock signal. A first time to digital converter generates clock change point information which represents the change timing of the clock signal. A second time to digital converter receives a data sequence in increments of cycles of the clock signal, and generates data change point information items which represent the change timing of the data in increments of phases of the data. A calculation unit calculates difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases. A judgment unit judges a DUT based upon the difference data received from the calculation unit. | 08-18-2011 |
| 20110199134 | TEST APPARATUS, TRANSMISSION APPARATUS, RECEIVING APPARATUS, TEST METHOD, TRANSMISSION METHOD AND RECEIVING METHOD - Provided is a test apparatus that tests a device under test, comprising a phase comparing section that compares a phase of an internal clock generated in the test apparatus and a phase of a clock superimposed on a device signal output by the device under test; an adjusting section that adjusts a phase shift amount of the internal clock with respect to the device signal, based on the phase comparison result; an acquiring section that acquires the device signal according to the internal clock whose phase shift amount with respect to the device signal is adjusted; and an inhibiting section that inhibits change of the phase shift amount based on the phase comparison result, for at least a portion of a period during which the clock is not superimposed on the device signal. Also provided is a test method relating to the test apparatus. | 08-18-2011 |
| 20110199133 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus and a test method for substantially synchronizing phases of test signals for each of a plurality of clock domains. The test apparatus tests a device under test including a plurality of clock domains. The test apparatus comprises a period generator that generates a rate signal for determining a test period corresponding to an operation period of the device under test; a pattern generator that generates a test pattern; phase comparing sections that, for each clock domain, receive an operation clock signal of the clock domain acquired from a terminal of the device under test included in the clock domain, and detect a phase difference of the operation clock signal of the clock domain with respect to the rate signal; and a plurality of waveform shaping sections that are provided respectively to the clock domains, and that each shape a test signal based on the test pattern, according to the phase difference of the corresponding clock domain, to substantially synchronize the test signal with the operation clock signal of the corresponding clock domain. | 08-18-2011 |
| 20110196640 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section. | 08-11-2011 |
| 20110196638 | TEST APPARATUS, INFORMATION PROCESSING SYSTEM AND DATA TRANSFER METHOD - Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; a control apparatus that controls the test unit; and a relay apparatus that relays between the control apparatus and the test unit. The relay apparatus includes a read issuing section that receives a command from the control apparatus and issues a read command for reading read data stored at an address designated by the control apparatus in a storage apparatus of the test unit; a buffer section that buffers the read data transmitted from the test unit in response to the read command; and a data transmitting section that receives the read command from the control apparatus and sends back the read data buffered in the buffer section. | 08-11-2011 |
| 20110195274 | SUBSTRATE STRUCTURE AND MANUFACTURING METHOD - Provided is a substrate structure and a manufacturing method thereof, the substrate structure including a base substrate of single crystal; and a rhombohedral ferroelectric thin film exhibiting a spontaneous ferroelectric polarization and of a perovskite structure, the ferroelectric thin film being formed on a surface of the base substrate. The substrate structure may further include an optical waveguide formed on the ferroelectric thin film; and an electric field applying section that applies, to the optical waveguide, an electric field parallel to a surface of the base substrate. The electric field applying section generates the electric field so that the electric field direction of the electric field applied to the optical waveguide is parallel to a direction of the spontaneous ferroelectric polarization of the ferroelectric thin film. | 08-11-2011 |
| 20110193733 | OUTPUT APPARATUS AND TEST APPARATUS - Provided is an output apparatus comprising a plurality of current sources; a plurality of holding sections that correspond respectively to the current sources and that each hold a designated voltage that designates a current flowing through the corresponding current source; a setting DAC that sequentially generates the designated voltage to be held by each holding section; and a supply section that sequentially switches a supply of the designated voltage generated by the setting DAC among corresponding holding sections. | 08-11-2011 |
| 20110193138 | ELECTRONIC DEVICE AND MANUFACTURING METHOD - Provided is an electronic device that generates an output signal corresponding to an input signal, comprising a signal processing section that receives the input signal and outputs the output signal corresponding to the input signal, and a floating electrode that accumulates a charge by being irradiated by an electron beam. The signal processing section adjusts electric characteristics of the output signal according to a charge amount accumulated in the floating electrode, and includes a transistor formed on the semiconductor substrate between an input terminal that receives the input signal and an output terminal that outputs the output signal. The floating electrode is formed between a gate electrode of the transistor and the semiconductor substrate | 08-11-2011 |
| 20110191739 | CIRCUIT DESIGN METHOD, CIRCUIT DESIGN SYSTEM, AND RECORDING MEDIUM - A circuit design method for interconnecting a plurality of modules includes: a step of acquiring port information including input ports and output ports of the plurality of modules; a step of acquiring instance information indicating that, among the plurality of modules, there is a module including a plurality of instances having the same function; and a step of associating the input ports and the output ports based on the port information and the instance information to interconnect the plurality of modules. | 08-04-2011 |
| 20110187400 | SEMICONDUCTOR TEST APPARATUS AND TEST METHOD - In a semiconductor test apparatus, a first device is tested as a device under test in a state where the first device provided with a transmitter transmitting a signal and a second device provided with a receiver receiving the signal transmitted by the transmitter, are connected together. The transmitter includes an equalizer circuit that shapes the waveform of the differential signal to be transmitted. The receiver includes a latch circuit that latches data corresponding to the differential signal thus received with the use of a clock, the timing of which is variable. A control unit varies, in a matrix, a parameter of the equalizer circuit and an edge timing of the clock CLK supplied to the latch circuit. | 08-04-2011 |
| 20110184687 | TEST APPARATUS AND TEST METHOD - A test apparatus for testing a device under test includes a test module that exchanges signals with the device under test to test the device under test, a test controller that includes a processor and a memory, where the test controller controls the test module, and a network that transfers communication packets between the test module and the test controller. Here, the test controller includes a receiving section that receives an interrupt packet requesting an interrupt to the test controller, from the test module via the network, a memory writing section that writes interrupt information included in the interrupt packet into the memory, and an interrupt notifying section that notifies the processor of the interrupt to cause the processor to reference the interrupt information written into the memory. | 07-28-2011 |
| 20110181311 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus and a test method related to the test apparatus for testing a device under test, including: a plurality of test modules that exchange a signal with the device under test; a test control section that outputs a group read instruction for collectively reading data stored in two or more of the test modules; and a control interface section that reads the data from the two or more test modules according to the group read instruction, and collectively sends the read data to the test control section. | 07-28-2011 |
| 20110181310 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus for testing a device under test, including: a plurality of test modules that exchange signals with the device under test; a bus to which the plurality of test modules are connected; and a test control section that controls the plurality of test modules via the bus, where each of the plurality of test modules includes: a test section that exchanges signals with the device under test, and a module control section that controls the test section, and the module control section of each test module exchanges signals with the module control section of another test module, via the bus. | 07-28-2011 |
| 20110181309 | TEST APPARATUS AND TEST MODULE - Provided is a test apparatus for testing at least one device under test, including: a test module that includes a plurality of test sections, the plurality of test sections testing the device under test by exchanging signals with the device under test; and a plurality of test control sections that control the plurality of test sections, where the test module includes the plurality of test sections; a setting storage section that stores setting as to which of the plurality of test control sections should be associated with each of the plurality of test sections; and an interface section that is connected to the plurality of test sections, provides an access request issued from one of the plurality of test control sections and directed to the test module, to a test section associated with the test control section, and is able to set, independently for each of the plurality of test sections, which of the plurality of test control sections should control the test section. | 07-28-2011 |
| 20110181308 | TEST APPARATUS AND TESTING METHOD - A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern. | 07-28-2011 |
| 20110181298 | MEASUREMENT APPARATUS AND TEST APPARATUS - Provided is a measurement apparatus that measures a signal under measurement input thereto, comprising a plurality of signal measurement circuits that measure a level of a signal input thereto, according to a sampling clock provided thereto; a noise measuring section that measures a noise component propagated from a first signal measurement circuit to a second signal measurement circuit, among the plurality of signal measurement circuits, based on a measurement result output by the second signal measurement circuit; and a clock supplying section that, when the signal under measurement is being measured, supplies the first signal measurement circuit and the second signal measurement circuit with sampling clocks having the same period and that, when the noise component is being measured, supplies the first signal measurement circuit and the second signal measurement circuit with sampling clocks having different periods. | 07-28-2011 |
| 20110178776 | EXCESSIVE NOISE RATIO DERIVING DEVICE, NOISE FIGURE DERIVING DEVICE, METHOD, PROGRAM, AND RECORDING MEDIUM - One of the objects of the present invention is to precisely obtain the noise figure (NF) of a receiver. A noise figure deriving device includes a first NF deriving unit that derives a first noise figure, which is a noise figure when a predetermined receiver-side pin pin | 07-21-2011 |
| 20110170875 | SIGNAL OUTPUT DEVICE, AND OUTPUT APPARATUS OF SIGNAL SOURCE OF SIGNALS AND OF LASER BEAM PULSES - A frequency converter includes a first direct digital synthesizer that receives a signal having a predetermined frequency f_master as a clock signal and further an internal frequency setting signal, and outputs an internal signal having a frequency based on the internal frequency setting signal, and a second direct digital synthesizer that receives the internal signal as a clock signal, and further an output frequency setting signal, and outputs an output signal having a frequency f_slave (=f_master−Δ) based on the output frequency setting signal. A difference between the predetermined frequency f_master and the frequency of the internal signal is larger than a difference between the predetermined frequency f_master and the frequency f_slave of the output signal. | 07-14-2011 |
| 20110169674 | A-D convert apparatus and control method - Provided is an AD conversion apparatus including: a differential amplifier that generates a differential input voltage according to an analog input signal; a differential DA converter of a charge redistribution type, which outputs a differential output voltage resulting from subtracting the differential input voltage from a differential comparison voltage that is in accordance with comparison data; a comparator that compares a positive output voltage and a negative output voltage in the differential output voltage; a control section that identifies the comparison data at which the differential output voltage becomes substantially 0 based on a comparison result of the comparator, and outputs the identified comparison data as output data; and a setting section that sets at least one of a common potential of the differential amplifier and a common potential of the differential DA converter, according to a targeted value of a common potential of the comparator | 07-14-2011 |
| 20110169501 | DELAY CIRCUIT - A sub-delay element has the same configuration as that of a main delay element, and applies a delay τ that corresponds to a bias voltage to a selected clock signal output from a first selector. A phase detectorgenerates a phase detection signal that corresponds to the phase difference between a selected clock signal that has propagated through the sub-delay element and a selected clock signal that has propagated through a bypass path. A counter performs a count operation according to the phase detection signal. A D/A converter supplies a bias voltage that corresponds to the count value of the counter to the main delay element and the sub-delay element. An initialization unit instructs a DLL circuit to actually operate, and sets the reference voltage to be supplied to the D/A converter based upon the fluctuation in the count value of the counter. | 07-14-2011 |
| 20110169500 | TEST APPARATUS, ADDITIONAL CIRCUIT AND TEST BOARD - Provided is a test apparatus that tests a device under test, comprising a power supply that generates power supplied to the device under test; a transmission path that transmits the power generated by the power supply to the device under test; an intermediate capacitor that is provided between the transmission path and a ground potential; a charge/discharge current measuring section that measures charge/discharge current of the intermediate capacitor; and a load current calculating section that calculates a load current flowing through the device under test, based on the current measured by the charge/discharge current measuring section. | 07-14-2011 |
| 20110168433 | CONTACT EQUIPMENT AND CIRCUIT PACKAGE - Provided is a contact device including a contact array, in which contacts are arranged in a grid, and a plurality of differential wire pairs electrically connected to the contact array, wherein each differential wire pair is connected to a contact pair formed by two adjacent contacts in the contact array, and each contact pair is arranged such that a direction of a straight line connecting the two contacts therein is different from a direction of a straight line connecting the two contacts in a contact pair adjacent thereto. | 07-14-2011 |
| 20110166819 | DIFFERENTIAL SR FLIP-FLOP - A differential SR flip-flop | 07-07-2011 |
| 20110163771 | TEST APPARATUS AND DRIVER CIRCUIT - A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section. | 07-07-2011 |
| 20110161763 | TEST APPARATUS AND SYNCHRONIZATION METHOD - Provided is a test apparatus that tests a device under test, comprising (i) a master domain that includes a master period signal generating section, which generates a master period signal, and that operates based on the master period signal and (ii) a slave domain that includes a slave period signal generating section, which generates a slave period signal, and that operates based on the slave period signal. The master period signal generating section receives a control signal and resumes generation of the master period signal, which is being held, and the slave period signal generating section receives the control signal, initializes phase data of the slave period signal, and resumes generation of the slave period signal, which is being held. | 06-30-2011 |
| 20110161041 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising: a test module that tests the device under test by sending signals to and receiving signals from the device under test; a test controller that controls the test module; and a network that transmits communication packets between the test module and the test controller, wherein at least one of the test module and the network transmits to the test controller a usage state packet that indicates a usage state of a communication buffer that buffers the communication packets. | 06-30-2011 |
| 20110158103 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a test module section that tests the device under test; a test control section that generates control packets for controlling the test module section; and a connecting section that receives the control packets from the test control section and transmits the control packets to the test module section. The test module section includes a first test module that operates according to control packets having a first packet structure and a second test module that operates according to control packets having a second packet structure, which is obtained by adding an expansion region to a control packet having the first packet structure, the test control section transmits control packets having the second packet structure to the connecting section, and the connecting section (i) removes the expansion region from control packets having the second packet structure received from the test control section and transmits the resulting control packets to the first test module, and (ii) transmits control packets having the second packet structure received from the test control section to the second test module. | 06-30-2011 |
| 20110156733 | TEST HEAD MOVING APPARATUS AND ELECTRONIC COMPONENT TESTING APPARATUS - A test head moving apparatus includes elevating arms that move a test head up and down, a frame that horizontally moves the test head, and an interlock mechanism that prohibits the horizontal movement of the frame on the basis of a height of the test head. The interlock mechanism has a limit switch that detects that the test head is positioned at the lowermost limit and stoppers capable of pressing the pressing units onto a floor plane. | 06-30-2011 |
| 20110156729 | TEST APPARATUS AND TEST METHOD - A test apparatus and a test method with which a circuit size can be decreased are provided. A recovered clock generating circuit generates a recovered clock of which phase is approximately the same as a phase of output data output by a device under test (DUT). The recovered clock generating circuit includes a phase comparator that compares a phase of the output data of the DUT to a phase of the recovered clock to generate a phase difference signal, a binary counter of which output value is incremented or decremented based on the phase difference signal, a control signal generating section that generates a control signal based on an output value of the binary counter, and a phase shifter that shifts the phase of the reference clock based on the control signal. | 06-30-2011 |
| 20110148680 | DIGITAL-ANALOG CONVERTING APPARATUS AND TEST APPARATUS - Provided is a DA conversion apparatus comprising a capacitor array DA converter that outputs to an output line an output voltage corresponding to a digital value input thereto; and a load changing section that changes a size of a load capacitance connected to the output line. The load changing section may set gain of the DA conversion apparatus with the size of the load capacitance connected to the output line being a constant capacitance unaffected by the digital value. The load changing section may include a load capacitor connected between the output line and a standard potential; a load-side switch connected in series with the load capacitor between the output line and the standard potential; and a load capacitance control section that controls the load-side switch. | 06-23-2011 |
| 20110148499 | SIGNAL GENERATING APPARATUS AND TEST APPARATUS - Provided is a signal generating apparatus that outputs from an output end thereof an output voltage corresponding to input data supplied thereto, comprising: a DA converter that outputs a voltage corresponding to data supplied thereto; a capacitor section that is provided between the output end and a standard potential; a transmission switch that provides a connection or a disconnect between a voltage generating end of the DA converter and the output end; and a control section that causes the DA converter to charge the capacitor section with a voltage corresponding to the input data by repeatedly connecting and disconnecting the transmission switch, thereby causing the voltage of the capacitor section to gradually approach the output voltage corresponding to the input data. | 06-23-2011 |
| 20110148492 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal. | 06-23-2011 |
| 20110148454 | SEMICONDUCTOR WAFER, SEMICONDUCTOR CIRCUIT, SUBSTRATE FOR TESTING AND TEST SYSTEM - A test system includes a test substrate that transmits/receives signals to/from a semiconductor wafer, and a control apparatus to control the test substrate. The semiconductor wafer includes an external terminal coupled to an external measurement circuit, a plurality of selecting wiring lines provided to receive/transmit signals to/from the corresponding the measuring points, and a selecting section that selects one of the selecting wiring lines and that allows signal transmission between the corresponding measuring point and the external terminal through the selected selecting wiring line. The test substrate includes a measurement circuit that is coupled to the external terminal of the semiconductor wafer and that measures an electrical characteristic of a signal transmitted through the selecting wiring line selected by the selecting section, and a control section that controls which one of the measurement wiring lines is to be selected by the selecting section in the semiconductor wafer. | 06-23-2011 |
| 20110148020 | CARRIER ASSEMBLY APPARATUS - [Problem] A carrier assembly apparatus which is able to be streamlined in structure is provided. | 06-23-2011 |
| 20110145664 | TEST MODULE AND TEST METHOD - Provided is a test module that tests a device under test, comprising a pattern generating section that generates a test pattern supplied to the device under test and an expected value pattern corresponding to the test pattern, based on a pattern program; an output pattern acquiring section that acquires an output pattern output by the device under test in response to the test pattern; a comparing section that compares the output pattern output and the expected value pattern; a fail counter that counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern; and a control section that controls operation of the fail counter according to control instructions in the pattern program. | 06-16-2011 |
| 20110140938 | SIGNAL GENERATING APPARATUS AND TEST APPARATUS - Provided is a signal generating apparatus comprising a DA converter that outputs an output signal corresponding to input data supplied thereto; a sample/hold unit that is provided between the DA converter and an output end of the signal generating apparatus, and that samples an output voltage of the DA converter and holds the sampled output voltage; a comparing section that compares (i) a level of a signal output from an analog circuit that propagates the output signal to output a signal corresponding to the input data to (ii) a level of the signal output by the DA converter; and a control section that, during a holding period, (iii) provides the DA converter with comparison data instead of the input data to cause the DA converter to output a comparison voltage corresponding to the comparison data, (iv) causes the comparing section to compare a voltage of the signal output by the analog circuit to the comparison voltage, and (v) adjusts the output voltage of the DA converter based on a comparison result of the comparing section. | 06-16-2011 |
| 20110140750 | LEVEL SHIFTER USING SR-FLIP FLOP - A level shifter receives an input signal of either a first lower voltage or a first upper voltage which form a voltage pair, and level-shifts the input signal to output an output signal of either a second lower voltage or a second upper voltage. An SR flip-flop generates an output signal which is switched to the second upper voltage upon receiving a positive edge via its set terminal, and is switched to the second lower voltage upon receiving a positive edge via its reset terminal. An AND gate generates the logical AND of a feedback signal having the inverted logical level of the output signal of the SR flip-flop and the input signal, which is output to the set terminal of the SR flip-flop. A NOR gate generates the logical NOR of the feedback signal and the input signal, which is output to the reset terminal of the SR flip-flop. | 06-16-2011 |
| 20110140711 | MEASUREMENT CIRCUIT AND ELECTRONIC DEVICE - Provided is a measurement circuit that is provided in the same electronic device as a circuit under measurement, comprises a difference generating section and an integrating section, and performs a sigma-delta AD conversion on a signal under measurement output by the circuit under measurement, the measurement circuit further comprising a sampling section that is provided between an output end of the difference generating section and an input end of the integrating section, detects a level of a signal input thereto at predetermined sampling intervals, and outputs a sampled signal corresponding to the detected signal level. This measurement circuit is used to easily perform a sigma-delta AD conversion on a high-frequency signal under measurement. | 06-16-2011 |
| 20110137606 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section. | 06-09-2011 |
| 20110137605 | TEST MODULE, TEST APPARATUS, AND TEST METHOD - Provided is a test module comprising a specified pattern detecting section that detects a specified pattern output in response to a specified test pattern from a device under test outputting output patterns in response to test patterns; a timing detecting section that detects a timing at which the specified pattern is detected; and a phase adjusting section that adjusts phases of the output patterns to match phases of expected value patterns, which are expected from the device under test as responses to the test patterns, based on the timing detected by the timing detecting section. | 06-09-2011 |
| 20110133973 | TIME MEASUREMENT CIRCUIT - A time measurement circuit measures the time difference between edges of a first signal and a second signal. A sampling circuit acquires the logical level of the first signal at a timing of the edge of the second signal. When a sampling circuit enters a metastable state, an output signal thereof transits with a long time scale. A transition time measurement circuit measures a transition time (settling time) of the output signal of the sampling circuit in the metastable state. | 06-09-2011 |
| 20110133768 | TEST WAFER UNIT AND TEST SYSTEM - Provided is a test wafer unit that tests a plurality of devices under test formed on a wafer under test, the test wafer unit comprising a plurality of test circuits that are formed on the same semiconductor wafer, where a plurality of types of the test circuits having different functions are provided for each device under test; and a selecting section that selects which type of test circuit is electrically connected to each pad of a device under test. Therefore, the test wafer unit can select the test circuit corresponding to testing content to be performed and connect this test circuit to the device under test to perform testing on a variety of devices under test or to perform a variety of tests on a device under test. | 06-09-2011 |
| 20110133751 | SIGNAL GENERATING APPARATUS AND TEST APPARATUS - Provided is a signal generating apparatus comprising a DA converter that outputs an output signal corresponding to input data supplied thereto; a sample/hold unit that is provided between the DA converter and an output end of the signal generating apparatus, and that samples an output voltage of the DA converter and holds the sampled output voltage; a comparing section that compares (i) a level of a signal output from an analog circuit that propagates the output signal to output a signal corresponding to the input data to (ii) a level of the signal output by the DA converter; and a control section that, during a holding period, (iii) provides the DA converter with comparison data instead of the input data to cause the DA converter to output a comparison voltage corresponding to the comparison data, (iv) causes the comparing section to compare a voltage of the signal output by the analog circuit to the comparison voltage, and (v) adjusts the output voltage of the DA converter according to the input data based on a comparison result of the comparing section. | 06-09-2011 |
| 20110133748 | SIGNAL OUTPUT CIRCUIT, TIMING GENERATE CIRCUIT, TEST APPARATUS AND RECEIVER CIRCUIT - Provided is a signal output circuit that outputs a signal, comprising an output circuit that changes a characteristic of a signal output therefrom according to a change in power supply voltage supplied thereto and a control signal supplied thereto; and a control section that changes the control signal to compensate for a change in the characteristic due to a change in the power supply voltage. | 06-09-2011 |
| 20110128052 | CLOCK HAND-OFF CIRCUIT - A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween. | 06-02-2011 |
| 20110128044 | TEST APPARATUS, TEST METHOD, AND PHASE SHIFTER - A test apparatus includes a recovered clock generating circuit generating a recovered clock having substantially the same phase as an output of a device under test (DUT), a data acquiring section acquiring a value of the output data at a timing indicated by a strobe signal based on the recovered clock, a comparator comparing the value acquired by the data acquiring section to a prescribed expected value, and a judging section judging pass/fail of the DUT based on a comparison result. The recovered clock generating circuit includes a phase comparator comparing the phase of the output data of the DUT to the phase of the recovered clock, a control signal generating section generating a control signal such that the phase of the recovered clock is synchronized with the phase of the output data, and a phase shifter continuously shifting the phase of the reference clock based on the control signal. | 06-02-2011 |
| 20110128032 | WAFER FOR TESTING, TEST SYSTEM, AND SEMICONDUCTOR WAFER - Provided is a test wafer that tests a plurality of semiconductor chips that are formed on a semiconductor wafer and that each include an operation circuit and an internal memory. The test wafer comprises a plurality of test circuits that correspond to the plurality of semiconductor chips, supply the operation circuits of the corresponding semiconductor chips with measurement signals, and measure electrical characteristics of signals output by the operation circuits in response to the measurement signals; and a plurality of write circuits that correspond to the plurality of semiconductor chips and each write, to the internal memory of the corresponding semiconductor chip, data corresponding to a measurement result of the corresponding test circuit. | 06-02-2011 |
| 20110128031 | TEST SYSTEM AND SUBSTRATE UNIT FOR TESTING - A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon. | 06-02-2011 |
| 20110128027 | WAFER UNIT FOR TESTING AND TEST SYSTEM - Provided is a test wafer unit that tests a plurality of circuits under test formed on a wafer under test. The test wafer unit comprises a test wafer that is formed of a semiconductor material and exchanges signals with each of the circuits under test, and a plurality of loop-back sections that are provided in the test wafer to correspond to the plurality of circuits under test and that each supply the corresponding circuit under test with a loop-back signal corresponding to a signal received from the corresponding circuit under test. | 06-02-2011 |
| 20110128024 | TEST APPARATUS, TEST METHOD AND COMPUTER READABLE MEDIUM - A test apparatus comprising a position information acquiring section that acquires position information concerning first terminals on a surface of a device under test and position information concerning second terminals on a surface of a probe card used for testing the device under test; a control section that calculates a displacement amount between each first terminal and a corresponding second terminal, based on the position information concerning the first terminals and the position information concerning the second terminals, and determines relative positions of the device under test and the probe card such that a maximum value from among the calculated displacement amounts is less than a predetermined value; and an aligning section that adjusts the relative positions of the device under test and the probe card, based on a signal from the control section, and electrically connects the device under test to the probe card. | 06-02-2011 |
| 20110128020 | TEST APPARATUS AND POWER SUPPLY APPARATUS - Provided is a test apparatus that tests a device under test, comprising a plurality of capacitors that are each charged to a predetermined voltage; a switching section that switches which of the capacitors charged to a predetermined voltage supplies power to the device under test; and a judging section that judges acceptability of the device under test based on an operational result of the device under test. Also provided is a test apparatus that selects one of a plurality of capacitors and a corresponding one of a plurality of power supply units, according to content of a test performed after a test that uses another of the capacitors to supply power to the device under test. | 06-02-2011 |
| 20110126931 | VALVE DEVICE AND TEMPERATURE ADJUSTING SYSTEM FOR ELECTRONIC DEVICE - A valve device for adjusting the flow volumes of a cooling medium and a heating medium for adjusting the temperature of an electronic device includes: flow paths through which a cooling medium and heating medium are able to flow; and a merging section into which these flow path merge. The merging section has a valve shaft internally and a first channel is formed in the valve shaft. The valve shaft makes the first channel face at least two of the flow paths so as to make at least two flow paths communicate with each other. | 06-02-2011 |
| 20110125308 | APPARATUS FOR MANUFACTURING SUBSTRATE FOR TESTING, METHOD FOR MANUFACTURING SUBSTRATE FOR TESTING AND RECORDING MEDIUM - A test substrate manufacturing apparatus comprising a test circuit database that stores circuit data of a plurality of types of test circuits in association with a plurality of types of testing content; a definition information storing section that stores definition information defining arrangements of device pads of devices under test and testing content to be performed for each of the device pads; and a lithography data generating section that generates lithography data for the test substrate by (i) selecting, from the test circuit database, circuit data of each test circuit to be connected to a device pad based on the testing content defined by the definition information stored in the definition information storing section and (ii) determining positions on the test substrate where the test circuits corresponding to the selected circuit data are formed using lithography, based on the arrangements of the device pads as defined by the definition information. | 05-26-2011 |
| 20110121904 | COMPARISON JUDGMENT CIRCUIT - A comparison judgment circuit judges the level of a signal received, via a transmission line, from a second device which is a communication partner. An input/output terminal is connected to the transmission line. An attenuator circuit attenuates the voltage at the input/output terminal so as to generate an attenuated voltage. A level comparator compares the attenuated voltage with a predetermined threshold voltage, and generates a level judgment signal that corresponds to the comparison result. A protection circuit monitors the voltage at the input/output terminal or the attenuated voltage. When the voltage to be monitored deviates from a predetermined voltage range, the protection circuit forcibly cuts off or changes the voltage input to the level comparator. | 05-26-2011 |
| 20110121848 | PROBE WAFER, PROBE DEVICE, AND TESTING SYSTEM - There is provided a testing system for testing a plurality of semiconductor chips formed on a single semiconductor wafer. The testing system includes a wafer substrate, a plurality of wafer connector terminals that are provided on the wafer substrate in such a manner that one or more wafer connector terminals correspond to each of the semiconductor chips, where each wafer connector terminal is to be electrically connected to an input/output terminal of a corresponding semiconductor chip, a plurality of circuit units that are provided on the wafer substrate in such a manner that one or more circuit units corresponds to each of the semiconductor chips, where each circuit unit generates a test signal to be used for testing a corresponding semiconductor chip and supplies the test signal to the corresponding semiconductor chip to test the corresponding semiconductor chip, and a controller that generates a control signal used to control the plurality of circuit units. | 05-26-2011 |
| 20110121847 | PROBE, ELECTRONIC DEVICE TEST APPARATUS, AND METHOD OF PRODUCING THE SAME - A probe comprises: a membrane having a bump which contacts an input/output terminal of an IC device built into a semiconductor wafer under test; a pitch conversion board having a bottom surface on which a first terminal is provided and a top surface on which a second terminal connected to the first terminal is provided; a circuit board which is electrically connected to a test head and has a third terminal; a first anisotropic conductive rubber member having a first conductor part which electrically connects the bump of the membrane and the first terminal of the pitch conversion board; and a second anisotropic conductive rubber member having a second conductor part which electrically connects the second terminal of the pitch conversion board and the third terminal of the circuit board, and the second conductor parts are provided on the whole of the second anisotropic conductive rubber member. | 05-26-2011 |
| 20110121815 | MEASURING APPARATUS, PARALLEL MEASURING APPARATUS, TESTING APPARATUS AND ELECTRONIC DEVICE - Provided is a measurement apparatus that measures a signal under measurement, comprising a first oscillation circuit that receives one pulse of the signal under measurement and begins oscillating according to the pulse of the signal under measurement to output a first oscillated signal; a second oscillation circuit that receives one pulse of a reference signal and begins oscillating according to the pulse of the reference signal to output a second oscillated signal having a period that is different from a period of the first oscillated signal; and a first sampling section that samples the first oscillated signal according to a pulse of the second oscillated signal. The first oscillation circuit and the second oscillation circuit each include a control section that selects one pulse; a delay section that delays the pulse; and a loop line that feeds the pulse back to an input terminal of the delay section | 05-26-2011 |
| 20110121814 | TEST APPARATUS - A first timing comparator TCP | 05-26-2011 |
| 20110119539 | PATTERN GENERATOR AND MEMORY TESTING DEVICE USING THE SAME - An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that includes a bank address to be applied to the memory under test, and which is generated according to a pattern program, is used as a save address to be used to write the row address to the row address memory, and as a load address to be used to read out the row address from the row address memory. | 05-19-2011 |
| 20110119537 | PATTERN GENERATOR - An address signal generating circuit generates an address signal which designates the address in memory to be accessed. An inversion inhibition signal generating unit generates multiple patterns of inversion inhibition signals each having the same bit width as that of the address signal, and each having a function of preventing particular bits of the address signal from being inverted. A selector selects one of the multiple patterns of inversion inhibition signals generated by the inversion inhibition signal generating unit, and outputs the inversion inhibition signal thus selected. When an inversion control signal is asserted, an address signal inverting circuit inverts only the bits of the address signal which are not prevented from being inverted according to the inversion inhibition signal selected by the selector, and outputs the resulting address signal. | 05-19-2011 |
| 20110119010 | METHOD OF DETERMINING CHARACTERISTICS OF DEVICE UNDER TEST, PROGRAM, AND STORAGE MEDIUM STORING PROGRAM - A method of determining characteristics of a DUT, in which test results indicating at least a pass/fail state of the DUT are used on a matrix in which plots defined by a combination of a first test parameter and a second test parameter for testing the DUT are arranged two-dimensionally, includes the steps of: (a) specifying at least one plot pair constituted by adjacent plots but indicating different test results on the matrix; (b) specifying test results of a plot pair constituted by adjacent plots and located next to both plots of the plot pair specified in the step (a); (c) selecting a plot pair constituted by adjacent plots but indicating different test results in a region including the plot pair specified in the step (a) and the step (b); and (d) specifying test results of a plot pair constituted by adjacent plots and located next to both plots of the plot pair selected in the step (c). | 05-19-2011 |
| 20110116333 | MEMORY TEST APPARATUS AND TESTING METHOD - A refresh control circuit receives an interrupt signal, which is a request to refresh DRAM (Dynamic Random Access Memory) and which is asserted at predetermined timings. The refresh control circuit counts the number of times the interrupt signal is asserted, and asserts an interrupt subroutine start signal, which is an instruction to refresh the DRAM, in an idle state in which the DRAM is accessible from an external circuit, for a number of times that is equal to the number of times thus counted. When the interrupt subroutine start signal is asserted, a refresh circuit executes a predetermined interrupt subroutine, and supplies a refresh pattern to the DRAM. | 05-19-2011 |
| 20110115519 | TEST SYSTEM AND WRITE WAFER - A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel. | 05-19-2011 |
| 20110115468 | RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD, AND TEST METHOD - Provided is a receiving method and a receiving apparatus comprising a multi-strobe generating section that generates a multi-strobe including a plurality of strobes having different phases with respect to a reception signal; an acquiring section that acquires the reception signal using each of the strobes; a detecting section that detects a change position at which a value of the reception signal changes, based on the acquisition result of the acquiring section; and a selecting section that selects, as a reception data value, the value of the reception signal acquired using a strobe at a position shifted by a predetermined phase from the change position. The receiving apparatus may further comprise a reference clock generating section that generates a reference clock having a preset period, and the multi-strobe generating section generates the multi-strobe for each pulse of the reference clock. | 05-19-2011 |
| 20110109377 | SEMICONDUCTOR INTEGRATED CIRCUIT - A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state. | 05-12-2011 |
| 20110109337 | PROBE WAFER, PROBE DEVICE, AND TESTING SYSTEM - A probe wafer electrically connected to a semiconductor wafer on which a plurality of semiconductor chips are formed includes: a wafer substrate for pitch conversion including a wafer connection surface and an apparatus connection surface opposing the wafer connection surface; a plurality of wafer connection terminals formed on the wafer connection surface of the wafer substrate for pitch conversion, at least one wafer connection terminal provided for each of the semiconductor chips and electrically connected to an input/output terminal of the corresponding semiconductor chip; a plurality of apparatus connection terminals formed on the apparatus connection surface of the wafer substrate in one-to-one relation with the plurality of wafer connection terminals at an interval different from an interval of the wafer connection terminals, to be electrically connected to an external apparatus; and a plurality of transfer paths, each electrically connecting a corresponding wafer connection terminal to an apparatus connection terminal. | 05-12-2011 |
| 20110109321 | TEST APPARATUS AND ELECTRICAL DEVICE - Provided is a test apparatus that tests a device under test, comprising a digital signal generator that outputs in parallel one or more n-bit digital test signals, where n is an integer greater than or equal to 1; a plurality of driver circuits that are connected respectively to a plurality of digital terminals of the device under test; and an analog signal generator that generates an analog test signal by converting, into an analog signal, an n×m-bit digital multi-bit signal based on the one or more digital test signals output by the digital signal generator to the plurality of driver circuits, where m is an integer greater than or equal to 2. | 05-12-2011 |
| 20110108740 | FIXING INSTRUMENT - Fixtures according to the present invention include fixing surfaces in the same shape as end surfaces of a device under test which is to be measured while an electromagnetic wave to be measured at a frequency equal to more than 0.01 [THz] and equal to or less than 100 [THz] is irradiated on the device under test. The end surfaces are fixed to the fixing surfaces. When a refractive index of the fixtures is n0, and a refractive index of the device under test is n1, a relationship n1−0.1≦n0≦n1+0.1 holds. The fixtures do not cover a side surface of the device under test. The fixtures are rotated about a straight line orthogonal to the fixing surfaces as a rotational axis. | 05-12-2011 |
| 20110102038 | DUTY RATIO CONTROL APPARATUS AND DUTY RATIO CONTROL METHOD - There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method. | 05-05-2011 |
| 20110099443 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a plurality of test circuits that each perform a predetermined test function; a plurality of I/O circuits that are provided between the test circuits and the device under test, where at least one of the circuits has electrical characteristics that differ from the electrical characteristics of the other circuits; and an I/O switching section that switches which of the I/O circuits is used to electrically connect at least one of the test circuits to the device under test. | 04-28-2011 |
| 20110097649 | CARRIER AND ADHESION AMOUNT MEASURING APPARATUS, AND MEASURING METHOD, PROGRAM, AND RECORDING MEDIUM OF THE SAME - The present invention measures a quantity of attachment (such as density) of a material (such as catalyst and promoter) attached to a carrier. A carrier | 04-28-2011 |
| 20110095777 | TEST WAFER UNIT AND TEST SYSTEM - A wafer unit for testing is electrically connected to a plurality of chips to be tested formed on a wafer to be tested, the wafer unit for testing including: a connecting wafer provided to face the wafer to be tested, and to be electrically connected to each of the plurality of chips to be tested; and a temperature distribution adjusting section provided on the connecting wafer, and to adjust a temperature distribution of the wafer to be tested. | 04-28-2011 |
| 20110094300 | COLLECTION MEDIUM AND COLLECTION AMOUNT MEASURING APPARATUS, AND MEASURING METHOD, PROGRAM, AND RECORDING MEDIUM OF THE SAME - The present invention precisely measures characteristic values (such as the absorption coefficient) of an electromagnetic wave when a density of a PM in a DPF which collects the PM in an exhaust gas. The DPF receives the exhaust gas, and collects the PM in the exhaust gas. The DPF includes first hole portions which are open at a first end on a side for receiving the exhaust gas, and are closed at a second end on a side opposite to the first end, second hole portions which are closed at the first end and are open at the second end, and third hole portions which are closed at the first end. The first hole portion and the second hole portion are adjacent to each other. The third hole portions are adjacent to each other. The PM in the exhaust gas passing through partition walls which partition the first hole portion and the second hole portion adjacent to each other is collected by the partition walls. | 04-28-2011 |
| 20110090431 | LIGHT RECEIVING DEVICE, LIGHT RECEIVING DEVICE MANUFACTURING METHOD, AND LIGHT RECEIVING METHOD - There is provided a light receiving device including a polarization dispersing section that disperses a polarization direction of incoming light into a plurality of polarization directions, a light collecting section that has a metal pattern shaped like concentric circles on a surface thereof, where the light collecting section collects light that has passed through the polarization dispersing section, and a light receiving section that receives the light collected by the light collecting section. Also provided are a light receiving device manufacturing method and a light receiving method. The light collecting section may have a surface plasmon antenna that has the metal pattern shaped like the concentric circles on a surface thereof, and the light receiving section may receive the light collected toward a center of the concentric circles of the metal pattern of the light collecting section, through a hole at the center of the concentric circles, on a rear side of the light collecting section. | 04-21-2011 |
| 20110089983 | LOOP TYPE CLOCK ADJUSTMENT CIRCUIT AND TEST DEVICE - A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter. | 04-21-2011 |
| 20110089550 | PRODUCTION DEVICE, PRODUCTION METHOD, TEST APPARATUS AND INTEGRATED CIRCUIT PACKAGE - Provided is a manufacturing apparatus that manufactures an integrated circuit package by packaging an integrated circuit chip, the manufacturing apparatus comprising a flattening section that flattens the integrated circuit chip; a holding section that holds a base substrate; a transporting section that transports the flattened integrated circuit chip to load the integrated circuit chip on the base substrate held by the holding section; and a packaging section that packages the integrated circuit chip and the base substrate as the integrated circuit package. | 04-21-2011 |
| 20110087934 | TEST APPARATUS AND TEST METHOD - A test apparatus testing a device under test includes a main pattern generating section that generates a main pattern, a plurality of sub-pattern generating sections each of which generates a sub-pattern corresponding to a different one of segment cycles based on a main pattern, the segment cycles formed by dividing a test cycle period, a test signal supplying section that supplies, to the device under test, a multiplexed test pattern formed by switching sub-patterns generated by the plurality of sub-pattern generating sections at each of the segment cycles, and a plurality of delay selecting sections each of which selects one of a main pattern that is from the main pattern generating section and a delayed main pattern that is formed by delaying the main pattern from the main pattern generating section by a test cycle, to supply the selected one to the corresponding sub-pattern generating section. | 04-14-2011 |
| 20110087931 | TEST APPARATUS AND TRANSMISSION DEVICE - Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; and a control apparatus that controls the test unit. The control apparatus includes a first buffer and a second buffer that buffer access requests to the test unit; a data output section that buffers, in the first buffer, access requests to be sent from the control apparatus to the test unit and, when an error occurs, buffers the access requests in the second buffer instead of the first buffer; and a transmitting section that sequentially transmits the access requests in the first buffer to the test unit and, when an error occurs, sequentially transmits the access requests in the second buffer to the test unit. | 04-14-2011 |
| 20110085608 | COMMUNICATION SYSTEM, TEST APPARATUS, COMMUNICATION APPARATUS, COMMUNICATION METHOD AND TEST METHOD - A communication system comprising a first communication apparatus and a second communication apparatus. The first communication apparatus includes a communicating section that communicates with the second communication apparatus via a first data signal line; an alive signal receiving section that receives, via a first alive signal line, an alive signal indicating whether the second communication apparatus is in an alive state in which it is capable of communicating with the first communication apparatus; and a reset signal transmitting section that, when the second communication apparatus is not in the alive state, transmits a reset signal to the second communication apparatus. The second communication apparatus includes a communicating section that communicates with the first communication apparatus via the first data signal line; an alive signal transmitting section that transmits the alive signal via the first alive signal line; and a reset signal receiving section that, upon receiving a reset signal, resets the communicating section of the second communication apparatus. | 04-14-2011 |
| 20110084750 | MODULATION APPARATUS AND TEST APPARATUS - Provided is a modulation apparatus that outputs an output signal having a designated amplitude and a designated phase, comprising a first variable delay section that outputs a first delayed signal obtained by delaying a periodic signal by a set delay time; a second variable delay section that outputs a second delayed signal obtained by delaying the periodic signal by a set delay time; an adding section that adds together the first delayed signal and the second delayed signal, and outputs the result as the output signal; and a setting section that sets the delay times for the first variable delay section and the second variable delay section according to the designated amplitude and the designated phase. | 04-14-2011 |
| 20110084721 | MANUFACTURING METHOD AND WAFER UNIT FOR TESTING - A manufacturing method of manufacturing a wafer unit for testing includes forming a plurality of test circuits on a circuit wafer, forming a plurality of circuit pads on a predetermined surface of a connecting wafer, forming a plurality of wafer pads on a rear surface of the connection wafer opposing the predetermined surface, forming a plurality of long via holes to electrically connect the plurality of circuit pads and the plurality of wafer pads, and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads. | 04-14-2011 |
| 20110081137 | MANUFACTURING EQUIPMENT AND MANUFACTURING METHOD - There are provided a manufacturing apparatus and a manufacturing method for manufacturing a substrate having a dielectric film, including a heat treatment apparatus that subjects a substrate on which a raw material containing composite oxide is applied, to heat treatment and crystallization in an atmosphere containing oxygen in a volume ratio of 20% or above under pressure of an atmospheric pressure or above. The manufacturing apparatus may manufacture a substrate having a ferroelectric film used as an optical control device. The heat treatment apparatus may include: a chamber that keeps, in the atmosphere, the substrate on which the raw material is applied; and a pressure adjusting section that adjusts a pressure of the atmosphere in the chamber to a predetermined value for a predetermined time period during heat treatment. | 04-07-2011 |
| 20110075127 | ELECTROMAGNETIC WAVE MEASURING APPARATUS - A desired spatial resolution upon a measurement can be attained by making an electromagnetic wave including a terahertz wave (frequency thereof is equal to or more than 0.01 [THz], and equal to or less than 100 [THz]) incident to a device under test. An electromagnetic wave measurement device includes an incident lens which makes an electromagnetic wave to be measured having a frequency equal to or more than 0.01 [THz] and equal to or less than 100 [THz] incident to a device under a test while decreasing a beam diameter of the electromagnetic wave to be measured, a scanning stage which rotates, about a line orthogonal to an optical axis of the incident lens as a rotational axis, the device under the test or the optical axis, and an electromagnetic wave detector which detects the electromagnetic wave to be measured which has transmitted through the device under the test, where a coordinate on the optical axis of a position which gives the minimum value d of the beam diameter is different from a coordinate on the optical axis of the rotational axis. | 03-31-2011 |
| 20110074518 | QUADRATURE AMPLITUDE MODULATOR AND QUADRATURE AMPLITUDE MODULATION METHOD - A quadrature amplitude modulator is provided. An oscillator generates an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase carrier signal. A multi-level driver generates an in-phase modulated signal by amplitude modulating the in-phase carrier signal with an analog in-phase baseband signal having a discrete voltage level or current level in accordance with the in-phase baseband data. Likewise, the multi-level driver generates a quadrature modulated signal by amplitude modulating the quadrature carrier signal with an analog quadrature baseband signal having a discrete voltage level or current level in accordance with the quadrature baseband data The multi-level driver generates a modulated signal, the amplitude of which takes a discrete level, by combining the modulated signals together. | 03-31-2011 |
| 20110074497 | POWER SUPPLY STABILIZING CIRCUIT, ELECTRONIC DEVICE AND TEST APPARATUS - A test apparatus that tests a device under test, comprising a signal input section that supplies a test signal to a device under test and a judging section that judges acceptability of the device under test based on a response signal output by the device under test in response to the test signal. The signal input section includes an operation circuit that operates to generate the test signal and a power supply stabilizing circuit provided in the same chip to stabilize power supply voltage supplied to the operation circuit. The power supply stabilizing circuit includes a high-speed compensating section compensating for a change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed, and a low-speed compensating section compensating for the change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed lower than that of the high-speed compensating section. | 03-31-2011 |
| 20110074456 | PROBE APPARATUS AND TEST APPARATUS - A probe apparatus exchanging signals with a target device, includes: a contact section electrically connected to the target device by contacting a terminal of the target device; a non-contact section that exchanges signals with the target device in a state not contacting the terminal of the target device; and a retaining section that retains the contact section and the non-contact section, in such a manner that a relative position between the contact section and the non-contact section in a connection direction connecting the non-contact section and a region corresponding to the target device is displaceable. | 03-31-2011 |
| 20110062979 | TEST SYSTEM AND PROBE APPARATUS - A probe apparatus includes a wire substrate with terminals; a wafer tray forming a hermetically sealed space with the wire substrate and for mounting a semiconductor wafer; a probe wafer provided between the wire substrate and the wafer tray, having an apparatus connection terminal electrically connected to a terminal of the wire substrate and wafer connection terminals electrically connected to the semiconductor chips respectively and collectively; an apparatus anisotropic conductive sheet provided between the wire substrate and the probe wafer; a wafer anisotropic conductive sheet provided between the probe wafer and the semiconductor wafer; and a decompressing section that decompresses the hermetically sealed space between the wire substrate and the wafer tray, to cause the wafer tray to move to a predetermined position from the wire substrate, to electrically connect the wire substrate and the probe wafer, and to electrically connect the probe wafer and the semiconductor wafer. | 03-17-2011 |
| 20110062977 | PROBE CIRCUIT, MULTI-PROBE CIRCUIT, TEST APPARATUS, AND ELECTRIC DEVICE - A probe circuit is provided in an electronic device that includes a circuit which is under test and outputs a response signal corresponding to an input signal in synchronization with an operation clock. The probe circuit includes a sampling clock supplying section that outputs a sampling clock having a predetermined frequency, and a sampling section that outputs, outside the electronic device, a probe output signal of which frequency is lower than a frequency of the response signal and which corresponds to a sampling result obtained by sampling the response signal using the sampling clock. The response signal has a prescribed signal pattern repeated with a predetermined recurrence period, and the sampling clock supplying section outputs the sampling clock of which relative phase with respect to the signal pattern sequentially changes in each recurrence period. | 03-17-2011 |
| 20110062920 | POWER SUPPLY, TEST APPARATUS, AND CONTROL METHOD - A power supply that outputs an output voltage corresponding to a specified voltage through an output terminal includes a plurality of switches that selects which of a high voltage and a low voltage is coupled to the output terminal, a multi-phase pulse width modulating section that controls a pulse width of the high voltage output from each of the plurality of the switches to cause the output voltage to approach the specified voltage, and a changing section that changes a voltage difference between the high voltage and the low voltage according to the specified voltage or the output voltage. | 03-17-2011 |
| 20110060933 | TEST APPARATUS AND TEST METHOD - There is provided a test apparatus for testing a device under test, including a plurality of test modules that test the device under test, and a synchronization module that is connected to each of the plurality of test modules, where the synchronization module synchronizes together the plurality of test modules. Here, based on a synchronization signal received from a digital module, the synchronization module synchronizes an analog module to the digital module, and the digital module is one of the plurality of test modules that exchanges a digital signal with the device under test, and the analog module is one of the plurality of test modules that performs an analog test on the device under test. | 03-10-2011 |
| 20110060545 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a pattern list storage section that stores a plurality of pattern lists that each designate, in a prescribed order, the test patterns to be output by the device under test; and a pattern list processing section that (i) sequentially outputs the test patterns by sequentially executing the pattern lists according to test results of the device under test and, (ii) when transitioning from a current pattern list to a subsequent pattern list, repeatedly outputs a prescribed idle pattern until execution of the subsequent pattern list is begun. | 03-10-2011 |
| 20110057673 | TEST APPARATUS AND TEST METHOD - There is provided a test apparatus for testing a device under test, including: a plurality of test sections; and a first synchronization section and a second synchronization section that, for each of a plurality of domains that respectively include one or more of the plurality of test sections, synchronize the one or more test sections included in the domain, where each of the first synchronization section and the second synchronization section includes: a local collection section that collects, for each domain, synchronization requests from the test sections connected to the corresponding synchronization section; an exchange section that exchanges, for a discrete domain of that includes test sections connected to the first synchronization section and test sections connected to the second synchronization section, synchronization requests collected in the corresponding synchronization section with synchronization requests collected in the other synchronization section; a global collection section that collects, the synchronization requests collected in the corresponding synchronization section and the synchronization requests collected in the other synchronization section; and a distribution section that distributes the collected synchronization requests to each of the test sections connected to the corresponding synchronization section. | 03-10-2011 |
| 20110057665 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A pattern generator generates test data to be transmitted. An encoding circuit generates amplitude data which represent a modulated signal waveform that corresponds to the test data. The amplitude data are generated in a parallel manner in the form of multiple amplitude data in increments of multiple sampling points set within a predetermined period for cycles of the predetermined period. A data rate setting unit receives the multiple amplitude data in increments of sampling points, latches the amplitude data at corresponding sampling timings, and sequentially outputs the amplitude data thus latched. A multi-level driver receives sequentially input amplitude data, and generates a test signal having a level that corresponds to the value of the amplitude data thus received. | 03-10-2011 |
| 20110057664 | DEVICE-DEPENDENT REPLACEABLE UNIT AND MANUFACTURING METHOD - There is provided a device-dependent replaceable unit for use with a test apparatus, which can reduce signal deterioration. The device-dependent replaceable unit is selected depending on a type of a device under test, and to be mounted on the test apparatus to form a signal path between the device under test and the test apparatus. The device-dependent replaceable unit includes a socket board that has a front surface and a back surface, where the device under test is to be moved close to or away from the front surface of the socket board, and a plurality of spring pins that are positioned in a same manner as a plurality of connection terminals of the device under test, where the spring pins are supported by the socket board in such a manner that upper ends of the spring pins protrude from the front surface of the socket board and come into contact with the connection terminals of the device under test. | 03-10-2011 |
| 20110057663 | TEST APPARATUS SYNCHRONOUS MODULE AND SYNCHRONOUS METHOD - Provided is a test apparatus that tests a device under test, comprising a plurality of test modules that test the device under test; a synchronization module that is connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module. The synchronization module includes a receiving section that receives, from each of the plurality of test modules, a state signal indicating a state of the test module; an aggregating section that generates an aggregate state signal by calculating an aggregate of the state signals received by the receiving section; and a transmitting section that transmits, to the plurality of test modules, a control signal ordering an operation corresponding to the aggregate state signal. | 03-10-2011 |
| 20110057642 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - An amplitude expected value data generator generates amplitude expected value data that represents, in increments of sampling points, which of multiple amplitude segments the amplitude of a modulated signal waveform that corresponds to the expected value of data to be output from a device under test belongs to. A demodulator performs sampling of the signal waveform to be tested received from the device under test, and generates judgment data that represents, in increments of sampling points, which of the multiple amplitude segments the amplitude of the signal waveform belongs to. A judgment unit makes a comparison between the amplitude expected value data and the judgment data in increments of sampling points. | 03-10-2011 |
| 20110057103 | CONTAINER, CONTAINER POSITIONING METHOD, AND MEASURING METHOD - A container according to the present invention contains at least a part of a device under test to be measured by a terahertz wave measurement device. The container includes a gap portion that internally disposes at least a part of the device under test, and an enclosure portion that includes a first flat surface portion and a second flat surface portion, and disposes the gap portion between the first flat surface portion and the second flat surface portion, thereby enclosing the gap portion. Moreover, a relationship n | 03-10-2011 |
| 20110051798 | EQUALIZER CIRCUIT - An equalizer circuit receives digital amplitude data A[N] which represents the amplitude level of the N-th (N is a nonnegative integer) signal to be transmitted via a transmission line and timing data T[N] which represents the cycle of the signal, and performs waveform shaping. The equalizer circuit includes: M (M is an integer) calculation units ECU | 03-03-2011 |
| 20110050194 | DRIVER CIRCUIT AND TEST APPARATUS - Provided is a driver circuit that outputs, from an output end, an output signal corresponding to an input signal supplied thereto, comprising an output resistance section that is provided between a constant voltage source and the output end; an output switching section that switches voltage of the output end according to the input signal; and a switching section that switches a resistance value of the output resistance section. The output resistance section includes an output resistance FET having a source/drain connection between the constant voltage source and the output end, and the switching section supplies a control voltage to a gate of the output resistance FET such that the resistance between the source and the drain of the output resistance FET switches to a designated value. | 03-03-2011 |
| 20110043250 | DRIVER CIRCUIT - A level switch circuit receives a digital input signal, and generates a level signal having a voltage level that corresponds to the value of the input signal thus received. A buffer circuit receives a level signal, and outputs the level signal via an output terminal thereof. A bias current generating circuit generates a bias current including a DC component having a constant level and a variable component that changes according to the input signal, and supplies the bias current thus generated to a buffer circuit. The bias current generating circuit detects an edge of the input signal, and raises the bias current by a predetermined amount for a predetermined period of time after the edge thus detected. | 02-24-2011 |
| 20110043237 | WAFER TRAY AND TEST APPARATUS - In order to shorten testing time of a plurality of devices under test formed on a semiconductor wafer, a wafer tray used by a test apparatus performing the test is provided. The wafer tray includes a first flow passage for fixing the semiconductor wafer to the wafer tray using vacuum suction, a second flow passage for fixing the wafer tray to the test apparatus using vacuum suction, and a heater for heating a loading surface on which at least the semiconductor wafer is loaded. By using this wafer tray, the semiconductor wafer, which is the object being tested, can be smoothly attached to and detached from different test heads, and testing can be begun quickly after the semiconductor wafer is attached to a test head. | 02-24-2011 |
| 20110031984 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a power supply that generates power supplied to the device under test; a transmission path that transmits the power generated by the power supply to the device under test; a current measuring section that measures a digital waveform of load current supplied to the device under test via the transmission path, the digital waveform including a frequency component higher than a frequency corresponding to a product of an inductance component of the power supply and a capacitance component between the transmission path and a ground potential; and a judging section that judges acceptability of the device under test based on the digital waveform of the load current measured by the current measuring section. | 02-10-2011 |
| 20110022341 | MEASUREMENT APPARATUS, PROGRAM, RECORDING MEDIUM, AND MEASUREMENT METHOD - Provided is a measurement apparatus that measures a characteristic of an AD converter, comprising a signal supplying section that supplies the AD converter with an analog input signal having a prescribed waveform; an acquiring section that acquires a digital output signal output by the AD converter as a result of sampling the analog input signal; a measured histogram generating section that generates a histogram of the digital output signal; and a range calculating section that calculates at least one of an analog value corresponding to a lower limit and an analog value corresponding to an upper limit of a prescribed digital range, based on at least one of (i) a frequency corresponding to digital values, in a measured histogram obtained by measuring the digital output signal, that are less than or equal to the digital range and (ii) a frequency corresponding to digital values in the measured histogram that are greater than or equal to the digital range. | 01-27-2011 |
| 20110018749 | CHARACTERISTIC ACQUISITION DEVICE, METHOD AND PROGRAM - It is possible to reduce errors generated between multiple D/A conversion paths. A characteristic acquisition device includes [1] an arbitrary signal generator that converts a first (second) input digital pattern into a first (second) output analog pattern, [2] a digitizer that converts a first input analog pattern into a first output digital pattern, and [3] a characteristic acquisition device that includes a first transmission characteristic deriving unit that derives a first transmission characteristic which converts the first input digital pattern into the output digital pattern where the input analog pattern is the first output analog pattern, a second transmission characteristic deriving unit that derives a second transmission characteristic which converts the second input digital pattern into the output digital pattern where the input analog pattern is the second output analog pattern, and a transmission characteristic ratio deriving unit that derives a transmission characteristic ratio which is a ratio relating to the first transmission characteristic and the second transmission characteristic. | 01-27-2011 |
| 20110018626 | QUADRATURE AMPLITUDE DEMODULATOR AND DEMODULATION METHOD - A quadrature amplitude demodulator demodulates a modulated signal on which quadrature amplitude modulation is performed. Oscillators generate an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase signal. First and second mixers respectively perform mixing of the modulated signal with the in-phase signal and the quadrature carrier signal. First and second integrators respectively integrate output signals of the first and the second mixers, for a predetermined period in accordance with the cycle of the in-phase carrier signal and the quadrature carrier signal. First and second A/D converters respectively convert outputs of the first and the second integrators into digital values. | 01-27-2011 |
| 20110018598 | PLL CIRCUIT - A PLL circuit according to the present invention includes a VCO that outputs an VCO signal having a frequency according to an input voltage, a loop filter that feeds a voltage according to an input current to the VCO, a phase comparator that outputs a phase difference pulse having a width according to a phase difference between a first input signal and a second input signal, a charge pump circuit that receives the phase difference pulse, and inputs the current to the loop filter, and a phase-difference-pulse stop unit that stops the input of the phase difference pulse to the charge pump circuit in a non-input state in which an REF signal (reference frequency signal) is not input. The first input signal is the REF signal itself or a signal obtained by dividing the frequency of the REF signal, and the second input signal is the VCO signal itself or a signal obtained by dividing the frequency of the VCO signal. | 01-27-2011 |
| 20110018559 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a power supply that generates supply power supplied to the device under test; a transmission path that transmits the supply power generated by the power supply to the device under test; an intermediate capacitor that is provided between the transmission path and a ground potential; a power supply current measuring section that measures a current flowing through the transmission path at a position closer to the power supply than the intermediate capacitor; a charge and discharge current measuring section that measures a charge and discharge current of the intermediate capacitor; and a load current calculating section that calculates a load current flowing through the device under test based on a sum of the current measured by the power supply current measuring section and the current measured by the charge and discharge current measuring section. | 01-27-2011 |
| 20110018549 | TEST APPARATUS, ADDITIONAL CIRCUIT AND TEST BOARD - Provided is a test apparatus that tests a device under test, comprising a power supply that generates power supplied to the device under test; a transmission path that transmits the power generated by the power supply to the device under test; a current measuring section that measures a peak in current supplied to the device under test via the transmission path, the peak including a frequency component higher than a frequency corresponding to a product of an inductance component from the power supply to the device under test and a capacitance component between the transmission path and a ground potential; and a judging section that judges acceptability of the device under test based on the peak measured by the current measuring section. | 01-27-2011 |
| 20110015890 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a test module that transmits and receives signals to and from the device under test; and a test control section that executes a test program for testing the device under test and that instructs the test module to execute a function designated by the test program from among a plurality of functions of the test module. The test module includes a signal input/output section that transmits and receives signals to and from the device under test; and a module control section that executes a function program according to the function designated by the test program and that accesses at least one of a register and a memory in the signal input/output section. | 01-20-2011 |
| 20110013682 | MODULATION APPARATUS, TEST APPARATUS AND CORRECTION METHOD - Provided is a modulation apparatus that quadrature modulates a periodic signal, comprising an I-side signal output section that outputs an I-component signal; a Q-side signal output section that outputs a Q-component signal; a quadrature modulator that quadrature modulates the periodic signal with the I-component signal and the Q-component signal; an I-side correcting section that corrects the I-component signal according to an error of the quadrature modulator; and a Q-side correcting section that corrects the Q-component signal according to the error of the quadrature modulator. | 01-20-2011 |
| 20110012659 | SIGNAL GENERATION APPARATUS AND TEST APPARATUS - Provided is a signal generating apparatus that generates an output signal having a designated phase, comprising a phase difference detecting section that outputs a control signal corresponding to a phase difference between a reference signal having a prescribed period and the output signal; an oscillating section that generates a periodic signal having a frequency corresponding to the control signal; and a phase shifting section that outputs the output signal to have a phase that is shifted from the phase of the periodic signal by a designated phase amount. | 01-20-2011 |
| 20110012622 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a power supply that generates supply power supplied to the device under test; a transmission path that transmits the supply power generated by the power supply to the device under test; a high-capacitance capacitor that is provided between the transmission path and a ground potential; a low-capacitance capacitor that has a lower capacitance than the high-capacitance capacitor and that is provided between the transmission path and the ground potential at a position closer to the device under test than the high-capacitance capacitor is to the device under test; an intermediate capacitor that is provided between the transmission path and the ground potential at a position between the high-capacitance capacitor and the low-capacitance capacitor; and a current measuring section that measures current flowing through the transmission path between the intermediate capacitor and the low-capacitance capacitor. | 01-20-2011 |
| 20110012612 | TEST APPARATUS - There is provided a test apparatus for testing a device under test, including a signal supply section that supplies a test signal to the device under test via a transmission line, and a comparing and judging section that receives a response signal from the device under test via the transmission line shared with the signal supply section, and judges whether the device under test is acceptable by referring to a comparison result obtained by comparing a signal level of the response signal with a reference level corresponding to a logic pattern of the test signal. | 01-20-2011 |
| 20110001468 | FREQUENCY CHARACTERISTICS MEASURING DEVICE - It is possible to provide a frequency characteristics measuring device which can simplify the configuration for performing a measurement and reduce the undue effort required for the measurement. | 01-06-2011 |
| 20110001048 | ELECTROMAGNETIC WAVE MEASURING APPARATUS, MEASURING METHOD, PROGRAM, AND RECORDING MEDIUM - According to the present invention, an electromagnetic wave measurement device includes an electromagnetic wave output device, an electromagnetic wave detector, a relative position changing unit, a delay period recording unit, a phase deriving unit, a delay-corrected phase deriving unit, a sinogram deriving unit, and an image deriving unit. The electromagnetic wave output device outputs an electromagnetic wave having a frequency equal to or more than 0.01 [THz] and equal to or less than 100 [THz] toward a device under test and a container storing at least a part of the device under test. The electromagnetic wave detector detects the electromagnetic wave which has transmitted through the device under test. The relative position changing unit changes a relative position of an intersection at which an optical path of the electromagnetic wave transmitting through the device under test and the device under test intersect with respect to the device under test. The delay period recording unit records a delay period of the electromagnetic wave caused by a transmission of the electromagnetic wave through the container. The phase deriving unit that derives, based on a detected result by the electromagnetic wave detector, a phase in the frequency domain of the electromagnetic wave which has transmitted through the device under test. The delay-corrected phase deriving unit that derives a delay-corrected phase obtained by subtracting an integral of the delay period with respect to the frequency from the phase. The sinogram deriving unit that derives a sinogram based on a derived result by the delay-corrected phase deriving unit. The image deriving unit derives, based on the sinogram, an image of a cross section of the device under test including the intersection. | 01-06-2011 |
| 20100327983 | RING OSCILLATOR - Multiple multi-stage delay circuits each have n (n is an integer) output terminals. The multi-stage delay circuits each apply delay times to a corresponding input signal, and output, via n output terminals, n delayed signals to which different delay times have been applied. Multiple inverters invert the respective input signals. The multiple multi-stage delay circuits and multiple inverters are alternately connected in the form of a ring. | 12-30-2010 |
| 20100327967 | TEST APPARATUS, DEMODULATION APPARATUS, TEST METHOD, DEMODULATION METHOD AND ELECTRIC DEVICE - Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase. | 12-30-2010 |
| 20100327917 | OUTPUT DEVICE AND TEST APPARATUS - An output device includes a main driver that outputs an output signal in accordance with an input signal input thereto, a noise driver that outputs a noise signal containing a noise waveform, a combiner that outputs a combined signal obtained by combining together the output signal and the noise signal, and a controller. The noise driver (i) sets an output end thereof at high impedance when not supplied with an enable signal, and (ii) varies an voltage level of the noise signal to be output therefrom in accordance with how a control signal supplied thereto varies when supplied with the enable signal. The controller controls the noise driver to output the noise signal containing the noise waveform that occurs when the output signal travels through a predetermined transmission line, by controlling a timing at which the control signal varies and a timing at which the enable signal is switched. | 12-30-2010 |
| 20100321682 | HOLDING FIXTURE, PLACEMENT METHOD OF HOLDING FIXTURE, AND MEASUREMENT METHOD - A container according to the present invention contains at least a part of a device under test to be measured by a terahertz wave measurement device. The container includes a gap portion that internally disposes at least a part of the device under test, and an enclosure portion that includes a first flat surface portion and a second flat surface portion, and disposes the gap portion between the first flat surface portion and the second flat surface portion, thereby enclosing the gap portion. Moreover, a relationship n | 12-23-2010 |
| 20100321127 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers. | 12-23-2010 |
