ADVANTECH GLOBAL, LTD Patent applications |
Patent application number | Title | Published |
20140342102 | Small Feature Size Fabrication Using a Shadow Mask Deposition Process - In a system and method of depositing material on a substrate, a shadow mask, including one or more apertures therethrough, in intimate contact with the substrate is provided inside of a chamber or reactor. Material ejected from a solid target material is deposited on one or more portions of the substrate after passage through the one or more apertures of the shadow mask. Desirably, a target-to-substrate distance is within a mean free path length at a specified deposition pressure. Alternatively, an electric field acts on a process gas to create a plasma that includes ionized atoms or molecules of the material that are deposited on one or more portions of the substrate after passage through the one or more apertures of the shadow mask. | 11-20-2014 |
20140325822 | Method and Apparatus for Tensioning a Shadow Mask for Thin Film Deposition - In a method and apparatus for shadow mask tensioning, a shadow mask frame and an anchor frame are positioned in spaced relation defining a gap therebetween and a shadow mask is positioned on the shadow mask frame and the anchor frame with an interior portion of the shadow mask extending across the gap. An edge of the shadow mask is affixed to the anchor frame and the shadow mask is tensioned by urging the interior portion of the shadow mask into the gap. Once the shadow mask has been tensioned to a desired extent, the shadow mask is affixed to the shadow mask frame. Thereafter, the combination of the shadow mask affixed to the shadow mask frame is separated from the anchor frame. | 11-06-2014 |
20130342843 | Reflection Shadow Mask Alignment Using Coded Apertures - In a shadow mask-substrate alignment method, a light source, a beam splitter, a first substrate including a first grate, a second substrate including a second grate, and a light receiver are positioned relative to each other to define a light path that includes light output by the light source being reflected a first time by the beam splitter. The light reflected the first time passes through the first or second grate and is at least partially reflected a second time by the second or first grate back through the first or the second grate, respectively. The light reflected the second time passes at least partially through the beam splitter for receipt by the light receiver. The orientation of the first substrate, the second substrate or both is adjusted to position the first grate, the second grate, or both until a predetermined amount is received by the light receiver. | 12-26-2013 |
20130236287 | SHADOW MASK ALIGNMENT USING CODED APERTURES - In a shadow mask-substrate alignment method, a substrate is provided that includes a grate having a plurality of spaced bars and a shadow mask is provided that includes a grate having a plurality of spaced bars. Also provided is a light source-light receiver pair that defines a path of light therebetween. The grate of the substrate and the grate of the shadow mask are caused to be positioned in the path of the light. Thereafter, the orientation of the substrate, the shadow mask, or both are caused to be adjusted to position the grate of the substrate, the grate of the shadow mask, or both until a predetermined amount of light or a predetermined range of an amount of light on the path passing through the grates is received by the light receiver. | 09-12-2013 |
20120074471 | Transistor Structure for Improved Static Control During Formation of the Transistor - A method of forming a shadow mask vapor deposited transistor includes shadow mask vapor depositing a semiconductor segment. An electrically conductive drain contact is shadow mask vapor deposited on a first part of the semiconductor segment and a first insulator is shadow mask vapor deposited on the drain contact. An electrically conductive source contact is shadow mask vapor deposited on a second part of the semiconductor segment spaced from the drain contact and a second insulator is shadow mask vapor deposited on the source contact. A third insulator is shadow mask vapor deposited over at least part of each of the first and second insulators and the semiconductor segment between the drain contact and the source contact. An electrically conductive gate contact is shadow mask vapor deposited on the third insulator and in spaced relation to the semiconductor segment between the drain contact and the source contact. | 03-29-2012 |
20100095885 | Shadow Mask Deposition Of Materials Using Reconfigurable Shadow Masks - A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate. | 04-22-2010 |
20100072466 | Electronic Circuit with Repetitive Patterns Formed by Shadow Mask Vapor Deposition and a Method of Manufacturing an Electronic Circuit Element - An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements. | 03-25-2010 |
20090311427 | Mask Dimensional Adjustment and Positioning System and Method - In a system and method of dimensional adjustment or positioning of an aperture mask for depositing a pattern of material on a substrate, an aperture mask is coupled to a frame such that the frame does not block one or more deposition apertures of the aperture mask. An external force applied to the frame causes the frame to move or bend and place the aperture mask in tension or compression thereby adjusting at least one dimension of the aperture mask or a position of at least one deposition aperture. | 12-17-2009 |
20090199968 | Method and Apparatus for Electronic Device Manufacture Using Shadow Masks - Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently. | 08-13-2009 |
20090098309 | In-Situ Etching Of Shadow Masks Of A Continuous In-Line Shadow Mask Vapor Deposition System - In a method of using and cleaning one or more shadow masks of a shadow mask vapor deposition system used to form an electronic device, a substrate is advanced through series connected deposition vacuum vessels. As the substrate advances through each deposition vacuum vessel, material from a material deposition source positioned in the deposition vacuum vessel is deposited on the substrate through a shadow mask positioned therein. The material is also deposited on a surface of the shadow mask that faces the one material deposition source. Following the deposit of material on the surface of the shadow mask in at least one deposition vacuum vessel, a reactive gas is introduced into the deposition vacuum vessel absent the substrate therein. The reactive gas is then ionized to remove the material deposited on the shadow mask. | 04-16-2009 |
20090089997 | Method Of Forming An Electrical Circuit With Overlaying Integration Layer - In a method of forming an electrical circuit assembly, a substrate is provided including a plurality of first segments that form an electrical circuit. The first segments have surfaces that rise above surfaces of other segments that form the electrical circuit. All of the segments are deposited on the substrate via one or more shadow mask vapor deposition processes in a vacuum. A photoresist caused to cover all of the segments is hardened and then abraded until surfaces of the first segments are exposed, but surfaces of the other segments are not exposed, and a surface of the abraded photoresist is at the same level as the exposed surfaces of the first segments. Second segments can be deposited on the exposed surfaces of the first segments via a shadow mask vapor deposition process in a vacuum to a level above the top surface of the abraded photoresist. | 04-09-2009 |
20080315942 | Vt Stabilization of TFT's In OLED Backplanes - In a method of reducing or undoing progressive threshold shift in a thin-film-transistor (TFT) circuit, first and second voltages applied to source and gate terminals of a first transistor cause the first transistor to conduct and apply the first voltage to the gate terminal of the second transistor. The first voltage applied to the gate terminal of the second transistor coacts with a reference voltage coupled to the source terminal of the second transistor via an LED element to cause the second transistor to not conduct whereupon the LED element does not receive electrical power. After a first predetermined period of time sufficient to reduce or undo a progressive threshold shift in the second transistor, the application of the first voltage to the gate terminal of the second transistor is terminated. | 12-25-2008 |