| ADVANPACK SOLUTIONS PTE LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120058604 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE CARRIER AND MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE USING THE SAME - A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed. | 03-08-2012 |
| 20110271902 | System For Encapsulation Of Semiconductor Dies - The present invention describes two systems ( | 11-10-2011 |
| 20110267789 | ETCH-BACK TYPE SEMICONDUCTOR PACKAGE, SUBSTRATE AND MANUFACTURING METHOD THEREOF - A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad. | 11-03-2011 |
| 20100264526 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa. | 10-21-2010 |
| 20090291530 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa. | 11-26-2009 |
| 20090102043 | Semiconductor package and manufacturing method thereof - A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa. | 04-23-2009 |
| 20080248610 | THERMAL BONDING PROCESS FOR CHIP PACKAGING - The present invention provides a thermal bonding process for chip packaging. In accordance with an aspect of the invention, there is provided an approach to solve the problems caused by the different CTEs between the die and the substrate. It discloses an improved thermal bonding process for forming pillar-shaped interconnection, which controls the thermal expansion of the semiconductor die and the substrate by applying differential heating temperature to the two, thereby minimizing the misalignment between the die and the substrate, overcoming the stresses imposed on the interconnection and allowing more reliable and accurate packaging. | 10-09-2008 |
