| ADVANCED SEMICONDUCTOR ENGINEERING, INC. Patent applications |
| Patent application number | Title | Published |
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| 20120033394 | METHOD OF FABRICATING EMBEDDED COMPONENT PACKAGE STRUCTURE AND THE PACKAGE STRUCTURE THEREOF - The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time. | 02-09-2012 |
| 20120032331 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF AND PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer. | 02-09-2012 |
| 20120028459 | MANUFACTURING PROCESS OF CIRCUIT SUBSTRATE - A manufacturing process of a circuit substrate is provided. A conductive structure including a first patterned conductive layer, a first dielectric layer, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The first dielectric layer and the second dielectric layer are respectively disposed on two opposite surfaces of the first patterned conductive layer. The first conductive layer and the second conductive layer are respectively disposed on the first dielectric layer and the second dielectric layer. The first dielectric layer is between the first patterned conductive layer and the first conductive layer. The second dielectric layer is between the first patterned conductive layer and the second conductive layer. A conductive via is formed at the conductive structure. The first conductive layer and the second conductive layer are patterned to respectively form a second patterned conductive layer and a third patterned conductive layer. | 02-02-2012 |
| 20120025363 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component. | 02-02-2012 |
| 20110304062 | CHIP PACKAGE STRUCTURE, CHIP PACKAGE MOLD CHASE AND CHIP PACKAGE PROCESS - A chip package structure including a carrier, a chip and a molding compound is provided. The chip is disposed on the carrier. The molding compound encapsulates a portion of the carrier and the chip. The top surface of the molding compound has a pin one dot and a pin gate contact. The pin one dot is located at a first corner on the top surface. The pin gate contact is located at a second corner except the first corner. The invention further provides a chip package mold chase and a chip package process using to form the chip package structure. | 12-15-2011 |
| 20110291785 | POWER INDUCTOR STRUCTURE - A variety of power inductor structures are obtained by arranging a magnetic material block between a plurality of wires and a plurality of bond fingers or bond finger pairs. The power inductor structure can provide high inductance and high currents and at the same time afford smaller sizes. | 12-01-2011 |
| 20110285014 | PACKAGING STRUCTURE AND PACKAGE PROCESS - A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip. | 11-24-2011 |
| 20110278713 | EMBEDDED COMPONENT SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME AND FABRICATION METHODS THEREOF - An embedded electronic component semiconductor package structure and a packaging process thereof are provided. By providing two or more preformed building blocks, the electronic component can be assembled to the joined building blocks to obtain the embedded component semiconductor package structure. | 11-17-2011 |
| 20110278610 | PACKAGE STRUCTURE AND PACKAGE PROCESS OF LIGHT EMITTING DIODE - A light emitting diode (LED) package structure comprising a carrier, an LED chip, a first encapsulant, at least one bonding wire, a plurality of phosphor particles and a second encapsulant is provided. The LED chip is disposed on the carrier. The LED chip has at least one electrode. The first encapsulant is disposed on the carrier and covering the LED chip. The first encapsulant is provided with at least one preformed opening exposing at least a portion of the at least one electrode. The at least one bonding wire is electrically connected between the at least one electrode and the carrier via the at least one preformed opening. The phosphor particles are distributed within the first encapsulant. The second encapsulant is disposed on the carrier and encapsulates the LED chip, the first encapsulant and the at least one bonding wire. | 11-17-2011 |
| 20110278609 | PACKAGE STRUCTURE AND PACKAGE PROCESS OF LIGHT EMITTING DIODE - A light emitted diode (LED) package structure and an LED package process are provided. The LED package structure comprises a carrier, a spacer, at least one LED chip, a junction coating, a plurality of phosphor particles, and an encapsulant. The spacer is disposed on the carrier and provided with a reflective layer covering a top surface of the spacer. The LED chip is disposed on the reflective layer and electrically connected to the carrier. The junction coating is disposed over the spacer and covers the LED chip. The phosphor particles are distributed within the junction coating. The encapsulant is disposed on the carrier and encapsulates the LED chip, the spacer and the junction coating. Uniform light output and high illuminating efficiency can be obtained by the phosphor particles uniformly distributed in the junction coating. The junction coating is formed by package level dispensing process to reduce the fabrication cost. | 11-17-2011 |
| 20110260327 | CHIP PACKAGE - A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided. | 10-27-2011 |
| 20110260266 | SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGE PROCESS - A semiconductor package structure and a package process are provided, wherein a lower surface of a die pad of a leadframe is exposed by an encapsulant so as to improve the heat dissipation efficiency of the semiconductor package structure. In addition, two chips are disposed at the same sides of the leadframe and the end portion of each of leads bonding to the upper chip is encapsulated by the encapsulant such that the scratch on the lead tips in wire bonding and die attach steps can be prevented and thus the wire bondability can be enhanced. | 10-27-2011 |
| 20110259840 | SEMICONDUCTOR PACKAGE MAGAZINE - A magazine rack suitable for holding, carrying, shipping or storing the semiconductor packages is provided. The magazine rack is designed with tiered support bars, so as to help secure the inserted packages in position and provide separation buffer. | 10-27-2011 |
| 20110259166 | CUTTING TOOL - A cutting tool suitable for cutting a workpiece placed on a photocurable adhesive layer is provided. The cutting tool includes a main body, a cutting layer and a light emitting material. The cutting layer is disposed on a surface of the main body and is applicable in cutting the workpiece. The light emitting material is disposed inside the cutting layer or between the main body and the cutting layer. The light emitting material is suitable for emitting a light capable of curing the photocurable adhesive layer adjacent to a cutting path as the workpiece is cut by the cutting layer. | 10-27-2011 |
| 20110237032 | Semiconductor Package and Method for Making the Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer. | 09-29-2011 |
| 20110217813 | METHOD OF FABRICATING MULTI-CHIP PACKAGE STRUCTURE - A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer or a chip are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures. | 09-08-2011 |
| 20110195545 | PACKAGE PROCESS - A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate. | 08-11-2011 |
| 20110193209 | SEMICONDUCTOR PACKAGE - The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of the pads of the semiconductor device and the first electrically connecting portion of the carrier, and the first wire has a first length. The second wire electrically connects one of the pads of the semiconductor device and the second electrically connecting portion of the carrier, and the second wire has a second length. The second length is larger than the first length, and the diameter of the second wire is larger than that of the first wire. Thus, the material usage for the wire is reduced, and the manufacturing cost is reduced. | 08-11-2011 |
| 20110189852 | Method for Forming a Via in a Substrate and Substrate with a Via - The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even. | 08-04-2011 |
| 20110176900 | SUCTION HEAD AND TRANSPORTING MACHINE APPLYING THE SAME - A suction head including a first transmission part, a second transmission part and a suction nozzle is provided. The second transmission part is magnetically attracted by the first transmission part to permit a displacement of the second transmission part relative to the first transmission part. The suction nozzle is disposed on the second transmission part and transmitted by the first transmission part via the second transmission part. Additionally, a transporting machine including a shuttle, a transporting mechanism and the aforementioned suction nozzle is provided. The shuttle is capable of carrying an object being transported, and the suction head is driven by the transporting mechanism to take the object being transported. The suction head and the transporting machine applying the same provide high transporting efficiency and ensuring a normal operation in transporting process. | 07-21-2011 |
| 20110175240 | CHIP MODULE - A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first glue structure is filled between the passive units so that an encircled area is defined by the first glue structure and the passive units. Then, a second glue structure is filled in the encircled area so that the chip is covered by the second glue structure. | 07-21-2011 |
| 20110173994 | COOLING SYSTEM FOR SEMICONDUCTOR MANUFACTURING AND TESTING PROCESSES - A cooling system for providing a desired environment for a semiconductor manufacturing and/or testing processes includes a vortex unit and a semiconductor processing device suitable for performing a semiconductor processing function. The vortex unit includes an air inlet for receiving compressed air, a first air exhaust for outputting an air stream having a temperature greater than the received compressed air, and a second air exhaust for outputting an air stream having a temperature lower than the received compressed air, and a dry air tube enclosing the second air exhaust and connecting to the air compressor unit and the vortex unit. Since the dry air continuously flows surrounding the cold air tube, no water will be condensed around the cold air tube. Accordingly, no pollution and damages by the condensed water will happen to the manufactured or tested products. | 07-21-2011 |
| 20110171829 | Method for Forming a Via in a Substrate and Substrate with a Via - The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the second surface of the substrate to expose the first conductive metal, the center insulating material and the first insulating material. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even. | 07-14-2011 |
| 20110169150 | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof - A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity. | 07-14-2011 |
| 20110127654 | Semiconductor Package and Manufacturing Methods Thereof - A semiconductor package and manufacturing methods thereof are provided. In one embodiment, the semiconductor package includes a die, a shield, a package body, and a redistribution layer. The die has an active surface and an inactive surface. The shield is disposed over the inactive surface of the die. The package body encapsulates the die and a first portion of the shield, where a first surface of the package body is substantially coplanar with the active surface of the die. The redistribution layer is disposed on the active surface of the die and on portions of the first surface of the package body. | 06-02-2011 |
| 20110121442 | PACKAGE STRUCTURE AND PACKAGE PROCESS - A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias. | 05-26-2011 |
| 20110117700 | STACKABLE SEMICONDUCTOR DEVICE PACKAGES - Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps. | 05-19-2011 |
| 20110084372 | PACKAGE CARRIER, SEMICONDUCTOR PACKAGE, AND PROCESS FOR FABRICATING SAME - A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments. | 04-14-2011 |
| 20110084370 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 04-14-2011 |
| 20110074004 | PACKAGE PROCESS AND PACKAGE STRUCTURE - A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the side walls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the side walls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices. | 03-31-2011 |
| 20110062567 | LEADFRAME AND CHIP PACKAGE - A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation. | 03-17-2011 |
| 20110057301 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a patterned metal foil, a chip, wires, a patterned dielectric layer, an adhesive layer, and a molding compound. The patterned metal foil has a first surface and a second surface opposite thereto. The patterned dielectric layer is disposed on the second surface and has openings exposing at least a portion of the patterned metal foil to form joints for external electrical connection. The chip is disposed on the first surface. The adhesive layer is disposed between the chip and the patterned metal foil. The wires respectively connect the chip and the patterned metal foil. The patterned dielectric layer is located below intersections between the wires and the patterned metal foil. The patterned dielectric layer, the wires, and the patterned metal foil overlap with one another on a plane. The molding compound is disposed on the first surface and covers the chip and the wires. | 03-10-2011 |
| 20110056736 | FABRICATION METHOD OF CIRCUIT BOARD, CIRCUIT BOARD, AND CHIP PACKAGE STRUCTURE - A circuit board, a chip package structure and a fabrication method of the circuit board are provided. By applying the fabrication method, a plurality of conductive channels can be formed in a single through hole of the circuit substrate. Unlike the conductive channels respectively formed in the through holes according to the related art, the conductive channels of the proposed circuit board can be formed in a single through hole. As such, it is conducive to the expansion of available layout area of the circuit board, the increase in layout flexibility, and the improvement of layout density of the circuit board. | 03-10-2011 |
| 20110049691 | SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING THE SAME - A semiconductor package includes a chip, a carrier, a bonding wire and a molding compound. The chip includes a pad. The carrier includes a finger and has an upper surface and a lower surface opposite to the upper surface, wherein the upper surface supports the chip. The bonding wire is extended from the finger to the pad for electrically connecting the chip to the carrier, wherein the bonding wire defines a projection portion on the upper surface of the carrier, a straight line is defined to pass through the finger and pad, there is a predetermined angle between the tangent line of the projection portion at the finger and the straight line. The molding compound seals the chip and the bonding wire, and covers the carrier. | 03-03-2011 |
| 20110049219 | WIRE-BONDING MACHINE WITH COVER-GAS SUPPLY DEVICE - A wire-bonding machine includes a main body, a fixture block, a mounting block, a gas supply tube, a cover-gas supply device, a capillary tool and an electrode. The fixture block is provided with a chamber defined therein and a central bore formed at one side wall of the fixture block communicating the chamber. The mounting block has a fixture member extending upwards for being mounted to the main body and an electrode clamping member extending downwards into the chamber of the fixture block. The cover-gas supply device has a continuous gas passage and an orifice defined therein. The protection gas flows in a steady flow field around the orifice in the continuous gas passage of the cover-gas supply device so as to result in better ball formation during the ball formation and ball-bonding process. | 03-03-2011 |
| 20110014751 | MANUFACTURING PROCESS FOR EMBEDDED SEMICONDUCTOR DEVICE - A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads. | 01-20-2011 |
| 20110006408 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a shielding layer conformally covering the underlying molding compound for is provided. The shielding layer can smoothly cover the molding compound and over the rounded or blunted, top edges of the molding compound, which provides better electromagnetic interferences shielding and better shielding performance. | 01-13-2011 |
| 20110001229 | PACKAGE STRUCTURE AND PACKAGE PROCESS - A package structure including a circuit substrate, at least a chip, leads and an encapsulant is provided. The circuit substrate has a first surface, a second surface opposite to the first surface, and contacts disposed on the first surface. The chip is disposed on the second surface of the circuit substrate and electrically connected to the circuit substrate. The said leads are disposed on the periphery of the second surface and surround the chip. Each lead has an inner lead portion and an outer lead portion and is electrically connected to the circuit substrate via the inner lead portion. The encapsulant encapsulates the circuit substrate, the chip and the inner lead portion and exposes the first surface of the circuit substrate and the outer lead portion, wherein the upper surface of the encapsulant and the first surface of the circuit substrate are coplanar with each other. | 01-06-2011 |
| 20100330803 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even. | 12-30-2010 |
| 20100327465 | PACKAGE PROCESS AND PACKAGE STRUCTURE - A package process is provided. First, a semiconductor substrate is disposed on a carrier, in which a surface of the carrier has an adhesive layer and the semiconductor substrate is bonded to the carrier by the adhesive layer. Next, a chip is bonded on the semiconductor substrate by flip chip technique and a first underfill is formed between the chip and the semiconductor substrate to encapsulate a plurality of first conductive bumps at the bottom of the chip. Then, a first molding compound is formed on the semiconductor substrate. The first molding compound at least encapsulates the side surface of the chip and the first underfill. Finally, the semiconductor substrate together with the chip and the first molding compound located thereon are separated from the adhesive layer of the carrier to form an array package structure. | 12-30-2010 |
| 20100295160 | QUAD FLAT PACKAGE STRUCTURE HAVING EXPOSED HEAT SINK, ELECTRONIC ASSEMBLY AND MANUFACTURING METHODS THEREOF - A quad flat package (QDP) structure having an exposed heat sink is provided. The QDP structure includes a leadframe, a chip, a heat sink, an insulating layer and a molding compound. The leadframe includes a die pad and multiple leads surrounding the die pad. The chip is disposed on the die pad and electrically connected to the die pad and the leads. The heat sink has a top surface, a bottom surface opposite thereto, and a side surface connected to the top and the bottom surfaces. The die pad is disposed in a central area of the top surface of the heat sink and electrically connected to the heat sink. The molding compound encapsulates the chip, the die pad, an inner lead portion of each lead and heat sink, and exposes the bottom surface of the heat sink and an outer lead portion of each lead. | 11-25-2010 |
| 20100288541 | SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER, AND PACKAGE APPLIED WITH THE SUBSTRATE , AND METHODS OF MANUFACTURING OF THE SUBSTRATE AND PACKAGE - A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate. | 11-18-2010 |
| 20100258934 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier having a die pad and a plurality of leads, at least a chip, a plurality of wires, and a molding compound. The rough surface of the carrier enhances the adhesion between the carrier and the surrounding molding compound. | 10-14-2010 |
| 20100258921 | ADVANCED QUAD FLAT-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads electively have a plurality of locking grooves for enhancing the adhesion between the inner leads and the surrounding molding compound. | 10-14-2010 |
| 20100258920 | MANUFACTURING METHOD OF ADVANCED QUAD FLAT NON-LEADED PACKAGE - The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability. | 10-14-2010 |
| 20100230788 | CHIP STRUCTURE, WAFER STRUCTURE AND PROCESS OF FAABRICATING CHIP - A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate. | 09-16-2010 |
| 20100219518 | QUAD FLAT NON-LEADED PACKAGE - A quad flat non-leaded package including a leadframe, a chip, a plurality of first bonding wires and a molding compound is provided. The leadframe includes a plurality of first leads, and each first lead has a first portion and a second portion that extend along an axis. The length of the first portion is greater than the length of the second portion. The thickness of the first portion is greater than the thickness of the second portion. The chip is disposed on the leadframe and covers a portion of the first portions. The first bonding wires are connected between the chip and another portion of the first portions or the chip and the second portions, such that the chip is electrically connected to the first leads through the first bonding wires. The molding compound encapsulates a portion of the first leads, the chip and the first bonding wires. | 09-02-2010 |
| 20100213598 | CIRCUIT CARRIER AND SEMICONDUCTOR PACKAGE USING THE SAME - A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad. | 08-26-2010 |
| 20100212948 | CIRCUIT BOARD AND CHIP PACKAGE STRUCTURE - A circuit board including a substrate, a conductive pattern and a solder mask layer is provided. The conductive pattern includes a pad, a tail trace and a signal trace. The tail trace connects with the edge of the pad and the signal trace connects with the edge of the pad. An angle between a portion of the signal trace neighboring the pad and the tail trace is larger than 0 degree and smaller than 180 degree. The solder mask layer is disposed on the substrate and covers a portion of conductive pattern. The solder mask layer has an opening exposing the whole pad. | 08-26-2010 |
| 20100207258 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including at least a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer disposed over the top surface of the laminate substrate can protect the chip package from the underneath EMI radiation. The chip package may further include another shielding layer over the molding compound of the chip package. | 08-19-2010 |
| 20100200981 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package, a chip is disposed on a carrier. An inert gas is run around one end of a line portion of a copper bonding wire while the end is being formed into a spherical portion. The spherical portion is bonded to a pad of the chip. The chip and the copper bonding wire are sealed and the carrier is covered by a molding compound. | 08-12-2010 |
| 20100200969 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion. | 08-12-2010 |
| 20100200965 | PACKAGE STRUCTURE FOR WIRELESS COMMUNICATION MODULE - A package structure for a wireless communication module is disclosed and includes: a substrate having an upper surface defining a supporting region, an annular ground pad surrounding the supporting region, and at least one auxiliary ground pad formed in the supporting region; at least one chip mounted on the supporting region and electrically connected to the substrate; and a shielding lid having a receiving space for receiving the chip, a ground end surface electrically connected to the annular ground pad of the substrate, and at least one auxiliary ground portion electrically connected to the auxiliary ground pad for forming at least one auxiliary ground pathway to adjust the characteristic of the enhanced peak generated by the cavity-resonance effect of the shielding lid. Thus, the enhanced peak can be shifted out of a regulated frequency range of the EMI shielding test, so that the yield thereof can be increased. | 08-12-2010 |
| 20100176407 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE AND PACKAGE STRUCTURE THEREOF - The present invention relates to a method for forming a package structure for a light emitting diode (LED) and the LED package structure thereof. By employing the same sawing process to cut through the trenches of the leadframe, the package units are singulated and different lead portions are simultaneously separated from each other in each package unit. Therefore, the overflow issues of the encapsulant can be avoided without using extra taping process. | 07-15-2010 |
| 20100140781 | QUAD FLAT NON-LEADED PACKAGE AND MANUFACTURING METHOD THEREOF - A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided. | 06-10-2010 |
| 20100139965 | EMBEDDED CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF - An embedded circuit substrate comprising: a core structure having a first surface and a second surface opposite to each other; a first patterned conductive layer disposed on the first surface and embedded in the core structure; a second patterned conductive layer disposed on the second surface and embedded in the core structure; and a plurality of conductive blocks disposed in the core structure for conducting the first patterned conductive layer and the second patterned conductive layer is provided. Furthermore, a manufacturing method of an embedded circuit substrate is also provided. | 06-10-2010 |
| 20100133675 | PACKAGE-ON-PACKAGE DEVICE, SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer. | 06-03-2010 |
| 20100110656 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a plurality of conductive bodies and a shielding layer for better electromagnetic interferences shielding is provided. The shielding layer over the molding compound contacts with the conductive bodies disposed on the substrate, and the shielding layer and the conductive bodies function as EMI shield. The shielding layer is electrically grounded through the conductive bodies connected to the laminate substrate and the ground plane of the substrate. | 05-06-2010 |
| 20100109132 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure. | 05-06-2010 |
| 20100096740 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure including a backplate, a circuit substrate, a first chip, a second chip, and a conductive film is provided. The backplate comprises a circuit layer. The circuit substrate is disposed on the backplate, and has an upper surface and an opposite lower surface. Besides, the circuit substrate has a receiving hole corresponding to the backplate. The first chip is disposed inside the receiving hole, and the first chip is electrically connected to the circuit substrate through the circuit layer of the backplate. The second chip is disposed above the first chip, and is electrically connected to the circuit substrate. The conductive film is disposed between the first chip and the second chip, wherein the conductive film is electrically connected to a ground of the circuit substrate. | 04-22-2010 |
| 20100084772 | Package and fabricating method thereof - A package and a fabricating method thereof are provided. The package includes a conductive layer, a chip, a plurality of first pads, a plurality of bonding wires and a sealant. The conductive layer has a die pad and includes a plurality of wires. A path of each wire is substantially parallel to a supporting surface of the die pad. Each wire has an upper surface and a lower surface. The chip disposed on the supporting surface has a plurality of pads. The first pads are correspondingly formed on the upper surfaces of the wires. The bonding wires electrically connect the pads of the chip to the first pads. The sealant seals up the conductive layer, the first pads, the chip and the bonding wires, and exposes the lower surface of the conductive layer. The conductive layer projects from a bottom surface of the sealant. | 04-08-2010 |
| 20100084749 | Package and fabricating method thereof - A package and a fabricating method thereof are provided. The package includes a lead frame, a chip and a sealant. The lead frame has a notch and a plurality of first notch-side leads, a plurality of first notch-side pads, a plurality of second notch-side leads and a plurality of second notch-side pads. The first notch-side leads extend to a first side of the notch. The first notch-side pads are correspondingly disposed on the first notch-side leads. The second notch-side leads extend to a second side of the notch. The second notch-side pads are correspondingly disposed on the second notch-side leads. The sealant seals up the chip and the lead frame and exposes a lower surface of the lead frame. The notch exposes a portion of the sealant. | 04-08-2010 |
| 20100071937 | CIRCUIT BOARD AND PROCESS OF FABRICATING THE SAME - A circuit board includes a dielectric layer, a circuit layer, and an insulation layer. The circuit layer is disposed on the dielectric layer and has a pad region and a trace region. The insulation layer is disposed on the circuit layer and covers the trace region. Here, a thickness of the pad region is less than a thickness of the trace region. | 03-25-2010 |
| 20100060375 | BALUN CIRCUIT MANUFACTURED BY INTEGRATE PASSIVE DEVICE PROCESS - A Balun circuit manufactured by integrate passive device (IPD) process. The Balun circuit includes a substrate, a first coplanar spiral structure, and a second coplanar spiral structure. One end of the innermost first left coil of the first coplanar spiral structure is electrically connected to the innermost first right coil through a first bridge. Two ends of the first coplanar spiral structure are electrically connected to the outermost first left coil and the outermost right coil respectively. One end of the innermost second left coil of the second coplanar spiral structure is electrically connected to the innermost second right coil through a second bridge. Two ends of the second coplanar spiral structure are electrically connected to the outermost second left coil and the outermost second right coil respectively. The first left coils and the second left coils are interlaced. The first right coils and the second right coils are interlaced. | 03-11-2010 |
| 20100059871 | LEADFRAME - A leadframe including a chip supporting plate, a lead forming plate, and solder points is provided. A notch is formed on an edge of the chip supporting plate. The thickness of the lead forming plate is less than the thickness of the chip supporting plate. The lead forming plate has a main body, inner leads, and a connecting rod. The inner leads and the connecting rod are extended from an edge of the main body. The connecting rod has an end portion fitting the notch. The solder points are located at the boundary between the end portion and the notch for structurally connecting the connecting rod and the chip supporting plate. | 03-11-2010 |
| 20100055392 | METHOD OF FABRICATING MULTI-LAYERED SUBSTRATE AND THE SUBSTRATE THEREOF - The present invention directs to fabrication methods of single-sided or double-sided multi-layered substrate by providing a lamination structure having at least a core structure and first and second laminate structures stacked over both surfaces of the core structure. The core structure functions as the temporary carrier for carrying the first and second laminate structures through the double-sided processing procedures. By way of the fabrication methods, the production yield can be greatly improved without increasing the production costs. | 03-04-2010 |
| 20100052186 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure employs a substrate having a pseudo-cavity or a keep-out zone at one side or both sides thereof. Through the pattern arrangement of the wiring layer and the solder mask layer, the thickness of the entire stacked type chip package structure is effectively reduced as lower wire loops and a thinner mold-cap can be achieved by mounting the chip within the depressed keep-out zone. In particular, the double-sided chip package structures are suitable for package on package structures adopted by mobile applications. | 03-04-2010 |
| 20100052156 | CHIP SCALE PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A chip scale package (CSP) structure and the packaging process thereof are described. By using a matrix of interlinked heat sink units compatible with the block substrate, the packaging process can be simplified and a plurality of packages units or chip scale packages with enhanced thermal performance can be obtained after singulation. | 03-04-2010 |
| 20100052122 | WIRE BODNING PACKAGE STRUCTURE - A chip package structure employing a die pad integrated with the ground/voltage pad is provided. The die pad for carrying the chip is split into at least two separate sections for accommodating the ground and the voltage. Due to the design of the die pad, the signal fingers may be extended under the chip to be connected with vias, and thermal/ground vias may be arranged under the die pad for thermal or electrical connections. Through such arrangement, all the fingers are located closer to the die, thus decrease the length of bonding wires and reducing the package dimensions. | 03-04-2010 |
| 20100044850 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the central portion and the peripheral portion. The central portion, the peripheral portion, and the connecting portions define at least two hollow regions. The leads are disposed around the die pad. The chip is located within the central portion of the die pad and electrically connected to the leads via a plurality of wires. The molding compound encapsulates the chip, the wires, inner leads and a portion of the carrier. | 02-25-2010 |
| 20100044843 | ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The leads include first leads disposed around the die pad, second leads disposed around the first leads and at least an embedded lead portion between the first leads and the second leads. The wires are disposed between the chip, the first leads and the embedded lead portion. The advanced quad flat non-leaded package structures designed with the embedded lead portion can provide better electrical connection. | 02-25-2010 |
| 20100032822 | CHIP PACKAGE STRUCTURE - A chip package structure including a first substrate, a chip, a second substrate, a plurality of conductive wires, a plurality of solder balls and a molding compound is provided. The chip is disposed on the first substrate. The second substrate disposed on the chip has an upper surface and a lower surface, in which a distance of the lower surface relative to the chip is smaller than that of the upper surface relative to the chip. The upper surface has a ball mounting surface and a wire bonding surface. A distance between the wire bonding surface and the first substrate is smaller than that between the ball mounting surface and the first substrate. The conductive wires connect the wire bonding surface to the first substrate. The solder balls are disposed on the ball mounting surface. The molding compound is disposed on the first substrate. | 02-11-2010 |
| 20100018761 | EMBEDDED CHIP SUBSTRATE AND FABRICATION METHOD THEREOF - An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip. | 01-28-2010 |
| 20100007439 | TRANSFORMER - A transformer is provided with four capacitors and four inductors. The first capacitor is electrically connected between a first port and ground in series. The first inductor is electrically connected to the first port in series. The second capacitor is electrically connected between the first inductor and ground in series. The second inductor is electrically connected between the first inductor and the second capacitor in series. The third capacitor is electrically connected between a second port and ground in series. The third inductor is electrically connected to the second port in series. The fourth capacitor is electrically connected between a third port and ground in series. The fourth inductor is electrically connected between the third inductor and the third port in series. | 01-14-2010 |
| 20100007438 | BAND PASS FILTER - A band pass filter includes an original circuit. An interaction of at least two of components of the original circuit produces at least a mutual capacitor or at least a mutual inductor, which constitutes a resonance circuit with the original circuit to produce at least a transmission zero for increasing the attenuation rate of the stop band. | 01-14-2010 |
| 20100007011 | SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING A SEMICONDUCTOR PACKAGE - A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad. | 01-14-2010 |
| 20100007010 | SEMICONDUCTOR PACKAGE, METHOD FOR ENHANCING THE BOND OF A BONDING WIRE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE - A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire. | 01-14-2010 |
| 20100007009 | SEMICONDUCTOR PACKAGE AND METHOD FOR PROCESSING AND BONDING A WIRE - A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion. | 01-14-2010 |
| 20100007004 | WAFER AND SEMICONDUCTOR PACKAGE - A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad. | 01-14-2010 |
| 20100006330 | STRUCTURE AND PROCESS OF EMBEDDED CHIP PACKAGE - A process of an embedded chip package structure includes following steps. Firstly, a metal core layer having a first surface, a second surface opposite to the first surface, an opening, and a number of through holes are provided. The opening and the through holes connect the first surface and the second surface. A chip is then disposed in the opening. Next, a dielectric layer is formed in the opening and the through holes to fix the chip in the opening. Thereafter, a number of conductive vias are respectively formed in the through holes and insulated from the metal core layer by a portion of the dielectric layer located in the through holes. A circuit structure is then formed on the first surface of the metal core layer by performing a build-up process, and the circuit structure electrically connects the chip and the conductive vias. | 01-14-2010 |
| 20100001827 | TRANSFORMER - A transformer, adapted for being configured in a wiring substrate, is provided. The transformer includes a first plane coil and a second plane coil. The first plane coil includes a plurality of first loops. The second plane coil includes a plurality of second loops. A first bundle constituted by at least two adjacent first loops and a second bundle constituted by at least two adjacent second loops are stridden one over another. | 01-07-2010 |
| 20100000775 | CIRCUIT SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE - A circuit substrate suitable for being connected to at least one solder ball is provided. The circuit substrate includes a substrate, at least one bonding pad, and a solder mask. The substrate has a surface. The bonding pad is disposed on the surface of the substrate for being connected to the solder ball. The solder mask covers the surface of the substrate and has an opening for exposing a portion of the bonding pad. The opening has a first end and a second end. As compared with the second end, the first end is much farther from the bonding pad, and a diameter of the first end is larger than that of the second end. | 01-07-2010 |
| 20090308647 | CIRCUIT BOARD WITH BURIED CONDUCTIVE TRACE FORMED THEREON AND METHOD FOR MANUFACTURING THE SAME - A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads and fingers of the conductive trace layer are heightened to facilitate the subsequent process of molding. | 12-17-2009 |
| 20090298227 | METHOD OF FABRICATING A STACKED TYPE CHIP PACKAGE STRUCTURE AND A STACKED TYPE PACKAGE STRUCTURE - A method of fabricating a stacked type chip package structure is provided. The method includes following steps. First, a substrate, a first chip, and a second chip are provided. A number of bumps are disposed on a surface of the second chip. The second chip is then fixed on a surface of the first chip. Next, the second chip and the first chip on the substrate are turned upside down, and then the second chip is electrically connected to the substrate through the bumps by using a flip chip bonding technique. After that, the first chip is electrically connected to the substrate. Finally, a molding compound is formed on the substrate for encapsulating the first chip, the second chip, and the bumps. | 12-03-2009 |
| 20090294027 | CIRCUIT BOARD PROCESS - A circuit board process is provided. In the circuit board process, a first substrate and a second substrate are stacked to form a cavity for accommodating chips. The top of the cavity is covered by a third metal layer that serves as a mask. The first substrate has a base, a first metal layer, a second metal layer, and at least a first conductive structure passing through the base and electrically connected to the first metal layer and the second metal layer. The first metal layer is patterned to form a first circuit layer having a number of first pads. A third circuit layer having a number of third pads is formed on the second substrate. The first pads and the third pads are not on a same plane for wire bonding. | 12-03-2009 |
| 20090289339 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener. | 11-26-2009 |
| 20090289338 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener. | 11-26-2009 |
| 20090288861 | CIRCUIT BOARD WITH BURIED CONDUCTIVE TRACE FORMED THEREON AND METHOD FOR MANUFACTURING THE SAME - A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads of the conductive trace layer are plated with a layer of copper so that the pads are heightened to facilitate the subsequent process of molding. | 11-26-2009 |
| 20090278626 | BAND PASS FILTER - A band pass filter is suitable to be formed in a multi-layered circuit substrate of a wireless communication module. The band pass filter includes an input port, a first inductor, a first capacitor, a first parasitic capacitor, a second capacitor, a second inductor, a second parasitic capacitor, a third inductor, a third parasitic capacitor and a output. The input port, first inductor, first capacitor, second capacitor, third inductor and output port are sequentially electrically connected in series. The first parasitic capacitor is induced between the first inductor, first capacitor and a ground. The second inductor is electrically connected to the first capacitor, second capacitor and ground. The second parasitic capacitor is induced between the second inductor, first capacitor, second capacitor and ground. The second parasitic capacitor is electrically connected in parallel with the second inductor. The third parasitic capacitor is induced between the third inductor, second capacitor and ground. | 11-12-2009 |
| 20090278243 | STACKED TYPE CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed on the die pads respectively, and are electrically connected to the leads by wire bonding. The third chip traverses the first chip and the second chip, and is electrically connected to the first chip and the second chip respectively. The insulating material is disposed on the chip carrier for encapsulating the first chip, the second chip and the third chip, and fills among the die pads and the leads. | 11-12-2009 |
| 20090278242 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip. | 11-12-2009 |
| 20090261470 | CHIP PACKAGE - A chip package comprising a carrier, a chip, a plurality of first conductive elements, an encapsulation, and a conductive film is provided. The carrier has a carrying surface and a back surface opposite to the carrying surface. Furthermore, the carrier has a plurality of common contacts in the periphery of the carrying surface. The chip is disposed on the carrying surface and electrically connected to the carrier. In addition, the first conductive elements are disposed on the common contacts respectively. The encapsulation is disposed on the carrying surface and encapsulating the chip. Moreover, the conductive film is disposed over the encapsulation and the first conductive elements, so as to electrically connect with the common contacts via the first conductive elements. A process for fabricating the chip package is further provided. The chip package is capable of preventing the EMI problem and thus provides superior electrical performance. | 10-22-2009 |
| 20090260872 | MODULE FOR PACKAGING ELECTRONIC COMPONENTS BY USING A CAP - A module for packaging electronic components includes a carrier, at least one electronic component and a cap. The carrier has a first region and a second region. The electronic component is disposed on the first region of the carrier. The cap is mounted on the second region, and includes an inner layer and an outer layer, wherein the inner layer is made of a non-conductive material, the outer layer is made of a conductive material, and the inner layer made of the non-conductive material covers the electronic components and the whole first region. | 10-22-2009 |
| 20090252931 | REINFORCED ASSEMBLY CARRIER AND METHOD FOR MANUFACTURING THE SAME AS WELL AS METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGES - A reinforced assembly carrier is provided. A supporting frame made of molding compound is formed on the edge area of the upper surface and/or on the edge area of the lower surface of the assembly carrier thereby enhancing the mechanical strength of the assembly carrier. | 10-08-2009 |
| 20090250806 | SEMICONDUCTOR PACKAGE USING AN ACTIVE TYPE HEAT-SPREADING ELEMENT - A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on the chip and located in the through opening. | 10-08-2009 |
| 20090249618 | METHOD FOR MANUFACTURING A CIRCUIT BOARD HAVING AN EMBEDDED COMPONENT THEREIN - A method for manufacturing a circuit board includes the following steps. First, a core layer is provided, wherein the core layer includes a first dielectric layer, and first and second metallic layers. A through hole is formed in the core layer. The core layer is disposed on a supporting plate, and an embedded component is disposed in the through hole, wherein the second metallic layer contacts the supporting plate, and the embedded component has at least one electrode contacting the supporting plate. The embedded component is mounted in the through hole. The supporting plate is removed. The first and second metallic layers are removed, and the thickness of the electrode of the embedded component is decreased. Third and fourth metallic layers are formed respectively, wherein the fourth metallic layer is electrically connected to the electrode of the embedded component. Finally, the third and fourth metallic layers are patterned so as to respectively form first and second patterned circuit layers. | 10-08-2009 |
| 20090239329 | METHOD FOR MANUFACTURING PACKAGE STRUCTURE OF OPTICAL DEVICE - A package structure of optical devices has a chip, a sealant, a cover, a substrate, a plurality of bonding wires, and a transparent encapsulant. The chip has at least an optical device and a plurality of chip connection pads. The sealant is disposed around the optical elements. The cover is disposed on the sealant. The substrate supports the chip and has a plurality of connection pads. The bonding wires are used for electrically connecting the chip connection pads of the chip to the connection pads of the substrate. The transparent encapsulant is formed over the substrate and the cover, and encapsulates the bonding wires. | 09-24-2009 |
| 20090230564 | CHIP STRUCTURE AND STACKED CHIP PACKAGE AS WELL AS METHOD FOR MANUFACTURING CHIP STRUCTURES - A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals. | 09-17-2009 |
| 20090230544 | HEAT SINK STRUCTURE AND SEMICONDUCTOR PACKAGE AS WELL AS METHOD FOR CONFIGURING HEAT SINKS ON A SEMICONDUCTOR PACKAGE - A heat sink structure according to the present invention is provided. The heat sink has a through opening extending from the upper surface through to the lower surface. A solder is disposed in the through opening and on the upper and lower surfaces of the heat sink, wherein the portion of the solder in the through opening is connected with the portions of the solder on the upper and lower surfaces. | 09-17-2009 |
| 20090218669 | MULTI-CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a multi-chip package structure is provided. In the method, a number of cavities are formed on a predetermined cutting line of a first wafer by partly removing the first wafer and a first metal layer. Conductive walls of a first circuit layer are electrically connected to a cut cross-section of the first metal layer exposed by the cavities. In addition, conductive bumps of a second wafer are pressed into a cover layer and electrically connected to the first circuit layer. The first metal layer is then patterned to form a second circuit layer having a number of second pads. Next, the first wafer and the second wafer are cut along the predetermined cutting line to form a number of separated multi-chip package structures. | 09-03-2009 |
| 20090215228 | WAFER LEVER FIXTURE AND METHOD FOR PACKAGING MICRO-ELECTRO-MECHANICAL-SYSTEM DEVICES - A fixture for packaging MEMS devices includes a base, a first material layer, an insulating layer and a second material layer. The base defines units, each including a notch. The first material layer is disposed on the base and the notches. The insulating layer is disposed on a part of the first material layer and exposes the other part of the first material layer located on the notches. The second material layer is disposed on the other part of the first material layer and formed with caps, whereby the caps are physically connected to the MEMS devices, and the MEMS devices are corresponding to the units of the base, wherein there is a first connecting force between the first and second material layers, there is a second connecting force between the caps and the MEMS devices, and the second connecting force is greater than the first connecting force. | 08-27-2009 |
| 20090194858 | HYBRID CARRIER AND A METHOD FOR MAKING THE SAME - The present invention relates to a hybrid carrier and a method for making the same. The hybrid carrier has a plurality of interconnection leads, so that a wire bondable semiconductor device or a flip chip die apparatus can be placed on the hybrid carrier, and is electrically connected to die paddle and bond fingers. Also, it is easy to dispose a semiconductor device on the hybrid carrier and easy to electrically bond the hybrid carrier and the semiconductor device. Therefore, the hybrid carrier and the method for making the same can be applied to an area array metal CSP easily, and the method of the present invention is simple, so the production cost can be reduced. | 08-06-2009 |
| 20090194227 | TOOL AND METHOD FOR PACKAGING LENS MODULE - A tool and a method for packaging lens module are provided. The method for packaging lens module includes the following steps. Firstly, a carrier having at least one cavity is provided. Next, a holder is disposed in the cavity. Then, a die is disposed on a surface of a substrate. After that, the substrate is inversely placed on the carrier, wherein the surface where the die is disposed faces the carrier, and the die corresponds to the holder. Then, a cover plate covers the carrier and the substrate, such that the substrate is fixed on the holder. | 08-06-2009 |
| 20090191329 | SURFACE TREATMENT PROCESS FOR CIRCUIT BOARD - A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer. | 07-30-2009 |
| 20090190025 | Image-capturing module and manufacturing method thereof - An image-capturing module and a manufacturing method thereof are provided. The image-capturing module includes a circuit board, an electric element, a lens set and a carrier. The circuit board has at least a locking hole. The electric element is disposed on the circuit board. The carrier is disposed on the circuit board for carrying the lens set. The carrier has at least a hook locking at the locking hole of the circuit board. | 07-30-2009 |
| 20090189626 | APPARATUS AND METHOD FOR DETECTING ELECTRONIC DEVICE TESTING SOCKET - An apparatus for detecting an electronic device testing socket including a testing base, a detecting circuit board, a depth gauge, and a conductive pressing block is provided. The detecting circuit board disposed on the testing base has a carrying surface for carrying an electronic device testing socket. The electronic device testing socket includes a plurality of pin units, and each of the pin units includes an S-shaped pin and a pair of elastic rods accommodated within recesses thereof. The depth gauge disposed on the testing base presses against a top surface of the conductive pressing block, and presses with a bottom surface thereof against the electronic device testing socket. The depth gauge is adapted to adjust a distance between the top surface of the conductive pressing block and the carrying surface. The detecting circuit board is electrically connected to the pin units for detecting the status of the pin units. | 07-30-2009 |
| 20090189270 | MANUFACTURING PROCESS AND STRUCTURE FOR EMBEDDED SEMICONDUCTOR DEVICE - A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads. | 07-30-2009 |
| 20090189255 | WAFER HAVING HEAT DISSIPATION STRUCTURE AND METHOD OF FABRICATING THE SAME - A wafer having a heat dissipation structure is provided. The wafer having the heat dissipation structure includes a wafer and a number of metallic heat dissipation parts. The wafer has a first surface and a second surface opposite thereto. Besides, a number of blind holes are formed on the second surface of the wafer. The metallic heat dissipation parts are partially embedded in the blind holes respectively and protrude from the second surface of the wafer. | 07-30-2009 |
| 20090184405 | Package structure - A package structure is provided. The package structure includes a substrate, a semiconductor device, and a shielding cap. The substrate has at least an alignment recess located at a corner of the substrate. The semiconductor device is disposed on an upper surface of the substrate. The shielding cap having an alignment pin covers the semiconductor device. The alignment pin is inserted into the alignment recess. | 07-23-2009 |
| 20090175312 | BONDING STRENGTH MEASURING DEVICE - A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform. | 07-09-2009 |
| 20090170244 | METHOD FOR MANUFACTURING A FLIP CHIP PACKAGE - A method for manufacturing a flip chip package uses a dipping method to cohere liquid-state stannum onto a plurality of gold bumps of a chip. The gold bumps are correspondingly connected to a plurality of first pads of a substrate so as to connect the chip and the substrate. Finally, a protecting gel layer is disposed between the substrate and the chip, and covers the gold bumps. By utilizing the manufacturing method of the invention, the production cost can be reduced, and the manufacturing method of the invention can apply to processes in which the bump pitch is less than 60 microns. In addition, through the manufacturing method of the invention, the gold bumps are strongly joined with the first pads. Moreover, the manufacturing method of the invention can apply to various processes, so the application has a wide range of uses. | 07-02-2009 |
| 20090152721 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer. | 06-18-2009 |
| 20090140436 | METHOD FOR FORMING A VIA IN A SUBSTRATE AND SUBSTRATE WITH A VIA - The present invention relates to a method for forming a via in a substrate and a substrate with a via. The method for forming a via in a substrate includes the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove that has a side wall and a bottom wall on the first surface of the substrate; (c) forming a first conductive metal on the side wall and the bottom wall of the groove so as to form a central groove; (d) forming a center insulating material in the central groove; (e) forming an annular groove that surrounds the first conductive metal on the first surface of the substrate; (f) forming a first insulating material in the annular groove; and (g) removing part of the second surface of the substrate to expose the first conductive metal, the center insulating material and the first insulating material. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even. | 06-04-2009 |
| 20090127706 | CHIP STRUCTURE, SUBSTRATE STRUCTURE, CHIP PACKAGE STRUCTURE AND PROCESS THEREOF - A chip package structure and process are provided; the structure includes a substrate, a chip, a solder layer and at least a stud bump. The substrate has at least a contact pad, and the chip has an active surface where at least a bonding pad is disposed. The stud bump is disposed on the bonding pad of the chip or on the contact pad of the substrate, and the stud bump joints with the solder layer to fix the chip on the substrate. The stud bump is made of gold-silver alloy containing silver below 15% by weight. | 05-21-2009 |
| 20090127682 | CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a chip package structure is provided. A metallic plate having a first surface, a second surface, and a first patterned metallic layer formed on the first surface thereof is provided. A half-etching process is performed to form first recesses on the first surface of the metallic plate, wherein leads are defined on the metallic plate by the first recesses. A first insulating material fills in each of the first recesses. A second patterned metallic layer is formed on the second surface of the metallic plate. A half-etching process is performed to form second recesses on the second surface of the metallic plate. The second recesses correspond to the first recesses, respectively, and expose the first insulating material inside the first recesses, such that the leads are electrically isolated from one another. A chip is placed on the metallic plate and electrically connected thereto. | 05-21-2009 |
| 20090117832 | WAFER POLISHING METHOD - A wafer polishing method is provided. First, a wafer, having a first surface, a second surface, and a plurality of opening portions depressed on the first surface, is provided. A plastic adhesive is filled in the opening portions and cured later. A polishing step is performed to thin the thickness of the wafer. Therefore, the yield of the wafer in the polishing process can be improved by the protection of the plastic adhesive. | 05-07-2009 |
| 20090115007 | MEMES PACKAGE STRUCTURE - A package structure including a chip, a lid, a substrate, a plurality of wires, an encapsulant, and a moisture resistive layer is provided. The chip has an active area where at least one MEMS device is disposed. The lid is covered on the chip, and the substrate is used to carry the chip and the lid. The plurality of wires is electrically connected between the substrate and the chip. The encapsulant is sealed around the lid and exposes an upper surface of the lid. The moisture resistive layer is covered on the encapsulant to enhance the airtightness and the moisture resistance of the encapsulant. | 05-07-2009 |
| 20090114436 | SUBSTRATE STRUCTURE - A substrate structure is provided. A plurality of solder pads is positioned on a substrate. A solder mask covers the substrate and has a plurality of openings to respectively expose portions of the solder pads, wherein the openings have the shape of a polygon of at least five sides. | 05-07-2009 |
| 20090108445 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME - A substrate structure is provided. The substrate structure includes a substrate and a patterned wiring layer formed on the substrate. The patterned wiring layer includes a plurality of conductive traces. An isolation layer covers the patterned wiring layer and has an opening to expose a portion of at least one of the conductive traces therefrom. A plurality of conductive coatings covers the exposed portions of the conductive traces. The present invention further provides a semiconductor package with the above substrate structure. | 04-30-2009 |
| 20090102066 | Chip package structure and method of manufacturing the same - A chip package structure and a method of manufacturing the same are provided. The chip package structure includes a package portion and a plurality of external conductors. The package portion includes a distribution layer, a chip, a plurality internal conductors and a sealant. The distribution layer has a first surface and a second surface, and the chip is disposed on the first surface. Each internal conductor has a first terminal and a second terminal. The first terminal is disposed on the first surface. The sealant is disposed on the first surface for covering the chip and partly encapsulating the internal conductors, so that the first terminal and the second terminal of each internal conductor are exposed from the sealant. The external conductors disposed on the second surface of the distribution layer of the package portion are electrically connected to the internal conductors. | 04-23-2009 |
| 20090102047 | Flip chip package structure and carrier thereof - A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps. | 04-23-2009 |
| 20090096077 | Tenon-and-mortise packaging structure - A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier. | 04-16-2009 |
| 20090091041 | STACKED TYPE CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A stacked type chip package structure including a package structure, a corresponding substrate, and a number of second bumps is provided. The package structure includes a first chip, a second chip, a number of first bumps, and a first underfill. The first chip is disposed above the second chip. The first bumps are disposed between the first chip and the second chip for electrically connecting the first chip and the second chip. The first underfill is used to fill between the first chip and the second chip and encapsulates the first bumps. The package structure is disposed above the corresponding substrate in a reverse manner, such that the first chip is disposed between the second chip and the corresponding substrate. The second bumps are disposed between the second chip and the corresponding substrate, such that the second chip is electrically connected to the corresponding substrate through the second bumps. | 04-09-2009 |
| 20090091036 | Wafer structure with a buffer layer - A wafer structure with a buffer layer is provided. The wafer structure comprises a wafer which has at least one pad formed thereon, a passivation layer formed on the wafer for partially exposing the at least one pad, a buffer layer formed on the passivation layer and the pad, and an under bump metallurgy (UBM) formed on the buffer layer. The buffer layer comprises a thickness-increased inner buffering member made from aluminum and located between the UBM and the pad to enhance the shock-absorbing ability of the wafer in a drop test to avoid the conductive bump bonded to a substrate coming off or cracking. The invention can also enhance the bonding between the conductive bump and the UBM. The buffer layer may further comprise an outer buffering member made of polyimide, coated on the passivation layer and partially arranged between the UBM and the passivation layer. | 04-09-2009 |
| 20090091015 | STACKED-TYPE CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks. | 04-09-2009 |
| 20090087947 | FLIP CHIP PACKAGE PROCESS - A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids. | 04-02-2009 |
| 20090079045 | Package structure and manufacturing method thereof - A quad-flat non-leaded (QFN) multichip package and a multichip package are provided. The QFN multichip package includes a lead frame, a first chip, a second chip and a molding compound. The lead frame has a plurality of first leads and second leads alternately arranged with each other. Each first lead includes a first connection portion and a first contact portion. Each second lead includes a second connection portion, a bending part and a second contact portion. The bending part is bent upward such that an interval is formed between the second contact portion and the first contact portion. The first chip is disposed between the first leads and the second leads. The second chip is disposed above the first chip. The molding compound encloses the first chip, the second chip, the first leads and the second leads, and further exposes the lower surfaces of the first and the second leads. | 03-26-2009 |
| 20090079044 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive part is not electrically connected to the second conductive part, and the second conductive part is electrically connected to the third conductive part. The chip is electrically connected to the first conductive part. The encapsulation encapsulates the chip and at least a portion of the lead frame, and forms a first surface and a second surface opposite to the first surface. The first conductive part and the third conductive part are exposed from the first surface, and the second conductive part is exposed from the second surface. | 03-26-2009 |
| 20090075027 | MANUFACTURING PROCESS AND STRUCTURE OF A THERMALLY ENHANCED PACKAGE - A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate. | 03-19-2009 |
| 20090065953 | Chip module and a fabrication method thereof - A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first glue structure is filled between the passive units so that an encircled area is defined by the first glue structure and the passive units. Then, a second glue structure is filled in the encircled area so that the chip is covered by the second glue structure. | 03-12-2009 |
| 20090065911 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a carrier, at least one chip, an encapsulation, and a patterned conductive film. The carrier has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the carrier and electrically connected to the carrier. The encapsulation encapsulates the chip and at least a portion of the first surface of the carrier. The patterned conductive film is disposed on the encapsulation to electrically connect to the carrier. A manufacturing method of the semiconductor package is also disclosed. | 03-12-2009 |
| 20090061614 | METHOD FOR FORMING BUMPS ON UNDER BUMP METALLURGY - A method for forming a bump on under bump metallurgy according to the present invention is provided. A bonding pad is first formed on the active surface of a wafer. Subsequently, a passivation layer is formed on the active surface of the wafer and exposes the bonding pad. An under bump metallurgy is formed on the bonding pad. A layer of film is formed on the passivation layer and overlays the under bump metallurgy. Afterward, the portion of the film on the under bump metallurgy is exposed to a UV light and the exposed portion of the film is removed to expose the under bump metallurgy. A solder paste is applied to the under bump metallurgy and the remaining film on the wafer is removed. Finally, the solder paste is reflowed to form a spherical bump. | 03-05-2009 |
| 20090051048 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure. | 02-26-2009 |
| 20090051031 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure comprises a carrier, a chip, at least one wire, a molding compound, at least one first solder ball and at least one second solder ball. The carrier has a chip chamber passing through the first surface and the second surface. The chip is disposed in the chip chamber, and an active surface of the chip is coplanar with the first surface. During packaging, the first surface and the active surface are both tightly pasted on a carrier tape to facilitate the subsequent wire bonding and sealing process. Afterwards, the carrier tape is removed for exposing the active surface and the first surface, and the active surface of the chip is coplanar with the first surface of the carrier, hence simplifying the packaging process and reducing the thickness of the package structure. | 02-26-2009 |
| 20090047782 | METHOD FOR MANUFACTURING A DEVICE HAVING A HIGH ASPECT RATIO VIA - Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched. | 02-19-2009 |
| 20090045491 | SEMICONDUCTOR PACKAGE STRUCTURE AND LEADFRAME THEREOF - A semiconductor package structure including a chip and a leadframe unit is provided. The chip has an active surface and a plurality of recesses disposed thereon. The leadframe unit has at least one packaging area in which the chip is disposed. The packaging area has a plurality of leads on the peripheral portion thereof, wherein each of the leads has a first end fastened on the peripheral portion of the packaging area and a second end extending inward to the active surface of the chip. The leads have a plurality of protrusions, which are capable of being contained by the recesses, located on the second ends to electrically connect the chip and the leadframe unit. | 02-19-2009 |
| 20090042367 | SAWING METHOD FOR A SEMICONDUCTOR ELEMENT WITH A MICROELECTROMECHANICAL SYSTEM - The present invention relates to a sawing method for a Micro Electro-Mechanical Systems (MEMS) semiconductor device. A gum material is disposed between a wafer having at least one MEMS and a carrier, and the gum material is disposed around the MEMS. The wafer is sawed according to the position correspondingly above the gum material. Finally, the carrier and the gum material are removed. By disposing the gum material between the carrier and the wafer, the MEMS are protected, and the wafer and the MEMS can avoid the pollution of water and foreign material, so that the yield can be improved. Furthermore, the wafer is sawed from the backside till the gum material without sawing through the gum material, so that the carrier is not sawed. Therefore, the carrier can be reused, such that the cost is reduced. | 02-12-2009 |
| 20090039526 | PACKAGE AND THE METHOD FOR MAKING THE SAME, AND A STACKED PACKAGE - The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement. | 02-12-2009 |
| 20090039521 | Semiconductor structure and semiconductor manufacturing method - A semiconductor structure comprising a first signal layer, a second signal layer, a wiring layer and at least one via is provided. The wiring layer is formed between the first signal layer and the second signal layer. A conducting wire is disposed between a first terminal and a second terminal on the wiring layer. At least one via is used to conduct the first signal layer and the second signal layer. The at least one via is disposed adjacent to the first terminal and the second terminal. | 02-12-2009 |
| 20090039483 | HEAT SLUG AND SEMICONDUCTOR PACKAGE - A heat slug includes a heat spreading member and a supporting member. The supporting member extends outwardly from the edge of the heat spreading member. The tips of the supporting member are formed with a plurality of contact portions, wherein each said contact portion has a bottom face inclined to the surface of the chip carrier at an angle of more than 5 degrees. The present invention further provides a semiconductor package. | 02-12-2009 |
| 20090035932 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even. | 02-05-2009 |
| 20090035931 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, comprising the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a photo resist layer on the first surface of the substrate; (c) forming a pattern on the photo resist layer; (d) forming a groove and a pillar in the substrate according to the pattern, wherein the groove surrounds the pillar; (e) forming a polymer in the groove of the substrate; (f) removing the pillar of the substrate to form an accommodating space; (g) forming a conductive metal in the accommodating space; and (h) removing part of the second surface of the substrate to expose the conductive metal and the polymer. As a result, thicker polymer can be formed in the groove, and the thickness of the polymer in the groove is uniform. | 02-05-2009 |
| 20090035895 | CHIP PACKAGE AND CHIP PACKAGING PROCESS THEREOF - A chip package comprises a substrate, a chip, a conductive layer and a molding compound. The substrate has a carrying surface and at least a ground pad disposed on the carrying surface. The chip has an active surface and a back surface opposite thereto. The chip is bonded to the substrate with the active surface facing towards the carrying surface of the substrate, wherein the ground pad is disposed outside of the chip. The conductive layer covers the chip and a portion of the carrying surface, and electrically connects to the ground pad. The molding compound is disposed on the carrying surface of the substrate and encapsulates the chip and the conductive layer. | 02-05-2009 |
| 20090034680 | CTS AND INSPECTING METHOD THEREOF - A substrate for inspecting a thickness of contacts at least includes a dielectric layer, a first metal layer, and a second metal layer. The first metal layer which includes a circuit region and a testing region is formed on an upper surface of the dielectric layer, and the circuit region has a plurality of contacts. The second metal layer which has a hollowed region is formed on a lower surface of the dielectric layer, and the hollowed region is aligned with the testing region of the first metal layer to avoid the interference when the testing region is inspected. | 02-05-2009 |
| 20090025964 | CIRCUIT SUBSTRATE AND METHOD FOR FABRICATING INDUCTIVE CIRCUIT - A circuit substrate including a laminated layer, an embedded electronic device, at least a circuit structure, and a solder mask layer is provided. The embedded electronic device is disposed within the laminated layer. The circuit structure is disposed on a surface of the laminated layer and is connected between a reference plane and the embedded electronic device. In addition, the solder mask layer is disposed on the surface of the laminated layer and exposes a portion of the circuit structure. The circuit structure has a specific layout by which a circuit trace with an adjustable length can be formed by disconnecting or connecting the exposed portion of the circuit structure. | 01-29-2009 |
| 20090019692 | METHOD OF CUTTING SIGNAL WIRE PRESERVED ON CIRCUIT BOARD AND CIRCUIT LAYOUT THEREOF - A method of cutting signal wire preserved on circuit board applicable to a circuit layout is provided to reduce signal return loss induced by the preserved wires. The circuit layout has a plurality of preserved wires and a common contact electrically connected to the preserved wires. The cutting method is performed by cutting off one of the preserved wires and disconnecting a break part of the wire from the common contact. | 01-22-2009 |
| 20080308938 | Under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure - An under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure are provided. The under bump metallurgy structure includes an adhesion layer, a barrier layer and a wetting layer. The adhesion layer is disposed on a bonding pad of a wafer. The barrier layer is disposed on the adhesion layer. The wetting layer is disposed on the barrier layer. The adhesion layer, the barrier layer and the wetting layer are respectively made of nickel with boron, cobalt and gold. | 12-18-2008 |
| 20080308912 | EMI SHIELDED SEMICONDUCTOR PACKAGE - An EMI shielded semiconductor package is provided. The package includes a substrate and a chip disposed on the substrate. The chip is electrically connected to the substrate by a plurality of bonding wires. At least one shielding conductive block is formed on the substrate and electrically connected to the ground trace of the substrate. A sealant is formed on the substrate and covers the chip, bonding wires and the shielding conductive block. The sealant has a side surface to expose a surface of the shielding conductive block. A layer of conductive film is formed on the outer surface of the sealant and covers the exposed surface of the shielding conductive block thereby shielding the chip from electromagnetic interference. | 12-18-2008 |
| 20080303167 | DEVICE HAVING HIGH ASPECT-RATIO VIA STRUCTURE IN LOW-DIELECTRIC MATERIAL AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar. | 12-11-2008 |
| 20080303146 | PROCESS FOR MANUFACTURING SUBSTRATE WITH BUMPS AND SUBSTRATE STRUCTURE - A process for manufacturing a substrate with bumps is provided. First, a metallic substrate having a body and a plurality of conductive elements is provided. Next, a first dielectric layer is formed on the body, and the conductive elements are covered by the first dielectric layer. Then, a plurality of circuits and a plurality of contacts are formed on a surface of the first dielectric layer, and the contacts are electrically connected to the conductive elements. Next, a second dielectric layer is formed on the surface of the first dielectric layer, and the circuits are covered by the second dielectric layer. Finally, the body is patterned to form a plurality of bumps, and the bumps are electrically connected to the contacts by the conductive elements. The bumps are formed by etching the body, so the connection reliability between bumps and conductive elements is desirable, and the manufacturing cost is reduced. | 12-11-2008 |
| 20080303128 | LEADFRAME WITH DIE PAD AND LEADS CORRESPONDING THERETO - A leadframe includes a die pad and a plurality of leads corresponding to the die pad. The die pad for supporting a die is formed with a plurality of sides, each of the sides having at least one recess portion and at least one protrusion portion. The leads are substantially coplanar to the die pad. The leads include a plurality of first leads and a plurality of second leads. The first leads extend into the recess portions respectively, and the second leads are aligned with the protrusion portions. The length of the first leads is greater than that of the second leads. The length of wires electrically connecting the die to the leads or the die pad can be adjusted by the sides of the leadframe with the recess portion and the protrusion portion having a dimension corresponding to the leads, so as to save the manufacture cost of the leadframe. | 12-11-2008 |
| 20080303126 | MICROELECTROMECHANICAL SYSTEM PACKAGE AND THE METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a microelectromechanical system package is provided. A plurality of cavities is first formed on a surface of a silicon wafer. The surface of the silicon wafer is then bonded to the microelectromechanical system wafer in such a manner that the active areas of the chips on the microelectromechanical system wafer are corresponding to the cavities on the silicon wafer. The structure assembly of the two wafers is finally singulated to form individual microelectromechanical system chips whose active areas are covered by the cavities. In this way, the profile of the microelectromechanical system package may be reduced accordingly. | 12-11-2008 |
| 20080303106 | IMAGE SENSOR PACKAGE AND PACKAGING METHOD FOR THE SAME - An image sensor package includes a substrate, a sensor chip, a frame, a lens element and at least a pair of guide pins. The sensor chip is mounted on the substrate, and has two opposite sides and a sensing region, which has a sensing region central axis. The frame is mounted on the substrate, and has an aperture and an inner space with the sensor chip disposed therein. The lens element is disposed inside the aperture and has a lens central axis. The guide pins locate oppositely inside the inner space of the frame with an interval between the tips of the guide pins substantially identical to the distance between the opposite sides of the sensor chip, wherein the central line of the interval between the tips of the guide pins defines a positioning line, which substantially coincides with the lens central axis; wherein the tip of each guide pin is aligned with one of the opposite sides of the sensor chip such that the positioning line is substantially coincided with the sensing region central axis. | 12-11-2008 |
| 20080299757 | Wafer structure and method for fabricating the same - A wafer structure and a method for fabricating the same are provided. First, a wafer having a pad and a first protection layer with a first opening is provided. Next, a second protection layer with a second opening is formed on the first protection layer. Part of the pad and the first protection layer are exposed from the openings. The edges of the openings construct a step structure. Following that, an adhesion layer is formed on the pad, the step structure and the second protection layer. Afterwards, a photo-resist layer with a third opening is formed on the adhesion layer. Then, a barrier layer is electroplated onto part of the adhesion layer. Further, a wetting layer is formed on the barrier layer, and then the photo-resist layer and part of the adhesion layer exposed outside the barrier layer are removed. Finally, a solder layer is printed onto the wetting layer. | 12-04-2008 |
| 20080290489 | Package structure and electronic device using the same - A package structure and an electronic device using the same are provided. The package structure includes a chip module and a cover. The chip module covered by the cover is used for receiving a first signal. The chip module includes a substrate, a heat sink and a first chip. The substrate has a first surface, a second surface and an opening. The first surface is opposite to the second surface. The opening penetrates the first surface and the second surface. The heat sink is disposed on the first surface of the substrate and covers the opening. The first chip is disposed on the heat sink and is positioned inside the opening. A bottom surface of the first chip flatly contacts the heat sink. The cover has a window element. The first signal passes through the window element to contact with the chip module. | 11-27-2008 |
| 20080283984 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a leadframe, a die, a solder layer and several connecting components. The leadframe includes a heat dissipation pad and several leads. The heat dissipation pad is disposed in a substantial center of the leadframe. The leads are surrounding the heat dissipation pad. The die having an active surface is disposed on the leadframe. The solder layer is disposed between the active surface and the heat dissipation pad. The connecting components are disposed between the active surface and the leads. The die is electrically connected to the leadframe through the solder layer and the connecting components. | 11-20-2008 |
| 20080272486 | CHIP PACKAGE STRUCTURE - A chip package structure includes a carrier, an interposer, a plurality of electrically conductive elements, a first sealant, a chip, and a second sealant. The interposer is disposed on the carrier. The electrically conductive elements electrically connect the interposer and the carrier. The first sealant seals the electrically conductive elements. A plurality of bumps of the chip is connected to the interposer. The second sealant seals the bumps. A first glass transition temperature of the first sealant is higher than a second glass transition temperature of the second sealant. Since glass transition temperatures of the first sealant and the second sealant are different, and the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant, the inner stress will be lowered and the yield is promoted. | 11-06-2008 |
| 20080271915 | METHOD FOR MAKING A CIRCUIT BOARD AND MULTI-LAYER SUBSTRATE WITH PLATED THROUGH HOLES - A method for making a circuit board includes the following steps. At least two substrates are provided, wherein each substrate includes two surfaces, two circuit layers respective formed on the two surfaces and at least a via passing through the two surfaces. A metal layer is formed on the side wall of the via, wherein the metal layer electrically connects two circuit layers on the two surfaces of each substrate to each other. An insulating film is at least formed on the surface of the metal layer by an electrophoretic deposition process. Vias of two substrates are aligned with each other and two substrates are laminated to each other, so as to form a multi-layer substrate. Another metal layer is formed on the insulating film, wherein each metal layer is an independent electrical channel. | 11-06-2008 |
| 20080261390 | METHOD FOR FORMING BUMPS ON UNDER BUMP METALLURGY - A method for forming metal bumps is provided. A bonding pad is first formed on the active surface of a chip and then a passivation layer is formed on the active surface of the chip and exposes the bonding pad. An under bump metallurgy is formed on the active surface of the chip to overlay the bonding pad. A layer of patterned photoresist is formed on the under bump metallurgy and exposes the portion of the under bump metallurgy on the bonding pad. A layer of copper is plated on the exposed portion of the under bump metallurgy and then a layer of solder is printed on the copper layer. Afterward the solder is reflowed to form a spherical metal bump. Finally, the photoresist layer is removed and the exposed portion of the under bump metallurgy is etched out. | 10-23-2008 |
| 20080261351 | WAFER SAWING METHOD - A wafer sawing method for sawing a wafer by using a cutting tool is provided. Sawing paths are formed on a surface of the wafer. In the wafer sawing method, a carrier on which strip-shaped adhesives or at least a fiducial mark is formed is firstly provided. The dimension of the carrier is greater than the dimension of the wafer. Next, the surface of the wafer is bonded to the carrier, and the strip-shaped adhesives or the fiducial mark is extended or located outside a bonding region between the wafer and the carrier. Here, the surface of the wafer faces the carrier. The cutting tool and the carrier are positioned according to the strip-shaped adhesives or the fiducial mark outside the bonding region. The wafer is then sawed by using the cutting tool. The wafer sawing method provides a precise and rapid sawing process and achieves superior productive yield. | 10-23-2008 |
| 20080252300 | Detecting device - A detecting device for detecting the electrical connection between several first pads and second pads of a package substrate is provided. The first and the second pads are disposed on two opposite sides of the package substrate. The detecting device includes a socket unit, several first detecting components and several second detecting components. The socket unit is disposed on and coupled to the first pads. The first detecting components are disposed on and coupled to the socket unit. The second detecting components are disposed under and coupled to the second pads. The socket unit and the second detecting components are disposed on two opposite sides of the package substrate. While detecting, the first detecting components, the socket unit, the first pads, the second pads and the second detecting components are electrically connected sequentially, so as to determine whether the first pads are respectively and electrically connected to the second pads. | 10-16-2008 |
| 20080247149 | CHIP PACKAGE STRUCTURE - A chip package structure including a carrier, a chip, and an underfill layer is disclosed. The carrier has a number of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip. | 10-09-2008 |
| 20080232077 | CONVERSION SUBSTRATE FOR A LEADFRAME AND THE METHOD FOR MAKING THE SAME - The present invention relates to a conversion substrate for a leadframe and the method for making the same. The conversion substrate comprises a core layer, a first copper layer, a first metal plating layer and a first brown/black oxide layer. The first copper layer is on a first surface of the core layer, and has a plurality of discontinuous sections. The first metal plating layer is on the first copper layer, and has a plurality of discontinuous sections. The first brown/black oxide layer is on the first copper layer, so as to protect the first copper layer. Thus, the polymeric solder mask is not used in the conversion substrate of the present invention, so that the metal plating layer will not be polluted, and the yield rate can be raised. | 09-25-2008 |
| 20080230895 | SEMICONDUCTOR PACKAGE AND THE METHOD FOR MANUFACTURING THE SAME - A method for manufacturing semiconductor packages is provided. The upper surface of a substrate has a plurality of slots and surface mount devices are positioned across the slots. In this circumstance, the space below the surface mount devices can be filled up with sealant as a result of the arrangement of the slots. This can avoid the occurrence of the melted solders to bridge to each other and of the tomb stone effect of the surface mount devices. | 09-25-2008 |
| 20080230887 | SEMICONDUCTOR PACKAGE AND THE METHOD OF MAKING THE SAME - The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased. | 09-25-2008 |
| 20080230885 | CHIP HERMETIC PACKAGE DEVICE AND METHOD FOR PRODUCING THE SAME - A chip hermetic package device includes a substrate, a chip, a hermetic lid, a hermetic material and a post. The height of the post is larger than the thickness of the hermetic material. A method for producing a chip hermetic package includes the steps of: mounting the chip on the substrate; disposing the post and the hermetic material between the substrate and the hermetic lid; disposing the hermetic lid on the substrate to form a chamber, the post supporting the hermetic lid on the substrate to form an air passage; and performing a sealing step in an atmosphere of inert gas. The present invention utilizes the post to form the air passage between the substrate and the hermetic lid. Therefore, only is the sealing step performed in the atmosphere of nitrogen, and present invention needs a reduced number of equipment. Therefore, the present invention has a low cost, simplifies the packaging process and improves efficiency. | 09-25-2008 |
| 20080230587 | METHOD FOR MANUFACTURING ELECTRIC CONNECTIONS IN WAFER - A method for manufacturing electrical connections in wafer is provided. A plurality of openings is formed on the upper surface of a wafer by dry etching or laser drilling and then solder paste is applied to the openings. Next, the wafer is positioned in a vacuum environment and is heated to soften the solder paste. Subsequently, the vacuum is suddenly broken to have the pressure upon the upper surface of the wafer greater than that in the openings thereby pressing the molten solder paste into the openings. | 09-25-2008 |
| 20080224294 | MULTI-CHIP PACKAGE WITH A SINGLE DIE PAD - A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage. | 09-18-2008 |
| 20080218981 | PACKAGE STRUCTURE FOR CONNECTION WITH OUTPUT/INPUT MODULE - A package structure for connection with an output/input module is disclosed. The package structure can be applied to conventional multi-chip packages and system in packages. The package structure defines at least one insertion cavity that is vertically or horizontally disposed. By simply inserting an output/input module into the insertion cavity, an electrical connection can be established between the output/input module and the package structure. Accordingly, the package structure thus constructed can address the repairing, replacement and upgrading problems of electronic components encountered by a package structure that adopts the conventional soldering connection method. | 09-11-2008 |
| 20080217758 | PACKAGE SUBSTRATE STRIP, METAL SURFACE TREATMENT METHOD THEREOF AND CHIP PACKAGE STRUCTURE - A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer. By original plating bars and the reserved plating bar, an anti-oxidation layer can be simultaneously formed on finger contacts, first ball pads electrically connected to the finger contacts, and second ball pads electrically connected to the bonding pads. The package substrate strip and the method for metal surface treatment thereof can simplify manufacturing process, reduce production cost, and improve production efficiency and yield. Furthermore, a chip package applying the package substrate strip is also provided. | 09-11-2008 |
| 20080211107 | Via hole structure and manufacturing method thereof - A via hole structure and a manufacturing method thereof are provided. The via hole structure is disposed on a substrate. The substrate has a through hole, which passes through the substrate from a top surface to a bottom surface. The via hole structure comprises a conductive layer, several first conductive lines and several second conductive lines. The conductive layer having several conductive sections is disposed on the inner wall of the through hole. The first conductive lines are adjacent to the top surface for connecting the top ends of the conductive sections. The second conductive lines are adjacent to the bottom surface for connecting the bottom ends of the conductive sections. The conductive sections, the first conductive lines and the second conductive lines are serially connected to form a three-dimension layout. | 09-04-2008 |
