| Advanced Micro Devices, Inc. Patent applications |
| Patent application number | Title | Published |
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| 20120131399 | APPARATUS AND METHODS FOR TESTING MEMORY CELLS - Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array. | 05-24-2012 |
| 20120131279 | MEMORY ELEMENTS FOR PERFORMING AN ALLOCATION OPERATION AND RELATED METHODS - Apparatus for memory elements and related methods for performing an allocate operation are provided. An exemplary memory element includes a plurality of way memory elements and a replacement module coupled to the plurality of way memory elements. Each way memory element is configured to selectively output data bits maintained at an input address. The replacement module is configured to enable output of the data bits maintained at the input address of a way memory element of the plurality of way memory elements for replacement in response to an allocate instruction including the input address. | 05-24-2012 |
| 20120127805 | MEMORY ELEMENTS HAVING SHARED SELECTION SIGNALS - Apparatus are provided for memory elements and related computing modules. An exemplary memory element includes a first array of one or more memory cells, a second array of one or more memory cells, write selection circuitry associated with the first array, and read selection circuitry associated with the second array. The write selection circuitry and the read selection circuitry are configured to be activated concurrently. | 05-24-2012 |
| 20120126871 | METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT - A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode. | 05-24-2012 |
| 20120124349 | POWER EFFICIENT PATTERN HISTORY TABLE FETCH IN BRANCH PREDICTOR - A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a queue. If a branch prediction is requested, the queue is accessed to obtain a prediction value. The queue may include any number of entries and the queue maintains the oldest prediction value at the head of the queue. The prediction value at the head of the queue is used when a branch prediction is needed. | 05-17-2012 |
| 20120124344 | LOOP PREDICTOR AND METHOD FOR INSTRUCTION FETCHING USING A LOOP PREDICTOR - A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in program execution is that a set of branches repeat over and over forming a loop. The loop may be detected based on a repeated pattern of access to a data structure used for branch prediction. Once a loop is detected and it may be determined whether the codes would stay in the loop for at least a duration sufficient to disable the branch prediction. On a determination that the detected loop is locked, a sequence of instruction addresses in one iteration of the detected loop may be captured in a buffer and the branch predictor may be turned off and a sequence of fetch instructions may be played from the buffer. | 05-17-2012 |
| 20120119792 | ADJUSTABLE FINITE IMPULSE RESPONSE TRANSMITTER - Apparatus and methods are provided for generating output signals representative of bits of serial data. A transmitter includes driver circuitry configured to generate an output signal at an output node and an allocation control module coupled to the driver circuitry. The driver circuitry includes a plurality of driver legs configured to generate the output signal based on a plurality of data bits. The allocation control module is configured to allocate a respective subset of the plurality of driver legs to a respective data bit of a plurality of data bits, wherein the each subset generates a component of the output signal that is influenced by its respective data bit. | 05-17-2012 |
| 20120119767 | POWER CYCLING TEST ARRANGEMENT - A device instructs a power supply to provide a current to a power cycling test structure that includes a heat source interconnected with a package, via a first level interconnect mechanism, and a printed circuit board (PCB) interconnected with the package, via a second level interconnect mechanism. The device also monitors thermal feedback associated with the heat source, and monitors, based on the provided current, voltage feedback associated with the power cycling test structure. The device further determines a thermal profile of the power cycling test structure based on the thermal feedback and the voltage feedback. | 05-17-2012 |
| 20120117420 | PROCESSOR AND METHOD IMPLEMENTED BY A PROCESSOR TO IMPLEMENT MASK LOAD AND STORE INSTRUCTIONS - A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits. | 05-10-2012 |
| 20120117330 | METHOD AND APPARATUS FOR SELECTIVELY BYPASSING A CACHE FOR TRACE COLLECTION IN A PROCESSOR - A method and apparatus for a selectively bypassing a cache in a processor of a computing device are disclosed. | 05-10-2012 |
| 20120110594 | LOAD BALANCING WHEN ASSIGNING OPERATIONS IN A PROCESSOR - A method and apparatus for assigning operations in a processor are provided. An incoming instruction is received. The incoming instruction is capable of being processed: only by a first processing unit (PU), only by a second PU or by either first and second PUs. The processing of first and second PUs is load balanced by assigning the received instructions capable of being processed by either the first and the second PUs based on a metric representing differential loads placed on the first and the second PUs. | 05-03-2012 |
| 20120110309 | Data Output Transfer To Memory - Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a memory includes: forming, based upon one or more of the outputs, a combined memory export instruction comprising one or more data elements and one or more control elements; and sending the combined memory export instruction to the memory. The combined memory export instruction can be sent to memory in a single clock cycle. Another method includes: forming, based upon outputs from two or more of the threads, a memory export instruction comprising two or more data elements; embedding at least one address representative of the two or more of the outputs in a second memory instruction; and sending the memory export instruction and the second memory instruction to the memory. | 05-03-2012 |
| 20120110256 | LOW POWER CONTENT-ADDRESSABLE MEMORY AND METHOD - Content-Addressable Memory (CAM) arrays and related circuitry for integrated circuits and CAM array comparison methods are provided such that relatively low power is used in the operation of the CAM circuitry. A binary value pair is stored in a pair of CAM memory elements. A comparison signal is provided to comparator circuitry that uniquely represents the stored binary values. A match signal is input to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair. In one example, a transistor is operated to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair. In that example, no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs. | 05-03-2012 |
| 20120102507 | STREAMING PROGRAMMING GENERATOR - A device receives input that includes definitions of components of a computational pipeline, where the components include one or more buffers, one or more kernels, and one or more stages within a control graph. The device generates, based on the input, kernel signatures for a graphics processor, where the kernel signatures compile into an executable streaming program for the computational pipeline. The device also generates, based on the input, host-side runtime code to execute the streaming program. | 04-26-2012 |
| 20120102376 | METHODS AND APPARATUS TO TEST MULTI CLOCK DOMAIN DATA PATHS WITH A SHARED CAPTURE CLOCK SIGNAL - Methods, circuits and systems are provided to test data paths that traverse multiple clock domains using a common capture clock that is applied to multiple domains. Test data is launched to a first clock domain, and each of the clock domains is selected to receive the common capture clock signal while the test data propagates through the selected clock domain. The test data is capture after it has propagated through each of the multiple domains in response to the shared domains. Applying a common capture clock to each of the different domains eliminates hold time errors that might otherwise occur as the data transitions from one clock domain to another. | 04-26-2012 |
| 20120102357 | METHOD AND APPARATUS FOR PROCESSING LOAD INSTRUCTIONS IN A MICROPROCESSOR HAVING AN ENHANCED INSTRUCTION DECODER AND AN ENHANCED LOAD STORE UNIT - A method and microprocessor are described for efficiently executing load instructions out-of-order (speculatively). The microprocessor includes an enhanced load store unit (LSU) and an enhanced instruction decoder. The enhanced LSU receives a plurality of out-of-order value addresses, and sends a resync signal to the enhanced instruction decoder when an execution error associated with a particular load instruction occurs. The enhanced instruction decoder stores a specific address associated with the particular load instruction, and increments a counter value that indicates how many times the resync signal was sent by the resync predictor. When the counter value reaches a predetermined threshold, subsequent load instructions from the specific address are executed in order (non-speculatively). When a future execution of the particular load instruction indicates that the probability of an execution error has been reduced, the counter value is decremented, facilitating newer load instructions associated with the same address to again be executed speculatively. | 04-26-2012 |
| 20120102333 | METHOD AND APPARATUS FOR INCLUDING ARCHITECTURE FOR PROTECTING MULTI-USER SENSITIVE CODE AND DATA - A secure execution environment for execution of sensitive code and data including a secure asset management unit (SAMU) is described. The SAMU provides a secure execution environment to run multiple instances of separate program code or data code associated with copy protection schemes established for content consumption. The SAMU architecture allows for hardware-based secure boot and memory protection and provides on-demand code execution for multiple instances of separate program code or data provided by a host processor. The SAMU may boot from an encrypted and signed kernel code, and execute encrypted, signed code. The hardware-based security configuration facilitates the prevention of vertical or horizontal privilege violations. | 04-26-2012 |
| 20120102307 | METHOD AND APPARATUS INCLUDING ARCHITECTURE FOR PROTECTING SENSITIVE CODE AND DATA - A secure execution environment for execution of sensitive code and data including a secure asset management unit (SAMU) is described. The SAMU provides a secure execution environment to run sensitive code, for example, code associated with copy protection schemes established for content consumption. The SAMU architecture allows for hardware-based secure boot and memory protection and provides on-demand code execution for code provided by a host processor. The SAMU may boot from an encrypted and signed kernel code, and execute encrypted, signed code. The hardware-based security configuration facilitates preventing vertical or horizontal privilege violations. | 04-26-2012 |
| 20120091558 | SHIELD-MODULATED TUNABLE INDUCTOR DEVICE - A semiconductor device is presented here. The semiconductor device includes an integrated inductor formed on a semiconductor substrate, a transistor arrangement formed on the semiconductor substrate to modulate loop current induced by the integrated inductor, dielectric material to insulate the integrated inductor from the transistor arrangement, and a controller coupled to the transistor arrangement. The controller is used to select conductive and nonconductive operating states of the transistor arrangement. A conductive operating state of the transistor arrangement allows formation of induced loop current in the transistor arrangement, and a nonconductive operating state of the transistor arrangement inhibits formation of induced loop current in the transistor arrangement. | 04-19-2012 |
| 20120086494 | RECEIVER CIRCUITRY AND RELATED CALIBRATION METHODS - Apparatus and methods are provided for calibrating and operating a receiver circuit. An exemplary method comprises the steps of applying a first voltage offset to a first input of an amplifier circuit, generating an output signal at an output of the amplifier circuit based on the first voltage offset and a second voltage offset at a second input of the amplifier circuit, adjusting the second voltage offset based on the output signal, and maintaining the second voltage offset at a constant voltage when the output signal is indicative of the second voltage offset cancelling the first voltage offset. | 04-12-2012 |
| 20120086482 | VOLTAGE-CONTROLLED OSCILLATOR MODULE HAVING ADJUSTABLE OSCILLATOR GAIN AND RELATED OPERATING METHODS - Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency. | 04-12-2012 |
| 20120079491 | THREAD CRITICALITY PREDICTOR - Each thread of a multi-threaded application is assigned a ranking, referred to as thread criticality, based on the amount of time the thread is expected to take to complete one or more operations associated with the thread. More resources are assigned to threads having a higher thread criticality, in order to increase the rate at which the thread completes its operations. Thread criticality is determined using a perceptron model, whereby the thread criticality for a thread is a weighted sum of a set of data processing device performance characteristics associated with the thread, such as the number of instruction cache misses and data cache misses experienced by the thread. The weights of the perceptron model can be repeatedly adjusted over time based on repeated measurements that indicate the relative speed with which each thread is completing its operations. | 03-29-2012 |
| 20120076207 | MULTIPLE-CANDIDATE MOTION ESTIMATION WITH ADVANCED SPATIAL FILTERING OF DIFFERENTIAL MOTION VECTORS - A system and method of performing motion estimation in a video encoder is enclosed. The system and method include calculating one or more candidate motion vectors for each macroblock of a video image to form a list of candidate motion vectors, calculating a second one or more candidate motion vectors using a sub-region of at least one macroblock of the video image to include in the list of candidate motion vectors, and comparing the calculated candidate motion vectors of a first macroblock with the calculated candidate motion vectors of at least one sub-region of the first macroblock to provide the estimated contribution to the candidate motion vector of the macroblock. The calculating a second one or more candidate motion vectors using a sub-region of at least one macroblock may include using an approximation different from the calculating one or more candidate motion vectors for each macroblock. | 03-29-2012 |
| 20120072789 | MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY CONFIGURED TO FACILITATE PRODUCTION OF PRE-STRESSED INTEGRATED CIRCUITS AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. | 03-22-2012 |
| 20120072788 | INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. | 03-22-2012 |
| 20120066471 | ALLOCATION OF MEMORY BUFFERS BASED ON PREFERRED MEMORY PERFORMANCE - A method and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method and apparatus associates one or more memory buffers with a plurality of memory banks based on preferred performance settings, wherein the plurality of memory banks spans over one or more of the plurality of memory channels. Additionally, the method and apparatus accesses the one or more memory buffers based on the preferred performance settings. Further, the method and apparatus can, in response to accessing the one or more memory buffers based on the preferred performance settings, determine whether the preferred performance settings are being satisfied. | 03-15-2012 |
| 20120066445 | DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES - A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers. | 03-15-2012 |
| 20120066444 | Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation - A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers. | 03-15-2012 |
| 20120059866 | METHOD AND APPARATUS FOR PERFORMING FLOATING-POINT DIVISION - A method and apparatus provides for performing floating-point division using input check/output correction floating-point division logic and a floating-point division fix-up instruction (e.g., an instruction, command, signal or other indicator). In one example, the apparatus includes a processor having a floating-point arithmetic logic unit (ALU) that includes the input check/output correction floating-point division logic. The input check/output correction floating-point division logic is responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to examine a first input representing a numerator and a second input representing a denominator to determine whether a special case of floating-point division occurs. The floating-point division fix-up instruction also causes the input check/output correction floating-point division logic to provide an output representing a floating-point division result based on the determined special case of floating-point division and a third input representing a candidate quotient. | 03-08-2012 |
| 20120056653 | DIGITAL PHASE-LOCKED LOOP - Apparatus, systems and methods are provided for digital phase-locked loops. A digital phase-locked loop comprises an oscillator module configured to generate an output signal and a phase detection module coupled to the oscillator module. The phase detection module is configured to signal the oscillator module to adjust a frequency of the output signal by a first amount when a phase difference between a reference signal and the output signal is less than a threshold amount, and signal the oscillator module to adjust the frequency by a greater amount when the phase difference is greater than the threshold amount. | 03-08-2012 |
| 20120042127 | CACHE PARTITIONING - A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit. | 02-16-2012 |
| 20120042104 | ADJUSTABLE FINITE IMPULSE RESPONSE TRANSMITTER - Apparatus and methods are provided for generating output signals representative of bits of serial data. A transmitter comprises a plurality of delay elements, driver circuitry, and bypass logic coupled between the plurality of delay elements and the driver circuitry. The plurality of delay elements delay serialized data, resulting in delayed serialized data, and the driver circuitry generates an output signal representative of a first bit of the delayed serialized data. The bypass logic is configured to selectively bypass one or more delay elements of the plurality of delay elements to provide the first bit of the delayed serialized data to the driver circuitry. | 02-16-2012 |
| 20120038835 | STAND-BY MODE TRANSITIONING - A device for rapidly instituting an active mode of a digital-television enabled system, the system including a first, volatile memory configured to load and store software instructions, includes: an input configured to receive first digital audio and video information; a first output configured to convey second audio and information toward a display regarding the first audio and video information; at least one second output configured to convey commands to, and receive information from, the first memory; and a processor configured to perform functions in accordance with software instructions stored in first and second memories and to cause the first memory to load software instructions for provision to the processor such that first instructions for processing at least one of the first audio information and the first video information are loaded and stored by the first memory with a higher priority than second instructions for performing other functionality. | 02-16-2012 |
| 20120038051 | BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME - A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect. | 02-16-2012 |
| 20120025316 | Process for Forming FINS for a FinFET Device - An integrated fin-based field effect transistor (FinFET) and method of fabricating such devices on a bulk wafer with EPI-defined fin heights over shallow trench isolation (STI) regions. The FinFET channels overlie the STI regions within the semiconductor bulk, while the fins extend beyond the STI regions into the source and drain regions which are implanted within the semiconductor bulk. With bulk source and drain regions, reduced external FinFET resistance is provided, and with the fins extending into the bulk source and drain regions, improved thermal properties is provided over conventional silicon on insulator (SOI) devices. | 02-02-2012 |
| 20120019542 | Method and System for Load Optimization for Power - A method for managing work distribution in a processor including a plurality of instruction data modules, is provided. The method includes analyzing work units received by the processor and comparing the utilization level in each active module within the plurality with a first predetermined threshold. The work units are distributed across selected ones of the modules within the plurality based upon the analyzing and the comparing. | 01-26-2012 |
| 20120019541 | Multi-Primitive System - Disclosed herein is a vertex core. The vertex core includes a grouper module configured to process two or more primitives during one clock period and two or more vertex translators configured to respectively receive the two or more processed primitives in parallel. | 01-26-2012 |
| 20120017118 | METHOD AND APPARATUS FOR TESTING AN INTEGRATED CIRCUIT INCLUDING AN I/O INTERFACE - Methods and apparatus provide for testing an integrated circuit including an input/output (I/O) interface. The method and apparatus place the I/O interface in a test mode by test enabling logic. During the test mode, the method and apparatus also provide, by a clock generator in the I/O interface, an internal phase-aligned receiver clock signal to a plurality of transceivers in the I/O interface. The clock generator is a transmitter portion of one of the plurality of transceivers in the I/O interface. The method and apparatus then monitor for errors in loopback data from the plurality of transceivers in the I/O interface by an automatic test equipment (ATE). The phase of the internal phase-aligned receiver clock signal is aligned with the loopback data of the plurality of transceivers, and the frequency of the internal phase-aligned receiver clock signal may be above about 200 MHz. | 01-19-2012 |
| 20120017062 | Data Processing Using On-Chip Memory In Multiple Processing Units - Methods are disclosed for improving data processing performance in a processor using on-chip local memory in multiple processing units. According to an embodiment, a method of processing data elements in a processor using a plurality of processing units, includes: launching, in each of the processing units, a first wavefront having a first type of thread followed by a second wavefront having a second type of thread, where the first wavefront reads as input a portion of the data elements from an off-chip shared memory and generates a first output; writing the first output to an on-chip local memory of the respective processing unit; and writing to the on-chip local memory a second output generated by the second wavefront, where input to the second wavefront comprises a first plurality of data elements from the first output. Corresponding system and computer program product embodiments are also disclosed. | 01-19-2012 |
| 20120013629 | Reading Compressed Anti-Aliased Images - Embodiments of the present invention enable the reduction of the memory bandwidth required for graphics rendering. According to an embodiment, a method to render a pixel from a compressed anti-aliased image includes: accessing metadata for the pixel, where the metadata includes entries for respective samples generated by multisampling the pixel; and retrieving a subset of said samples based upon the metadata, wherein the subset is stored in the compressed anti-aliased image stored in a memory. | 01-19-2012 |
| 20120013627 | DYNAMIC CONTROL OF SIMDs - Systems and methods to improve performance in a graphics processing unit are described herein. Embodiments achieve power saving in a graphics processing unit by dynamically activating/deactivating individual SIMDs in a shader complex that comprises multiple SIMD units. On-the-fly dynamic disabling and enabling of individual SIMDs provides flexibility in achieving a required performance and power level for a given processing application. Embodiments of the invention also achieve dynamic medium grain clock gating of SIMDs in a shader complex. Embodiments reduce switching power by shutting down clock trees to unused logic by providing a clock on demand mechanism. In this way, embodiments enhance clock gating to save more switching power for the duration of time when SIMDs are idle (or assigned no work). Embodiments can also save leakage power by power gating SIMDs for a duration when SIMDs are idle for an extended period of time. | 01-19-2012 |
| 20120013624 | Split Storage of Anti-Aliased Samples - Embodiments of the present invention are directed to improving the performance of anti-aliased image rendering. One embodiment is a method of rendering a pixel from an anti-aliased image. The method includes: storing a first set and a second set of samples from a plurality of anti-aliased samples of the pixel respectively in a first memory and a second memory; and rendering a determined number of said samples from one of only the first set or the first and second sets. Corresponding system and computer program product embodiments are also disclosed. | 01-19-2012 |
| 20120005459 | PROCESSOR HAVING INCREASED PERFORMANCE AND ENERGY SAVING VIA MOVE ELIMINATION - Methods and apparatuses are provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The apparatus comprises a first plurality of available physical registers mapped to a second plurality of logical registers, including a source logical register and a destination logical register. A renaming unit remaps the destination logical register to the same physical register mapping as the source logical register in response to a move instruction. In this way, the move instruction is effectively executed without moving data between physical registers. A method is provided for increasing processor performance and energy saving via eliminating physical data movement to accomplish a move instruction. The method comprises determining a mapping of a logical source register and a logical destination register to physical registers of a processor and then remapping the logical destination register to the same physical register mapping as the logical source register to affect an equivalent of the move instruction with actual data movement between physical registers. | 01-05-2012 |
| 20120005432 | Reducing Cache Probe Traffic Resulting From False Data Sharing - Disclosed herein are a processing unit and a multi-processing unit system that implement a cache-coherency method. Such a multi-processing unit system includes a main memory, a first processing unit, and a second processing unit. The first processing unit and the second processing unit are coupled to the main memory. The first processing unit includes a cache and logic. The cache is configured to store data from the main memory. The logic is configured to maintain an entry in a directory of the cache. The entry indicates whether either of the first processing unit and the second processing unit accesses a data object of a cache line for which the first processing unit is a home node. | 01-05-2012 |
| 20120001927 | INTEGRATED GRAPHICS PROCESSOR DATA COPY ELIMINATION METHOD AND APPARATUS WHEN USING SYSTEM MEMORY - A method and apparatus for processing data in a system comprising a central processing unit (CPU), a system memory, and a graphics processing unit (GPU) includes determining whether the GPU is an integrated graphics processor (IGP). Based upon a determination that the GPU is an IGP, data stored in the system memory is accessed by the GPU without copying the data to a memory on the GPU. Processing is performed on the data in the GPU. | 01-05-2012 |
| 20110302586 | MULTITHREAD APPLICATION-AWARE MEMORY SCHEDULING SCHEME FOR MULTI-CORE PROCESSORS - A device may include a memory controller that identifies a multithread application, and adjusts a memory scheduling scheme for the multithread application based on the identification of the multithread application. | 12-08-2011 |
| 20110292057 | Dynamic Bandwidth Determination and Processing Task Assignment for Video Data Processing - A method and apparatus for dynamic bandwidth determination and processing task assignment is disclosed. Embodiments include a video driver/interface that communicates with a video processing application such as a video editor. The video driver/interface is configurable to determine a best configuration of the system in order optimally perform the chosen video processing task. Configuration of a system includes dividing the task into subtasks and assigning the subtasks to processors of the system, including central processing units (CPUs) and graphics processing units (GPUs). Configuration of the system also includes optimizing use of available memory of different kinds. | 12-01-2011 |
| 20110291746 | REALTIME POWER MANAGEMENT OF INTEGRATED CIRCUITS - An integrated circuit comprising a plurality of functional blocks, each functional block being operative to cause one or more power consuming events, each power consuming event being associated with a respective weight. The integrated circuit also comprises at least one accumulation block for monitoring the functional blocks over a time window and generating a weighted count of the number of occurrences of each power consuming event within the time window; and a power calculation module for calculating a runtime power consumption estimate over the time window using the weighted count. The weighted count may comprise a sum of products of each one of the power consuming events by its respective weight. Calculating the runtime power consumption estimate may comprise averaging the weighted count over the time window to generate a dynamic power estimate, calculating a leakage power estimate over the time window, and summing the dynamic power estimate with the leakage power estimate. The integrated circuit may further comprise a power management module for adapting power consumption of the integrated circuit based on a comparison of the runtime power consumption estimate with one or more predetermined thresholds. | 12-01-2011 |
| 20110289332 | METHOD AND APPARATUS FOR POWER MANAGEMENT IN A MULTI-PROCESSOR SYSTEM - Techniques for power management in a multi-processor system are disclosed. One of the processors in the system monitors whether all threads on all central processing unit (CPU) cores in the multi-processor system halt, and send a message to a south bridge to cause at least a part of the system to enter a low power state if all threads in the multi-processor system halt. The processor sends another message to the south bridge to cause at least a part of the multi-processor system to wake up if at least one thread on any CPU core in the multi-processor system exits a halt. | 11-24-2011 |
| 20110285731 | Mechanism for Granting Controlled Access to a Shared Resource - Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource. | 11-24-2011 |
| 20110283293 | Method and Apparatus for Dynamic Allocation of Processing Resources - A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device. | 11-17-2011 |
| 20110283117 | POWER MANAGEMENT METHOD AND APPARATUS - An apparatus includes a power management interpretation circuit and a power management control circuit. The power management interpretation circuit provides power management control information in response to power control parameters. The power management control circuit selectively controls power consumption of a power consuming circuit based on the power management control information. The power consuming circuit provides the power control parameters. | 11-17-2011 |
| 20110279938 | DYNAMIC LEAKAGE CONTROL USING SELECTIVE BACK-BIASING - Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first power rail is coupled to an existing power supply and the second power rail is coupled to a separate adjustable voltage regulator. A separate voltage regulator may also be provided for the first power rail. A hardware-based state machine or software process is programmed to detect the occurrence of one or more modes of operation and adjust the voltage regulators for the first and second power rails to either enable or disable the back biasing state of the circuit, or alter the threshold voltage of the circuit within a specified voltage range. | 11-17-2011 |
| 20110279156 | PROGRAMMABLE FINE LOCK/UNLOCK DETECTION CIRCUIT - An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also includes a programmable fine lock/unlock detection circuit that includes programmable static phase error sensitivity logic that senses phase error. The programmable static phase error sensitivity logic sets a phase lock sensitivity window used to determine a fine lock/unlock condition of the generated output clock signal. The programmable fine lock/unlock detection logic is also operative to generate a fine phase lock/unlock signal based on the set phase lock sensitivity window. The integrated circuit may also include a coarse lock detection circuit that generates a coarse lock signal based on a frequency unlock condition. | 11-17-2011 |
| 20110272791 | METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION - A method far farming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors. | 11-10-2011 |
| 20110263094 | METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION - A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner. | 10-27-2011 |
| 20110260263 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material. | 10-27-2011 |
| 20110253983 | SIDEWALL GRAPHENE DEVICES FOR 3-D ELECTRONICS - A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device. | 10-20-2011 |
| 20110250749 | INTERCONNECTS WITH IMPROVED ELECTROMIGRATION RELIABILITY - An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality of segments to enable the interconnect structure to avoid electromigration problems. | 10-13-2011 |
| 20110244377 | FLUORINE-PASSIVATED RETICLES FOR USE IN LITHOGRAPHY AND METHODS FOR FABRICATING THE SAME - Fluorine-passivated reticles for use in lithography and methods for fabricating and using such reticles are provided. According to one embodiment, a method for performing photolithography comprises placing a fluorine-passivated reticle between an illumination source and a target semiconductor wafer and causing electromagnetic radiation to pass from the illumination source through the fluorine-passivated reticle to the target semiconductor wafer. In another embodiment, a fluorine-passivated reticle comprises a substrate and a patterned fluorine-passivated absorber material layer overlying the substrate. According to another embodiment, a method for fabricating a reticle for use in photolithography comprises providing a substrate and forming a fluorine-passivated absorber material layer overlying the substrate. | 10-06-2011 |
| 20110234253 | INTEGRATED CIRCUIT DIE TESTING APPARATUS AND METHODS - A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines. When on the wafer, the dies in a pipeline are interconnected with pipeline die test interconnection paths that provide pipeline test information interconnection among the plurality of dies in the pipeline. | 09-29-2011 |
| 20110231630 | ADDRESS MAPPING IN VIRTUALIZED PROCESSING SYSTEM - A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic. The resulting WorldID and ASID search keys are used to perform one or more TLB lookups to obtain address mapping information related to the particular address space represented by the WorldID/ASID combination. | 09-22-2011 |
| 20110208989 | Command Protocol for Adjustment of Write Timing Delay - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal. | 08-25-2011 |
| 20110208951 | INSTRUCTION PROCESSOR AND METHOD THEREFOR - A method of executing a program instruction is disclosed. An instruction operand stored at a register of a register file is accessed by an execution unit using multiple access requests. A first portion of the execution unit provides a first access request to a first access port of the register file to access a first portion of the instruction operand. A second portion of the execution unit provides a second access request to a second access port of the register file to access a second portion of the instruction operand. The register file can be configured into physically separate portions. | 08-25-2011 |
| 20110208505 | ASSIGNING FLOATING-POINT OPERATIONS TO A FLOATING-POINT UNIT AND AN ARITHMETIC LOGIC UNIT - A processor may include a floating-point unit (FPU) and an arithmetic logic unit (ALU). Instructions to the processor may include greater or lesser amounts of floating-point operations and integer operations. In a circumstance where instructions include predominantly integer operations, power to the FPU may be reduced or turned completely off. In such a circumstance, occasional floating-point operations may be emulated and performed by the ALU. If the processor subsequently determines that incoming instructions include a greater proportion of floating-point operations, the FPU may be powered back on and used to perform the floating-point operations. | 08-25-2011 |
| 20110204429 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME - A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor. | 08-25-2011 |
| 20110202724 | IOMMU Architected TLB Support - Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs). | 08-18-2011 |
| 20110198677 | SYSTEMS AND METHODS FOR A CONTINUOUS-WELL DECOUPLING CAPACITOR - A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities. | 08-18-2011 |
| 20110191741 | DETERMINING A PREDICTED SOFT ERROR RATE FOR AN INTEGRATED CIRCUIT DEVICE DESIGN - A method for determining a predicted soft error rate (SER) for an integrated circuit device design includes calculating the SER based on a predicted amount of charge imparted by a one or more particles to the integrated circuit device based on the design. The SER is further based on a predicted sensitivity level of a region of the integrated circuit device to the charge imparted by the one or more particles, and can also be based on the energy spectrum of the particles. | 08-04-2011 |
| 20110187569 | ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION - A 1.5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage. The second voltage then is either increased or decreased by the reference voltage based on the polarity of the second voltage to generate the residual voltage used for the next conversion cycle in the series. Each bit pair is mapped to a corresponding two-bit code value and the resulting code values are used to generate the digital value. | 08-04-2011 |
| 20110185256 | Adjustment of Write Timing Based on Error Detection Techniques - A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 07-28-2011 |
| 20110185218 | Adjustment of Write Timing Based on a Training Signal - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 07-28-2011 |
| 20110183486 | TRANSISTOR HAVING V-SHAPED EMBEDDED STRESSOR - A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions. | 07-28-2011 |
| 20110165739 | ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION - A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs. | 07-07-2011 |
| 20110161620 | SYSTEMS AND METHODS IMPLEMENTING SHARED PAGE TABLES FOR SHARING MEMORY RESOURCES MANAGED BY A MAIN OPERATING SYSTEM WITH ACCELERATOR DEVICES - Systems and methods are provided that utilize shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system. | 06-30-2011 |
| 20110161619 | SYSTEMS AND METHODS IMPLEMENTING NON-SHARED PAGE TABLES FOR SHARING MEMORY RESOURCES MANAGED BY A MAIN OPERATING SYSTEM WITH ACCELERATOR DEVICES - Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system. | 06-30-2011 |
| 20110156130 | METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE - A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures. | 06-30-2011 |
| 20110148923 | POWER EFFICIENT MEMORY - A circuit includes a memory circuit. The memory retiling circuit moves image information configured to be distributed among a plurality of memory channels into reconfigured image information configured to be distributed among a subset of the plurality of memory channels. | 06-23-2011 |
| 20110148899 | Image Quality Configuration Apparatus, System and Method - A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed. | 06-23-2011 |
| 20110148838 | BIAS CIRCUIT FOR A COMPLEMENTARY CURRENT MODE LOGIC DRIVE CIRCUIT - A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage. | 06-23-2011 |
| 20110145676 | DATA ERROR CORRECTION DEVICE AND METHODS THEREOF - A method and device for error detection includes performing error detection for each data word received in a burst access to a memory. When no error is detected, the data words are written to a cache and indicated as valid data. In response to detecting an error in a data word, the error is corrected and the corrected data written to the cache without indicating the data as valid. In addition, the location of the detected error, indicating the data symbol associated with the error, is recorded in an error vector. The error vectors associated with each data word in the burst access are compared to determine whether a detected error was properly corrected. | 06-16-2011 |
| 20110145515 | Method for modifying a shared data queue and processor configured to implement same - According to one exemplary embodiment, a method for modifying a shared data queue accessible by a plurality of processors comprises receiving an instruction from one of the processors to produce a modification to the shared data queue, running a microcode program in response to the instruction, to attempt to produce the modification, and generating a final datum to signify whether the modification to the shared data queue has occurred. In one embodiment, the modification comprises enqueuing data, and running the microcode program includes checking writability of a write pointer of the shared data queue, checking writability of a data field designated by the write pointer, locking the write pointer and checking the old value of its lock bit with atomicity, writing the data to the data field and incrementing the write pointer by the size of the data, and unlocking the write pointer. | 06-16-2011 |
| 20110145492 | POLYMORPHOUS SIGNAL INTERFACE BETWEEN PROCESSING UNITS - A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol. | 06-16-2011 |
| 20110134520 | Optical isolation module and method for utilizing the same - According to one embodiment, an optical isolation module comprises first and second linear polarizers, a Faraday rotator situated between the first and second linear polarizers and a transmissive element including a half-wave plate also situated between the first and second linear polarizers. In one embodiment, a method for performing optical isolation comprises rotating an axis of polarization of a linearly polarized light beam by a first rotation in a first direction, and selectively rotating a portion of the linearly polarized light beam by a second rotation in the first direction to produce first and second linearly polarized light beam portions. As a result, the first linearly polarized light beam portion undergoes the first rotation, and the second linearly polarized light beam portion undergoes the first and second rotations. The method further comprises filtering one of the first and second linearly polarized light beam portions to produce a light annulus. | 06-09-2011 |
| 20110133788 | DUAL FUNCTION VOLTAGE AND CURRENT MODE DIFFERENTIAL DRIVER - A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver. | 06-09-2011 |
| 20110131381 | CACHE SCRATCH-PAD AND METHOD THEREFOR - An address containing data to be accessed is determined in response to executing an instruction received at a processor core of a microprocessor. During a scratch-pad mode of operation, it is determined whether a set of cache lines of a data cache is accessible based upon the memory location from which the instruction was retrieved. The address space of the data cache during scratch-pad mode can be isolated from other address spaces. | 06-02-2011 |
| 20110111348 | SEMICONDUCTOR DEVICE FABRICATION USING A MULTIPLE EXPOSURE AND BLOCK MASK APPROACH TO REDUCE DESIGN RULE VIOLATIONS - A method of fabricating a semiconductor device begins by forming a layer of hard mask material on a substrate comprising a layer of semiconductor material and a layer of insulating material overlying the layer of semiconductor material, such that the layer of hard mask material overlies the layer of insulating material. A multiple exposure photolithography procedure is performed to create a combined pattern of photoresist features overlying the layer of hard mask material, and a recess line pattern is in the hard mask material, using the combined pattern of photoresist features. The method continues by covering designated sections of the recess line pattern with a blocking pattern of photoresist features, and forming a pattern of trenches in the insulating material, where the pattern of trenches is defined by the blocking pattern of photoresist features and the hard mask material. Thereafter, an electrically conductive material is deposited in the trenches, resulting in conductive lines for the semiconductor device. | 05-12-2011 |
| 20110111330 | METHOD OF CREATING PHOTOLITHOGRAPHIC MASKS FOR SEMICONDUCTOR DEVICE FEATURES WITH REDUCED DESIGN RULE VIOLATIONS - A method of creating photolithographic masks for semiconductor device features with reduced design rule violations is provided. The method begins by providing preliminary data that represents an overall mask pattern. The preliminary data is processed to decompose the overall mask pattern into a plurality of component mask patterns. Next, a design rule check is performed on the plurality of component mask patterns to identify tip-to-tip and tip-to-line violations in the plurality of component mask patterns. The method continues by modifying at least one of the plurality of component mask patterns in accordance with the identified violations to obtain a modified set of component mask patterns, wherein each mask pattern in the modified set of component mask patterns is void of tip-to-tip and tip-to-line violations. Photolithographic masks are then created for the modified set of component mask patterns. | 05-12-2011 |
| 20110107328 | VIRTUAL MACHINE DEVICE AND METHODS THEREOF - A data processing device is configured such that, during a loop executed by a guest, the device executes a PAUSE instruction. In response to executing a PAUSE instruction, the data processing device determines a relationship between the current PAUSE instruction and a previously executed PAUSE instruction. For example, the data processing device can determine the amount of time that has elapsed between the PAUSE instructions. Based on the relationship between the current and previous pause instructions, the data processing device can reset the counter to a reset value, or adjust (i.e. increment or decrement) the counter by a defined amount. | 05-05-2011 |
| 20110107092 | PERFORMANCE BASED AUTHENTICATION METHOD AND APPARATUS FOR SECURE COMMUNICATION - An apparatus includes a first module and a second module. The first module provides a challenge. The second module performs a signature function in response to the challenge. The first module authenticates the second module based on a time required by the second module to complete the signature function and/or an amount of power consumed by the second module to complete the signature function. | 05-05-2011 |
| 20110087833 | LOCAL NONVOLATILE WRITE-THROUGH CACHE FOR A DATA SERVER HAVING NETWORK-BASED DATA STORAGE, AND RELATED OPERATING METHODS - A data server, a host adapter system for the data server, and related operating methods facilitate data write and read operations for network-based data storage that is remotely coupled to the data server and for non-network-based data storage in a locally attached cache device. The host adapter system includes a local storage controller module and a network storage controller module. The local storage controller module is utilized for a locally attached, nonvolatile, write-through cache device of the data server. The network storage controller module is utilized for a network-based data storage architecture of the data server. The storage controller modules support concurrent writing of data to the local cache storage and the network-based storage architecture. The storage controller modules also support reading of server-maintained data from the local cache storage and the network-based storage architecture. | 04-14-2011 |
| 20110078653 | ADDING SIGNED 8/16/32-BIT INTEGERS TO 64-BIT INTEGERS - Disclosed are methods, apparatus, and computer-readable media for generating output computer code that adds a 64-bit integer to a smaller-length integer having a length of less than 64 bits. Input computer code includes a loop that includes adding a 64-bit integer and a smaller-length integer. Output code is generated that represents the input code in a format such as assembly language or machine code. The output code includes instructions to convert the smaller-length integer to a 64-bit integer, such that the conversion is not performed during each loop execution. The smaller-length integer is converted by subtracting an offset from the 64-bit integer, adding the offset to the smaller-length integer, and zero-extending the smaller-length integer. The offset is determined based on the length of the smaller-length integer. The output code preserves the integer semantics of the smaller-length integer as required by the input code. | 03-31-2011 |
| 20110067013 | SYSTEMS AND METHODS FOR DEFERRING SOFTWARE IMPLEMENTATION DECISIONS UNTIL LOAD TIME - A software development method defers certain implementation details until load time. A programmer first annotates, in source code, a selected set of software components using metadata (such as Java-style annotations) that define one or more criteria—e.g., criteria relating to the state of the target hardware platform, the capabilities of the platform, or arbitrary user input. The annotated source code files are then compiled to create one or more intermediate code files (e.g., Java bytecode files). During load time of the resulting intermediate code files, one or more of the selected set of software components are loaded from the intermediate code files based on the criteria. | 03-17-2011 |
| 20110066813 | Method And System For Local Data Sharing - Embodiments for a local data share (LDS) unit are described herein. Embodiments include a co-operative set of threads to load data into shared memory so that the threads can have repeated memory access allowing higher memory bandwidth. In this way, data can be shared between related threads in a cooperative manner by providing a re-use of a locality of data from shared registers. Furthermore, embodiments of the invention allow a cooperative set of threads to fetch data in a partitioned manner so that it is only fetched once into a shared memory that can be repeatedly accessed via a separate low latency path. | 03-17-2011 |
| 20110063311 | Course Grain Command Buffer - A method for executing processes within a computer system is provided. The method includes determining when to switch from a first process, executing within the computer system, to executing another process. Execution of the first process corresponds to a computer system storage location. The method also includes switching to executing the other process based upon a time quantum and resuming execution of the first process after the time quantum has lapsed, the resuming corresponding to the storage location. | 03-17-2011 |
| 20110063010 | RECTIFYING AND LEVEL SHIFTING CIRCUIT - A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs. | 03-17-2011 |
| 20110060928 | Method and Apparatus for Disabling a Device - A method of operating a device is provided. The method includes transitioning the GPU to a substantially disabled state in response to a first received signal, and generating, while the GPU is in the substantially disabled state, a response signal in response to a second received signal. The response signal is substantially similar to a second response signal that would be generated by the GPU in a powered state in response to the second received signal. | 03-10-2011 |
| 20110060879 | SYSTEMS AND METHODS FOR PROCESSING MEMORY REQUESTS - A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit. | 03-10-2011 |
| 20110057940 | Processing Unit to Implement Video Instructions and Applications Thereof - Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data. | 03-10-2011 |
| 20110057939 | Reading a Local Memory of a Processing Unit - Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit. | 03-10-2011 |
| 20110057938 | Variable Frequency Output To One Or More Buffers - A system and method are presented by which data on a graphics processing unit (GPU) can be output to one or more buffers with independent output frequencies. In one embodiment, a GPU includes a shader processor configured to respectively emit a plurality of data sets into a plurality of streams in parallel. Each data is emitted into at least a portion of its respective stream. Also included is a first number of counters configured to respectively track the emitted data sets. | 03-10-2011 |
| 20110057936 | Managing Resources to Facilitate Altering the Number of Active Processors - A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU. | 03-10-2011 |
| 20110057933 | Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation - A method and computer program product are provided for resolution enhancement of a video stream based on spatial and temporal correlation. For instance, the method can include predicting interpolated pixels for an image frame of the video stream based on a spatial correlation of pixels in the image frame. The method can also include generating one or more motion vectors for the image frame. Based on the spatially-correlated pixels and the one or more motion vectors, an enhanced image can be reconstructed. Further, the method can include providing a correction factor to one or more pixels in the enhanced image frame. | 03-10-2011 |
| 20110057677 | DIE STACKING, TESTING AND PACKAGING FOR YIELD - A method to test and package dies so as to increase overall yield is provided. The method includes performing a wafer test on a first die and mounting the first die on a package substrate to form a partial package, if the wafer test of the first die is successful. The method further includes performing a system test on the partial package including the first die and stacking a second die on the first die if the system test on the partial package and the first die is successful. | 03-10-2011 |
| 20110055511 | Interlocked Increment Memory Allocation and Access - A method of allocating a memory to a plurality of concurrent threads is presented. The method includes dynamically determining writer threads each having at least one pending write to the memory; and dynamically allocating respective contiguous blocks in the memory for each of the writer threads. Another method of allocating a memory to a plurality of concurrent threads includes launching the plurality of threads as a plurality of wavefronts, dynamically determining a group of wavefronts each having at least one thread requiring a write to the memory, and dynamically allocating respective contiguous blocks in the memory for each wavefront from the group of wavefronts. A corresponding method of assigning a memory to a plurality of reader threads includes determining a first number corresponding to a number of writer threads having a block allocated in said memory, launching a first number of reader threads, entering a first wavefront of said reader threads from said group of wavefronts to an atomic operation, and assigning a first block in the memory to the first wavefront during the corresponding atomic operation, where the first block is contiguous to a previously allocated block dynamically allocated to another wavefront from said group of wavefronts. Corresponding system embodiments and computer program product embodiments are also presented. | 03-03-2011 |
| 20110055308 | Method And System For Multi-Precision Computation - Systems and methods for multi-precision computation are disclosed. One embodiment of the present invention includes a plurality of multiply-add units (MADDs) configured to perform one or more single precision operations and an arrangement generator to generate one or more mantissa arrangements using a plurality of double precision numbers. Each MADD is configured to receive and load said mantissa arrangements from the arrangement generator. The MADDs compute a result of a multi-precision computation using the mantissa arrangements. In an embodiment, the MADDs are configured to simultaneously perform operations that include, single precision operations, double-precision additions and double-precision multiply and additions. | 03-03-2011 |
| 20110050716 | Processing Unit with a Plurality of Shader Engines - A processor includes a first shader engine and a second shader engine. The first shader engine is configured to process pixel shaders for a first subset of pixels to be displayed on a display device. The second shader engine is configured to process pixel shaders for a second subset of pixels to be displayed on the display device. Both the first and second shader engines are also configured to process general-compute shaders and non-pixel graphics shaders. The processor may also include a level-one (L1) data cache, coupled to and positioned between the first and second shader engines. | 03-03-2011 |
| 20110050713 | Hardware-Based Scheduling of GPU Work - An apparatus and methods for scheduling and executing commands issued by a first processor, such as a CPU, on a second processor, such as a GPU, are disclosed. In one embodiment, a method of executing processes on a graphics processing unit (GPU) includes monitoring one or more buffers in a memory, selecting a first subset from the one or more buffers for execution on the GPU based on a workload profile of the GPU, and executing the first subset on the GPU. The GPU may also receive a priority ordering of the one or more buffers, where the selecting is further based on the received priority ordering. By performing prioritization and scheduling of commands in the GPU, system performance is enhanced. | 03-03-2011 |
| 20110050710 | Internal, Processing-Unit Memory For General-Purpose Use - Disclosed herein is a graphics-processing unit (GPU) having an internal memory for general-purpose use and applications thereof. Such a GPU includes a first internal memory, an execution unit coupled to the first internal memory, and an interface configured to couple the first internal memory to a second internal memory of an other processing unit. The first internal memory may comprise a stacked dynamic random access memory (DRAM) or an embedded DRAM. The interface may be further configured to couple the first internal memory to a display device. The GPU may also include another interface configured to couple the first internal memory to a central processing unit. In addition, the GPU may be embodied in software and/or included in a computing system. | 03-03-2011 |
| 20110050284 | SENSE AMPLIFIER CIRCUIT AND RELATED CONFIGURATION AND OPERATION METHODS - A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET. | 03-03-2011 |
| 20110037115 | SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE - A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench. | 02-17-2011 |
| 20110029694 | SOFTWARE CONTROLLED REDIRECTION OF CONFIGURATION ADDRESS SPACES - A peripheral device can be powered off when not in use by redirecting accesses to the peripheral device's configuration space from the peripheral device to a memory located separate from the peripheral device. A method for redirecting accesses includes copying the current contents of the configuration space to the memory. Accesses to the configuration space are redirected to the memory, whereby the memory services the accesses to the configuration space. After the redirection is enabled, the peripheral device can be powered off. When the peripheral device needs to be used again, it is powered on and the contents of the memory are copied to the configuration space. The configuration space can then resume servicing configuration space accesses. | 02-03-2011 |
| 20110024841 | MOSFET WITH ASYMMETRICAL EXTENSION IMPLANT - A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure. | 02-03-2011 |
| 20110022817 | Mapping Processing Logic Having Data-Parallel Threads Across Processors - A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads into one or more workgroups, associating a first workgroup from the one or more workgroups with an operating system thread on the processor core, and configuring threads from the first workgroup as user-level threads within the operating system thread. In an example, a method enables the execution of GPU-kernels that has been previously configured for a GPU, to execute on a CPU such as a multi-core CPU. The mapping of the numerous data-parallel threads to the CPU is done in such a manner as to reduce the number of costly operating system threads instantiated on the CPU, and to enable efficient debugging. | 01-27-2011 |
| 20110016053 | FINANCIAL TRANSACTION SYSTEM - A system and method for conducting a financial transaction is disclosed. The system includes a first memory location embedded in a personal portable device. The first memory location stores a plurality of personal financial data files associated with a user. The system also includes a second memory location to store biometric information and a first input interface to receive authentication information after initiation of a purchase transaction session. The system also includes a security module including an input coupled to the first interface to authenticate the authentication information based on the biometric information and an output interface comprising an input coupled to the first memory location and an output to provide personal financial data file information to a host device. | 01-20-2011 |
| 20110010707 | VIRTUAL MACHINE DEVICE AND METHODS THEREOF - A data processing device includes one or more state registers to store state information associated with an execution core of the device. Each state register includes an associated “dirty” bit. When a guest program is executed at the execution core, a dirty bit is set in response to a change in the state information at the associated state register. In response to a world switch from the guest program to a VMM, the state information at each state register is stored to memory only if the associated dirty bit is set. In addition, if the VMM changes any stored state information, it clears a “clean” bit associated with the changed information. In response to a world switch from the VMM to a guest, the state information associated with cleared clean bits is retrieved from memory. | 01-13-2011 |
| 20100332792 | Integrated Vector-Scalar Processor - Systems and methods for improved vector data processing based on separately processing elements of a vector in multiple simultaneously executing vector element processing units are disclosed. One embodiment of the present invention is a vector processing system including a plurality of vector element processing units and a routing infrastructure. The routing infrastructure is configured to route each element of a received vector to a respective one of the vector element processing units. The received vector may be from a memory which is coupled to the vector element processing units by the routing infrastructure. Each vector element processing unit is configured to simultaneously process two or more elements, wherein each of the two or more elements is from a separate vector. Embodiments of the present invention also provide for forwarding of data and results of computation between vector element processing units. | 12-30-2010 |
| 20100329045 | Adjustment of Write Timing in a Memory Device - A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal. | 12-30-2010 |
| 20100313175 | VERIFICATION SYSTEMS AND METHODS - Described are verification devices and methods for controlling X propagation in a circuit design which identify a first location in a circuit at which an X value is generated, specify a second location in the circuit at which the X value is unwanted, and prove that the X value is unable to propagate from the first location to the second location over any path through the circuit between the first and second locations. | 12-09-2010 |
| 20100306301 | ARITHMETIC PROCESSING UNIT THAT PERFORMS MULTIPLY AND MULTIPLY-ADD OPERATIONS WITH SATURATION AND METHOD THEREFOR - Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal. | 12-02-2010 |
| 20100303156 | Method and Apparatus for Providing Precise Transport Stream Packet Ordering and Erasure Optimization for Digital Video Decoder - One method includes estimating, by a lost packet determination logic, an expected number of packets, expected to be received within a time interval, based on packet arrival speed; and determining a number of lost packets by using the expected number of packets and a packet counter wherein the packet counter counts a plurality of received packets. The method may further include comparing the expected number of packets to the packet counter and determining that the expected number of packets is greater than the packet counter; and then using the expected number of packets and the packet counter to determine the actual number of lost packets, where the actual number of lost packets exceeds the packet counter maximum. The methods may also introduce erasures when there is uncertainty of whether some packets or bytes are in error, such that a simplified erasure-based Reed-Solomon decoder may be used. | 12-02-2010 |
| 20100299454 | HIERARCHICAL LOSSLESS COMPRESSION - A method is provided for data compression. The data compression method transforms a square of data into a tile of data. The tile of data is then divided into quads of data that are converted into a representative element, a first delta element, a second delta element, a third delta element, and a control word. A new tile of data is then formed with the representative elements, and the process is repeated until a single representative element remains. The single representative element is then embedded into an output stream with the control words and corresponding delta elements. Decompression of the data is symmetrical to the encoding once the bit stream has been parsed. | 11-25-2010 |
| 20100295575 | DIGITAL LEVEL SHIFTER AND METHODS THEREOF - A digital level shifter is disclosed that receives an input voltage from a first voltage domain, and provides an output voltage to a second voltage domain. The level shifter includes transistors configured in parallel with input transistors of the level shifter in order to place the output of the level shifter in a determinate state when one of the voltage domains is placed in a low power state. Further, the level shifter includes output transistors configured to equalize a rise time slew rate and fall time slew rate, improving the reliability of the level shifter as the voltage in each voltage domain varies. | 11-25-2010 |
| 20100270652 | DOUBLE EXPOSURE TECHNOLOGY USING HIGH ETCHING SELECTIVITY - Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask. | 10-28-2010 |
| 20100268921 | DATA COLLECTION PREFETCH DEVICE AND METHODS THEREOF - A method of retrieving information from a memory includes receiving an instruction associated with a data collection. In response to determining the instruction is a request to retrieve a first element of the data collection, an application program interface (API) generates an instruction to prefetch a second element of the data collection. In one embodiment, the second element to be prefetched is indicated by a pointer or other information associated with the first element. In response to the prefetch instruction, an execution core of the data processing device retrieves the second element from a memory module and stores the second element at a cache. By prefetching the second element before it has been explicitly requested by the application, the efficiency of the application can be increased. | 10-21-2010 |
| 20100267238 | METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING PLANARIZED SPACERS - Methods of fabricating a semiconductor device on and in a semiconductor substrate are provided. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, wherein the sacrificial mandrel has sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel, the sidewall spacers having an upper portion and a lower portion. The upper portion of the sidewall spacers is removed. The sacrificial mandrel is removed and the semiconductor substrate is etched using the lower portion of the sidewall spacers as an etch mask. | 10-21-2010 |
| 20100267237 | METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING ASHABLE SACRIFICIAL MANDRELS - Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel. The sacrificial mandrel is removed using an ashing process, and the substrate is etched using the sidewall spacers as an etch mask after removal of the sacrificial mandrel. | 10-21-2010 |
| 20100262750 | REGION PREFETCHER AND METHODS THEREOF - A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address. | 10-14-2010 |
| 20100260001 | MEMORY DEVICE AND METHODS THEREOF - A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor. | 10-14-2010 |
| 20100250842 | HYBRID REGION CAM FOR REGION PREFETCHER AND METHODS THEREOF - A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range. | 09-30-2010 |
| 20100248454 | METHOD OF FORMING FIN STRUCTURES USING A SACRIFICIAL ETCH STOP LAYER ON BULK SEMICONDUCTOR MATERIAL - A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material. | 09-30-2010 |
| 20100245374 | METHOD AND APPARATUS FOR ANGULAR INVARIANT TEXTURE LEVEL OF DETAIL GENERATION - A method and apparatus for angular invariant texture level of detail calculation is disclosed. The method includes a determination for a LOD that determines angular invariant LODs that result in efficient ASIC hardware implementation. | 09-30-2010 |
| 20100244267 | INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND RELATED METHOD OF MANUFACTURE - A semiconductor device having a device substrate is provided. The semiconductor device comprises an electrically-conductive pad formed overlying the device substrate, an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity, the electrically-conductive platform having a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion, and a cushioning material disposed in the cavity. | 09-30-2010 |
| 20100238599 | Power Supply Equalization Circuit Using Distributed High-Voltage and Low-Voltage Shunt Circuits - Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail. | 09-23-2010 |
| 20100238598 | Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices - Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time. | 09-23-2010 |
| 20100238358 | ADJACENT CHANNEL POWER SCAN - A method and apparatus are disclosed for determining the presence of adjacent channel interference. Received digital signals are processed to detect the existence of strong channels adjacent to the channel of interest and control signals may be generated based on the detection of strong adjacent channels. The control signals are then used to adjust the signal power of the received signals. | 09-23-2010 |
| 20100237924 | DIGITAL FREQUENCY SYNTHESIZER DEVICE AND METHOD THEREOF - A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal. | 09-23-2010 |
| 20100232552 | SYNCHRONIZATION AND ACQUISITION FOR MOBILE TELEVISION RECEPTION - A method for synchronizing a receiver to a received signal begins by down-converting the received signal to a first baseband signal. A coarse frequency offset (CFO) of the first baseband signal is determined and is applied to the down-converting of the received signal to a second baseband signal. A fine frequency offset (FFO) of the second baseband signal is determined. The receiver is synchronized to the received signal using the CFO and the FFO. | 09-16-2010 |
| 20100231588 | METHOD AND APPARATUS FOR RENDERING INSTANCE GEOMETRY - A method and apparatus for rendering instance geometry whereby all culling, level of detail (LOD) and scene management is performed directly on a GPU. | 09-16-2010 |
| 20100225741 | 3D VIDEO PROCESSING - A method and apparatus for reducing motion judder in a 3D input source are disclosed. The 3D input source is separated into left and right images. Motion vectors for the left and right images are calculated. Frame rate conversion is performed on the left and right images, to produce motion compensated left and right images. The left and right images and the motion compensated left and right images are reordered for display. Alternatively, the motion estimation and motion compensation can be performed on the 3D input source, and the input image and the motion compensated image can then be separated into respective left and right images. The method and apparatus can be adapted to perform 2D to 3D conversion by extracting a 2D input source into left and right 3D images and performing motion estimation and motion compensation. | 09-09-2010 |
| 20100223525 | ERROR DETECTION DEVICE AND METHODS THEREOF - A first error detection for a first data word is performed using a first error correction code associated with the first data word. In response to the first error detection indicating a first uncorrectable error at the first data word based upon the first error correction code, a second error detection for a plurality of data words including the first data word and a second data word is performed using a second error correction code based upon the first and second data words. | 09-02-2010 |
| 20100218207 | METHOD AND APPARATUS TO DETECT PREVIEW OF ENCRYPTED CONTENT - A method and apparatus detects a presence of a change in encryption status of video information, such as a preview, in a video stream. The method and apparatus issues notification information such as through a visual user interface, audibly or in any other suitable manner, that new content, such as a pay per view video information, is either available or unavailable based on the detection of a change in encryption status of the video information. An interactive and automated technique is provided to inform a user while, for example, the user is watching a display device, that a preview of content is now available or that a previously available preview has now changed and is now encrypted and therefore a user must order the previewed content before an expiration period occurs. In this fashion, a user is automatically notified that a free preview is available, while watching television and a broadcaster may increase revenues since preview information is more readily detected and presented to potential customers. | 08-26-2010 |
| 20100214008 | SEMICONDUCTOR DEVICE WITH TRANSISTOR-BASED FUSES AND RELATED PROGRAMMING METHOD - A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer. | 08-26-2010 |
| 20100213555 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a silicon oxide layer overlying the semiconductor substrate, forming a metal oxide gate capping layer overlying the silicon oxide layer, depositing a first metal gate electrode layer overlying the metal oxide gate capping layer, and removing a portion of the first metal gate electrode layer and the metal oxide gate capping layer to form a gate stack. | 08-26-2010 |
| 20100213553 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer. | 08-26-2010 |
| 20100211336 | DATA PROCESSING INTERFACE DEVICE - Information of a first type is determined at an integrated circuit die of a data processing device included an integrated circuit package. The integrated circuit package includes the first integrated circuit die and a second integrated circuit die. Information of a second type is determined at the integrated circuit die. The first and second type of information is transmitted from the integrated circuit die to another integrated circuit die using a time-divided multiplexed protocol by transmitting the first information during a first time slot of the protocol and transmitting the second information during a second time slot of the protocol. | 08-19-2010 |
| 20100210084 | METHODS FOR FABRICATING MOS DEVICES HAVING HIGHLY STRESSED CHANNELS - Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, etching recesses into the substrate using the gate electrode as an etch mask, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses. | 08-19-2010 |
| 20100207176 | Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same - Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer. | 08-19-2010 |
| 20100207175 | SEMICONDUCTOR TRANSISTOR DEVICE HAVING AN ASYMMETRIC EMBEDDED STRESSOR CONFIGURATION, AND RELATED MANUFACTURING METHOD - A semiconductor transistor device is provided. The transistor device includes a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, a source region in the layer of semiconductor material, and a drain region in the layer of semiconductor material. The source region has a stress-inducing semiconductor material located therein, while the drain region is free of any stress-inducing semiconductor material. This asymmetric arrangement of stress-inducing elements results in relatively high source-body leakage, and relatively low drain-body leakage, which is beneficial in analog circuit applications. | 08-19-2010 |
| 20100201343 | PROGRAMABLE DELAY MODULE TESTING DEVICE AND METHODS THEREOF - A data processing device is configured so that, in a test mode of operation, the phase of an output signal of a second programmable delay module (PDM) is based on the phase of the input signal of the first PDM. To test the first and second PDMs, the output signal of the first PDM is set to each of a first set of phases and the corresponding phase of the output signal of the second PDM is compared to determine whether the performance of the first and second PDMs match a specification. Accordingly, the first and second PDMs are qualified based on their relative performance, reducing the need for test structures that consume an undesirably large amount of area. | 08-12-2010 |
| 20100197096 | METHODS FOR FABRICATING FINFET STRUCTURES HAVING DIFFERENT CHANNEL LENGTHS - Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously. | 08-05-2010 |
| 20100193876 | METHOD TO REDUCE MOL DAMAGE ON NiSi - Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance. | 08-05-2010 |
| 20100188411 | Non-Graphics Use of Graphics Memory - Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc. | 07-29-2010 |
| 20100185820 | PROCESSOR POWER MANAGEMENT AND METHOD - A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power. | 07-22-2010 |
| 20100184265 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES MINIMIZING UNDER-OXIDE REGROWTH - Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack. | 07-22-2010 |
| 20100169892 | Processing Acceleration on Multi-Core Processor Platforms - Embodiments disclosed herein include an accelerator module that modifies a single application to run on multiple processing cores of a single CPU. In one aspect, the application performs a task that includes some parallel operations and some serial operations. The parallel tasks may be run on different cores concurrently. In addition, serial tasks may be broken up to execute among different cores simultaneously without errors. In a particular embodiment, a FFMPEG decoding application is modified by the accelerator module to execute on multiple cores and perform video decoding in real time or faster than real time. | 07-01-2010 |
| 20100166073 | Multiple-Candidate Motion Estimation With Advanced Spatial Filtering of Differential Motion Vectors - Embodiments include a motion estimation method performed in a parallel processing system that determines a list of several candidate motion vectors for a macroblock of a video image and retains them through multiple computation passes. All candidate motion vectors are used as potential neighboring predictors, so that the best combination of differential vectors rises to the top of the candidate list. Numerous combinations of differential motion vectors are considered during the process that compares motion vectors among up to eight neighboring macroblocks, instead of simply between pairs of macroblocks. The motion estimation system is configured to use a large number of compute engines, such as on a highly parallel GPU platform. This is achieved by having no dependencies between macroblocks except one per pass. This allows the number of calculations per pass to be very large. | 07-01-2010 |
| 20100166055 | Face Detection System for Video Encoders - Embodiments include a codec for use in a videoconferencing or similar system includes a video encoder pipeline that has a pre-processor component that is optimized to detect faces and compress the facial video data in an optimum manner. The codec has a pre-processing step that analyzes each frame on a per macroblock basis to determine the mathematical activity level per block. The activity level calculation is used as a parameter to the bitrate control module of the encoder to control the quantization, and thus the fine grained quality of the output data. An object detection module (e.g., a face detector) is placed in the pre-processing step. The object detection data is then combined with the activity level and object detection certainty value through a combinatorial algorithm comprising a weighted average or normalized multiplication process. | 07-01-2010 |
| 20100157695 | VOLTAGE SHIFTING WORD-LINE DRIVER AND METHOD THEREFOR - A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected to a level shifter to shift the corresponding select signal so that the driver module provides a level-shifted signal at the first word-line in response to assertion of the first select signal. A single level shifter can be connected to multiple driver modules, thereby reducing the area required to implement level-shifting for multiple word-lines. | 06-24-2010 |
| 20100157153 | Upgrading Non-Volatile Storage Via an Encoded Video Signal - Systems for generating and transmitting a video stream that is encoded with program data such that when decoded can be executed to update non-volatile storage within a video based electronic device. Typically video based electronic devices are controlled by processors running software stored in writable, non-volatile storage. It is often desirable or necessary to update the software after the device has been shipped from a factory in order to correct a software failure discovered after shipment or to incorporate a new set of features. As many video based electronic devices have no common interface available to connect a computer, there is no ability to receive a software update. However, most video based electronic devices can be connected to a video source. Therefore, systems that allow a video based electronic device to receive, decode, and execute program data that is encoded within a video stream are presented. A method for encoding program code into a video stream is also presented. | 06-24-2010 |
| 20100153893 | CONSTRAINT MANAGEMENT AND VALIDATION FOR TEMPLATE-BASED CIRCUIT DESIGN - A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations. | 06-17-2010 |
| 20100151660 | METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION - A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors. | 06-17-2010 |
| 20100146211 | Shader Complex with Distributed Level One Cache System and Centralized Level Two Cache - A shader pipe texture filter utilizes a level one cache system as a primary method of storage but with the ability to have the level one cache system read and write to a level two cache system when necessary. The level one cache system communicates with the level two cache system via a wide channel memory bus. In addition, the level one cache system can be configured to support dual shader pipe texture filters while maintaining access to the level two cache system. A method utilizing a level one cache system as a primary method of storage with the ability to have the level one cache system read and write a level two cache system when necessary is also presented. In addition, level one cache systems can allocate a defined area of memory to be sharable amongst other resources. | 06-10-2010 |
| 20100144106 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS AND METHODS FOR FABRICATING THE SAME - A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor. | 06-10-2010 |
| 20100144105 | METHODS FOR FABRICATING STRESSED MOS DEVICES - Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses. | 06-10-2010 |
| 20100141666 | Method and Apparatus for Spatial Binning on a GPU and Global Path Planning to Avoid Spatially Binned Objects - A method and apparatus for sorting data into spatial bins or buckets using a graphics processing unit (GPU). The method takes unsorted point data as input and scatters the points, in sorted order, into a set of bins. This key operation enables construction of a spatial data structure that is useful for applications such as particle simulation or collision detection. The disclosed method achieves better performance scaling than previous methods by exploiting geometry shaders to progressively trim the size of a working set. The method also leverages predicated rendering functionality to allow early termination without CPU/GPU synchronization. Furthermore, unlike previous techniques, the method can guarantee sorted output without requiring sorted input. This allows the method to be used to implement a form of bucket sort using the GPU. | 06-10-2010 |
| 20100134161 | Phase Detector Circuit for Automatically Detecting 270 and 540 Degree Phase Shifts - Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal. | 06-03-2010 |
| 20100128181 | Seam Based Scaling of Video Content - Methods and systems are provided for processing video data. In an embodiment, a method of scaling video data includes scaling one frame based on at least one seam of pixels of the one frame. The seam of pixels is selected based at least on information derived from at least one of: a previous frame and metadata relating to the one frame. In an embodiment, a method of processing video data includes determining whether a frame is to be scaled based on at least one seam of pixels based on at least one of information derived from the frame or metadata relating to the frame. The at least one seam of pixels is selected based at least on an energy associated with each pixel of the at least one seam of pixels. | 05-27-2010 |
| 20100125621 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF - An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and the second mode supports two simultaneous single-precision computations using the same exponent and mantissa datapaths. | 05-20-2010 |
| 20100125620 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF - A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM. | 05-20-2010 |
| 20100124293 | Method to Reduce Peak to Average Power Ratio in Multi-Carrier Modulation Receivers - Provided is a method for performing channel estimation in an Orthogonal Frequency Division Multiplexed (OFDM) signal. The method includes performing the channel estimation based upon use of reserved tone channel carriers. | 05-20-2010 |
| 20100124292 | Method and System for Receiver Synchronization - Provided is a method for synchronizing a multiple carrier receiver to receive a transmitted signal. The method includes determining a location of one or more scattered pilot carriers in a received symbol sequence and modulating the scattered pilot carriers in accordance with a single pseudorandom binary sequence. The method also includes performing phase error correction via the modulated scattered pilot carriers. | 05-20-2010 |
| 20100122711 | WET CLEAN METHOD FOR SEMICONDUCTOR DEVICE FABRICATION PROCESSES - A wet clean method for semiconductor device fabrication begins by providing a semiconductor device structure having a substrate and features protruding from the substrate. The features are formed from a dielectric material, such as an ultra-low-k material. The method continues by cleaning the semiconductor device structure with an aqueous solution and, following the cleaning step, displacing the aqueous solution with a first solvent. Thereafter, the features are exposed to a second solvent that contains a hydrophobic treatment agent that reacts with sidewalls of the features to form a hydrophobic layer on the sidewalls. | 05-20-2010 |
| 20100122262 | Method and Apparatus for Dynamic Allocation of Processing Resources - A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device. | 05-13-2010 |
| 20100120239 | MEMORY DEVICE ETCH METHODS - A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF | 05-13-2010 |
| 20100117676 | Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer - According to one exemplary embodiment, a non-destructive method for determining a breakdown voltage of a dielectric layer on a semiconductor substrate includes injecting a test current in increasing ramp steps into the dielectric layer. The method further includes measuring a test voltage across the dielectric layer at each increasing ramp step of the test current. The method further includes detecting a dropped test voltage in response to the increasing ramp steps of the test current. The ramp steps of the test current can be substantially logarithmically increased. The breakdown voltage of the dielectric layer can be designated to be substantially equal to the dropped test voltage. | 05-13-2010 |
| 20100111298 | BLOCK CIPHER DECRYPTION APPARATUS AND METHOD - An apparatus and method obtains cipher block chaining mode (CBC) ciphertext blocks that were encrypted using a cipher block chaining encryption method, such a audio or video, and decrypts the CBC ciphertext blocks that were encrypted using the cipher block chaining encryption method using a multistage counter mode (CTR) decryptor to produce blocks of plaintext data from the CBC ciphertext blocks. In one example, cipher block chaining mode (CBC) information is translated (e.g., rearranged) to random counter mode (CTR) information so that a multistage counter mode (CTR) decryptor decrypts CBC ciphertext blocks into corresponding decrypted CBC plaintext blocks, in a parallel fashion, based on the translated CBC information. As such, apparatus with CTR hardware can be used to decrypt CBC or CFB ciphertext blocks. | 05-06-2010 |
| 20100109056 | METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS - Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching. | 05-06-2010 |
| 20100107249 | Method, Apparatus, and Device for Protecting Against Programming Attacks and/or Data Corruption - The method and accompanying apparatus and device protects against programming attacks and/or data corruption by computer viruses, malicious code, or other types of corruption. In one example, signature verification policy information that identifies a plurality of policies associated with a plurality of target memory segments is programmed during a secure boot process. The programmed signature verification policy information associated with each of the plurality of target memory segments is then evaluated during run-time. Signature verification is then repeatedly performed, during run-time, on each of the plurality of target memory segments based on the programmed signature verification policy information associated with each target memory segment. | 04-29-2010 |
| 20100107166 | SCHEDULER FOR PROCESSOR CORES AND METHODS THEREOF - A data processing device assigns tasks to processor cores in a more distributed fashion. In one embodiment, the data processing device can schedule tasks for execution amongst the processor cores in a pseudo-random fashion. In another embodiment, the processor core can schedule tasks for execution amongst the processor cores based on the relative amount of historical utilization of each processor core. In either case, the effects of bias temperature instability (BTI) resulting from task execution are distributed among the processor cores in a more equal fashion than if tasks are scheduled according to a fixed order. Accordingly, the useful lifetime of the processor unit can be extended. | 04-29-2010 |
| 20100106979 | Method, Apparatus, and Device for Providing Security Among a Calling Function and a Target Function - The device and accompanying apparatus and method provides security among a calling function, such as an any executable code, and at least one target function, such as any executable code that the calling function wishes to have execute. In one example, the device includes an engine operative to perform run-time verification of the signatures of secure interrupt handler code and at least one target function before allowing execution of the at least one target function. If both the secure interrupt handler code's signature and the at least one target function's signature are successfully verified, the at least one target function is allowed to execute. | 04-29-2010 |
| 20100106929 | Method and Apparatus for Providing Secure Register Access - The method and accompanying apparatus provides secure register access. In one example, as part of a secure boot process, data is written into a managed secure register (MSR) register and access policy data is written into programmable MSR policy registers. During run-time, the MSR register securely stores data in compliance with the programmable register access policy data. Access policy is enforced during run-time based on the programmable register access policy data. | 04-29-2010 |
| 20100104021 | Remote Transmission and Display of Video Data Using Standard H.264-Based Video Codecs - Embodiments include implementing a remote display system (either wired or wireless) using a standard, non-custom codec. In this system, the decoder side can be fully implemented using an existing standard from a decode/display point of view and using a single stream type. The encoder side includes a pre-processing component that analyzes screen images comprising the video data to determine an amount of difference between consecutive frames of the screen images, divides each screen image into a plurality of regions, including no change regions, high quality regions, and low quality regions. The pre-processor characterizes each region as requiring a minimum quality level, encodes the low quality regions for compression in accordance with the H.264 encoding standard; and encodes the high quality regions using the lossless compression scheme of the H.264 standard. A no change region is encoded using a version of the H.264 encoding standard that adaptively and dynamically selects between lossless and lossy compression in a manner that optimizes efficiency of the compression operation. | 04-29-2010 |
| 20100103712 | MEMORY TEST DEVICE AND METHODS THEREOF - In accordance with a specific embodiment of the present disclosure, a content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches one of a plurality of values stored at memory locations of the CAM. In a test mode of operation, a plurality of test signals are applied to the CAM, and the CAM provides a match value in response to assertion of one of the test signals. The match value is applied to a functional module associated with the CAM to determine a test result. Accordingly, the test signals applied to the CAM provide a flexible way to generate match values and apply those values to the functional module during testing of the data processing device. | 04-29-2010 |
| 20100102891 | OSCILLATOR DEVICE AND METHODS THEREOF - An oscillator device includes a plurality of stages. Each stage is a monostable stage having a delay path, whereby a signal transition of a designated type (rising or falling) at the input of the delay path results in a signal transition at the output of the stage of the same transition type. Each stage of the oscillator device also includes a reset module that causes the output signal to be reset to a nominal state a predetermined period of time after the signal transition of the output signal. Each stage thus provides an output signal pulse in response to the signal transition of the designated type at the input. The output of the final stage of the oscillator device is connected to the input, so that the oscillator output provides an oscillating signal having a period based upon the delay path of each the oscillator device stages. | 04-29-2010 |
| 20100102435 | METHOD AND APPARATUS FOR REDUCING SEMICONDUCTOR PACKAGE TENSILE STRESS - A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package. | 04-29-2010 |
| 20100102363 | AIR GAP SPACER FORMATION - Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance. | 04-29-2010 |
| 20100100711 | DATA PROCESSOR DEVICE AND METHODS THEREOF - A microsequencer is disclosed that controls the order in which microcode instructions are fetched from a microcode ROM. Each microcode instruction includes an execution command for execution by one or more execution units. Each microcode instruction also includes a microsequencer command to indicate the location of another microcode instruction at the microcode ROM. The microcode instruction can also include a delay field, indicating a selectable time when the associated microcode instruction is to be decoded. The delay field thereby provides more flexible control of the sequencing of microcode instructions. | 04-22-2010 |
| 20100099045 | METHODS FOR PERFORMING PHOTOLITHOGRAPHY USING BARCS HAVING GRADED OPTICAL PROPERTIES - Photolithography methods using BARCs having graded optical properties are provided. In an exemplary embodiment, a photolithography method comprises the steps of depositing a BARC overlying a material to be patterned, the BARC having a refractive index and an absorbance. The BARC is modified such that, after the step of modifying, values of the refractive index and the absorbance are graded from first values at a first surface of the BARC to second values at a second surface of the BARC. The step of modifying is performed after the step of depositing. | 04-22-2010 |
| 20100099032 | SYSTEM FOR GENERATING AND OPTIMIZING MASK ASSIST FEATURES BASED ON HYBRID (MODEL AND RULES) METHODOLOGY - An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate. | 04-22-2010 |
| 20100096698 | STRESS ENHANCED TRANSISTOR - Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer | 04-22-2010 |
| 20100091584 | MEMORY DEVICE AND METHODS THEREOF - A memory device is disclosed that includes multiple bit cells, whereby each bit cell is capable of being programmed to more than two states. A value stored at the memory device is determined by comparing the information stored at three or more of the bit cells. In an embodiment, the bit cell includes a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (FET) device, and the information stored at the bit cell can be represented by a corresponding level of charge stored in the body of the device. | 04-15-2010 |
| 20100091028 | Texture Level Tracking, Feedback, and Clamping System for Graphics Processors - Embodiments include a texture mapping processor incorporating a dynamic level of detail map for use in a graphics processing system. Level of detail values are defined, with 0 being the finest and corresponding to the largest mipmap level. Each bound texture in a graphics object is assigned an identifier. This identifier is used as an index into a minimum-LOD value tracking table that is updated whenever a texel is fetched. A texture processing module controls when the tracking table is initialized and read back, and which identifiers are tracked. The minimum-LOD values in the tracking table are accompanied by a coarse region access mask to associate a minimum LOD value with a specific region of the image or object. A clamping table contains LOD clamp values for each region and a region code that specifies the coarseness of the LOD associated with each region of the texture. | 04-15-2010 |
| 20100091018 | Rendering Detailed Animated Three Dimensional Characters with Coarse Mesh Instancing and Determining Tesselation Levels for Varying Character Crowd Density - A method carried out by graphics processing circuitry includes generating animated coarse mesh vertex information based on instanced coarse mesh data; and tessellating instanced coarse mesh data based on the animated coarse mesh vertex information to produce instances of a three dimensional object for display. A graphics processing circuitry includes programmable shader logic operative to execute programmable instructions that when executed cause the programmable shader logic to generate animated coarse mesh vertex information based on instanced coarse mesh data; and tessellate instanced coarse mesh data based on the animated coarse mesh vertex information to produce instances of a three dimensional object for display. Another method carried out by graphics processing circuitry includes determining density of a plurality of three dimensional objects in a current view on a display; setting a tessellation level based on said density; and tessellating said plurality of three dimensional objects. | 04-15-2010 |
| 20100090289 | SEMICONDUCTOR DEVICES HAVING FACETED SILICIDE CONTACTS, AND RELATED FABRICATION METHODS - The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions. | 04-15-2010 |
| 20100088733 | DISTRIBUTED AUDIO AND VIDEO PROCESSING - A method of distributing audio and video processing tasks among devices interconnected to a display device via a local network is disclosed. In one embodiment, the display device offloads some processing tasks to a computing device on the local network to achieve improved processing performance. The computing device receives audiovisual data, decodes, processes, encodes and transmits the encoded data to the display device in a suitable data format. The processing in the computing device is complementary to any processing to be performed in the display device. In another embodiment, the display device utilizes a plurality of devices on the local network to perform particular signal processing tasks. The other devices in network perform the processing tasks indicated by the display, and send processed data back to the display device for presentation, which helps improve the overall audiovisual data processing performance. | 04-08-2010 |
| 20100088453 | Multi-Processor Architecture and Method - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 04-08-2010 |
| 20100088452 | Internal BUS Bridge Architecture and Method in Multi-Processor Systems - An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 04-08-2010 |
| 20100081245 | METHODS FOR FABRICATING MOS DEVICES HAVING HIGHLY STRESSED CHANNELS - Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses. | 04-01-2010 |
| 20100079162 | DATA PROCESSING DEVICE AND METHODS THEREOF - A data processing device includes a first memory for use during normal operation of the device and a second memory for use during testing. The second memory stores a set of test patterns for testing of a functional module. When the data processing device is in a normal (i.e. non-test) mode of operation, data is retrieved from a first memory based on a received memory address. The retrieved data is applied to the functional module of the data processing device to perform a designated function. When the data processing device is in a test mode of operation, received memory addresses are provided to the second memory for retrieval of a test pattern associated with the address. The test pattern is applied to the functional module to generate an output pattern. The result of a test is determined by comparing the output pattern to an expected pattern. | 04-01-2010 |
