| ADTRON, INC. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110035540 | FLASH BLADE SYSTEM ARCHITECTURE AND METHOD - A flash blade and associated methods enable improved areal density of information storage, reduced power consumption, decreased cost, increased IOPS, and/or elimination of unnecessary legacy components. In various embodiments, a flash blade comprises a host blade controller, a switched fabric, and one or more storage elements configured as flash DIMMs. Storage space provided by the flash DIMMs may be presented to a user in a configurable manner. Flash DIMMs, rather than magnetic disk drives or solid state drives, are the field-replaceable unit, enabling improved customization and cost savings. | 02-10-2011 |
| 20090259919 | FLASH MANAGEMENT USING SEPARATE MEDTADATA STORAGE - Disclosed are techniques for flash memory management, including storing metadata and/or error correcting information separately from payload data. In various embodiments, metadata and/or error correcting information are stored in a random access memory within a solid state drive. | 10-15-2009 |
| 20090259806 | FLASH MANAGEMENT USING BAD PAGE TRACKING AND HIGH DEFECT FLASH MEMORY - Disclosed are techniques for flash memory management, including utilizing defect information corresponding to a granularity smaller than a physical erase block size of a flash memory chip. | 10-15-2009 |
| 20090259805 | FLASH MANAGEMENT USING LOGICAL PAGE SIZE - Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip. | 10-15-2009 |
| 20090259801 | CIRCULAR WEAR LEVELING - A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory. | 10-15-2009 |
| 20090259800 | FLASH MANAGEMENT USING SEQUENTIAL TECHNIQUES - Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device. | 10-15-2009 |
| 20090212814 | Deliberate Destruction of Integrated Circuits - A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device. | 08-27-2009 |
