Adapteva Incorporated

Patent application number	Title	Published
Adapteva Incorporated Patent applications
20100115239	VARIABLE INSTRUCTION WIDTH DIGITAL SIGNAL PROCESSOR - A DSP architecture achieves high code density and performance by using 16 bit encoding/decoding of three-register instructions and including orthogonal 64 register selection fields within a 32-bit instruction. A 64 entry register file allows high performance, while the 16-bit instruction size provides excellent code density in control type applications.	05-06-2010
20100111088	MESH NETWORK - A mesh network has a plurality of nodes that can be arranged in a two or three dimensional arrangement. The address-based mesh routing scheme sends a full address and full data on every clock cycle. The system can include broadcasting to columns, rows, planes, or all system elements using a single data transaction. A selectable routing scheme can be random, fixed, or adaptive, depending on user configuration. A registered transaction-weight scheme is provided that can stall transactions in a mesh without having to resend data.	05-06-2010