MegaChips Corporation Patent applications |
Patent application number | Title | Published |
20160134267 | SKEW ADJUSTMENT CIRCUIT AND SKEW ADJUSTMENT METHOD - A skew adjustment circuit comprises a phase adjustment circuit that adjusts a phase of a first input clock based on a predetermined phase control signal, and outputs it as an output clock, a logical circuit that performs a logical operation between signals that are input, an integral circuit that generates a predetermined voltage signal, based on a result of the logical operation by the logical circuit, a comparator that compares an electric potential of the predetermined voltage signal and an electric potential of a predetermined reference voltage signal, a first controller that generates the predetermined phase control signal based on a result of the comparison by the comparator, and a second controller that performs control for selecting a signal that is to be input to the logical circuit. The second controller, in a first mode, performs the control such that the output clock and a second input clock are selected. | 05-12-2016 |
20160124826 | SEMICONDUCTOR DEVICE AND METHOD FOR TESTING RELIABILITY OF SEMICONDUCTOR DEVICE - A semiconductor memory includes a memory controller including a plurality of processing circuits. The plurality of processing units includes an encryption/decryption unit that encrypts and decrypts a signal transmitted to and from the memory controller. The encryption/decryption unit includes a self test unit that performs a reliability test of the encryption/decryption unit on receipt of a predetermined test command from a testing device. | 05-05-2016 |
20160119648 | IMAGE PROCESSOR - In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image. | 04-28-2016 |
20160118142 | MEMORY DEVICE AND METHOD FOR TESTING RELIABILITY OF MEMORY DEVICE - A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device. | 04-28-2016 |
20160111791 | PATTERN ANTENNA - A pattern antenna, with desired antenna characteristics, that is formed in a small area is provided. The pattern antenna includes a substrate, a ground portion formed on a first surface of the substrate, an antenna element portion, a short-circuiting portion, and a connecting portion. The antenna element portion is a conductor pattern including a conductor pattern in which a plurality of bent portions are formed. The conductor pattern is formed on the first surface of the substrate and, and is electrically connected to the grand portion. The short-circuiting portion includes a conductor pattern formed in a second surface, which is a different surface from the first surface. The conductor pattern is formed so as to at least partially overlap with the conductor pattern of the antenna element portion as viewed in planar view. The connecting portion is configured to electrically connect the conductor pattern of the antenna element portion to the conductor pattern of the short-circuiting portion. | 04-21-2016 |
20160093027 | IMAGE PROCESSOR AND IMAGE PROCESSING METHOD - A first edge strength calculation circuit calculates an edge strength of each pixel in the image on the basis of results of detection by the first edge detection circuit. A filter strength setting unit sets a filter strength of a two-dimensional lowpass filter for each pixel, on the basis of the edge strength calculated by the edge strength calculation circuit. A second edge strength calculation circuit calculates an edge strength of each pixel in the image, on the basis of results of detection by the second edge detection circuit. An enhancement strength setting circuit sets an edge enhancement strength of the edge enhancement filter for each pixel, on the basis of the edge strength calculate by the second edge strength calculation circuit. | 03-31-2016 |
20160065971 | IMAGE CODING APPARATUS - It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part ( | 03-03-2016 |
20160035098 | STATE ESTIMATION APPARATUS, STATE ESTIMATION METHOD, AND INTEGRATED CIRCUIT - The purpose of the present invention is to provide a state estimation apparatus that appropriately estimates the internal state of an observation target by determining likelihoods from a plurality of observations. An observation obtaining unit of the state estimation system obtains, at given time intervals, a plurality of observation data obtained from an observable event. The observation selecting unit selects a piece of observation data from the plurality of pieces of observation data obtained by the observation obtaining unit based on a posterior probability distribution data obtained at a preceding time t−1. The likelihood obtaining unit obtains likelihood data based on the observation data selected by the observation selecting unit and predicted probability distribution data obtained through prediction processing using the posterior probability distribution data. The posterior probability distribution estimation unit estimates posterior probability distribution data representing a state of the observable event based on the predicted probability distribution data obtained by the likelihood obtaining unit and the likelihood data. The prior probability distribution output unit outputs prior probability distribution data based on the posterior probability distribution data estimated by the posterior probability distribution estimation unit as prior probability distribution data at a next time t+1. | 02-04-2016 |
20160028379 | CLOCK GENERATOR - A clock generator comprises a voltage controlled oscillator including a ring oscillator which has a plurality of differential inverter circuits connected in a ring shape, and a phase controller to control an output of a differential inverter circuit which belongs to a second group, in a first state or a second state, for a predetermined time period. The differential inverter circuit which belongs to the second group is distinct from a differential inverter circuit which belongs to a first group. The differential inverter circuit which belongs to the second group, in the first state, outputs a first logic signal from a first differential output terminal and outputs a second logic signal from a second differential output terminal. Further, the differential inverter circuit which belongs to the second group, in the second state, outputs the second logic signal from the first differential output terminal and outputs the first logic signal from the second differential output terminal. | 01-28-2016 |
20160005287 | LOST CHILD SEARCH SYSTEM, RECORDING MEDIUM, AND LOST CHILD SEARCH METHOD - In a lost child search system including a parent terminal and a child terminal, the child terminal is provided with: a gyro sensor that measures the angular velocity for identifying the posture of that child terminal; an acceleration sensor that measures the acceleration of that child terminal; a positioning control unit that performs relative positioning of that child terminal based on the identified posture and the measured acceleration; a communication unit that performs data communication via near-field wireless communication using radio waves; an intensity detection unit that detects the radio wave intensity in the near-field wireless communication with the parent terminal; and an intensity decision unit that decides whether or not search for the child terminal is necessary in accordance with the detected intensity information. The acceleration sensor is made to start measuring the acceleration in accordance with the decision result (decision information) by the intensity decision unit. | 01-07-2016 |
20150379777 | AUGMENTED REALITY PROVIDING SYSTEM, RECORDING MEDIUM, AND AUGMENTED REALITY PROVIDING METHOD - An augmented reality providing system is provided with: a group of sensors measuring information on movement; a storage device that stores the reference position of the group of sensors; a card control unit that decides whether or not the group of sensors is located at the reference position; a position and posture identification unit that, after decision by the card control unit that the group of sensors is located at the reference position, identifies the current position of the group of sensors based on the reference position stored in the storage device and the information on the movement measured by the group of sensors; and a display unit that outputs output information in accordance with the current position of the group of sensors identified by the position and posture identification unit, thereby representing augmented reality. | 12-31-2015 |
20150302258 | OBJECT DETECTION DEVICE - An object detection device detects an object being recognized (such as a pedestrian) in a frame image, and identifies an area where a detected object which is detected in the frame image is present. A frame image is input after the frame image. The object detection device detects the object being recognized in the frame image, and identifies an area where a detected object which is detected in the frame image is present. When a distance from center coordinates of the area to center coordinates of the area smaller than a reference distance, the object detection device determines that the detected object which is detected in the frame image identical to the detected object which is detected in the frame image. | 10-22-2015 |
20150281508 | DATA PROCESSOR AND DATA PROCESSING METHOD - A plurality of pieces of first input data are input to a first decision circuit in an order based on a first rule. The memory has a plurality of first memory areas that respectively store a plurality of pieces of first data that match at least part of the plurality of pieces of first input data. The first decision circuit compares the first data read from the memory with the first input data to be input. When they do not match each other, The first decision circuit compares the first data with the first input data to be input next. When they match, The first decision circuit compares the first data read next from the memory on the basis of the first read pointer incremented with the first input data to be input next. | 10-01-2015 |
20150280663 | SEMICONDUCTOR CIRCUIT AND AMPLIFIER CIRCUIT - An amplifier circuit outputs a control signal for controlling a control target circuit and receives input of a feedback signal from the control target circuit. The amplifier circuit and the control target circuit constitute a feedback loop that includes a plurality of poles. A semiconductor capacitive element is provided for phase compensation in the feedback loop. The amplifier circuit includes an output branch that includes a first transistor having a first current terminal from which the control signal is output and a second current terminal connected to a power supply potential, and a branch that is connected in parallel to the output branch and includes a cascode circuit. The cascode circuit includes a second transistor having third and fourth current terminals, and a third transistor having fifth and sixth current terminals. The fourth and fifth current terminals are connected to each other. The semiconductor capacitive element that obtains the Miller effect is connected between the control target circuit and the fourth and fifth current terminals. | 10-01-2015 |
20150279445 | METHOD AND APPARATUS FOR DATA CAPTURE IN DDR MEMORY INTERFACE - A method for data acquisition in a memory system includes oversampling a data signal and a strobe signal with a multiphase clock having n phases to generate a series of data signals and a series of strobe signals representing a first data series and a first strobe series respectively, generating a second strobe series by edge detection of the first strobe series followed by retiming of the edge detected series, generating a third strobe series by edge adjustment of the second strobe series, wherein the edge adjustment ensures that there are no overlapping edges among the signals of the third strobe series, generating a sample selected series by linear shifting of each signal of the third strobe series by n/2, generating a second data series by retiming the first data series, generating a third data series by sample adjustment of the second data series, wherein the sample adjustment ensures that the third data series is in synchronization with a sampling window of the sample selected series, and determining a final data signal by multiplexing the third data series with the sample selected series. | 10-01-2015 |
20150278601 | STATE ESTIMATION APPARATUS, STATE ESTIMATION METHOD, AND INTEGRATED CIRCUIT - A state estimation apparatus appropriately estimates the internal state of an observation target by calculating a likelihood from observation data, and tracks, for example, multiple objects in a moving image and detects a new object and adds the object as a tracking target in an appropriate manner. A labeling unit detects a closed area from an observation image, and adds a label number to the closed area to generate a label image. A likelihood obtaining unit generates an object-erased image for new object detection by erasing image areas corresponding to all the currently-tracked objects. The apparatus performs the process for detecting a new object using the object-erased image for new object detection based on label numbers. The apparatus is appropriately prevented from erroneously determining that an area of the object-erased image for new object detection corresponding to the currently-tracked object and remaining after the erasure corresponds to a new object. | 10-01-2015 |
20150278424 | SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE - A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer. | 10-01-2015 |
20150278113 | DATA TRANSFER CONTROL DEVICE AND MEMORY-CONTAINING DEVICE - An image processing module input/output port in a DMAC includes an input part which receives second address information and an addressing request signal from an image processing module and an output part which outputs a reply signal indicating valid reception of the second address information to the image processing module. The image processing module input/output port can perform signal input/output control processing of returning, in response to the addressing request signal, the reply signal indicating confirmation of valid reception of the second address information to the image processing module when valid reception of the second address information is confirmed. A memory access controller performs memory access processing of accessing a storage area to be accessed in a memory based on the first address information (=the second address information) received via the image processing module input/output port. | 10-01-2015 |
20150277928 | SIMD PROCESSOR - A SIMD processor with a versatile hardware configuration performs efficient range determination that is frequently used in image processing and recognition. A SIMD processor includes a range determination arithmetic unit including first and second registers that can store two values. The SIMD processor uses three values, namely, these two values and the value of source data input from a register file unit, to flexibly set the processing target data for range determination and the two boundaries defining the processing target range of the range determination. | 10-01-2015 |
20150277909 | VLIW PROCESSOR - A very long instruction word (VLIW) processor performs efficient processing including extended bits operations, such as processing performed in response to instructions commonly used in image processing, image recognition, and other processing, while preventing scaling up of the circuit. The VLIW processor includes an instruction control unit, a register file unit, and an instruction execution unit. The instruction execution unit includes a plurality of slots, and a state register arranged between the second slot and the third slot to transfer N-bit data between the second and third slots. The VLIW processor stores data output from the third slot into the state register and uses the data, and thus achieves efficient processing including bit-expanded operations, such as processing performed in response to instructions commonly used in image processing, image recognition, and other processing, while preventing scaling up of the circuit. | 10-01-2015 |
20150277776 | DATA STORAGE CONTROL APPARATUS AND DATA STORAGE CONTROL METHOD - A compressed data generator compresses, by using a lossless compressor and a lossy compressor, image data in units of first blocks to generate a plurality of types of compressed data. A selector performs selection processing in units of second blocks each including a predetermined number N of first blocks, where N is an integer of 1 or more. The selection processing involves determining whether each of the plurality of types of compressed data satisfies a selection condition and selecting one piece of compressed data that satisfies the selection condition. The selection condition includes a data size condition that a data size of all the first blocks included in the second block is less than or equal to a predetermined value, and a data accuracy condition that information maintaining accuracy is highest among compressed data that satisfy the data size condition. | 10-01-2015 |
20150277470 | CURRENT MIRROR CIRCUIT AND RECEIVER USING THE SAME - A current mirror circuit that amplifies a reference current generated by a current source at a first magnification to supply a mirror current to a load circuit. The current mirror circuit includes a first transistor and a second transistor that share a power supply, and a drain potential mirror unit that amplifies the reference current at a second magnification to generate a first current, that amplifies a generated first current at a third magnification to generate a second current, and that supplies a predetermined potential determined based on the second current to a drain of the second transistor. The mirror current is supplied from the second transistor to the load circuit based on a potential of a gate of the first transistor determined based on the reference current | 10-01-2015 |
20150269072 | SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR READING INSTRUCTIONS - A system-in-package semiconductor device with a CPU, a first flash memory configured to store first instructions to be executed by the CPU, and a second flash memory configured to store second instructions to be executed in accordance with a predetermined control instruction included in the first instructions. The semiconductor device determines, prior to the CPU executing the instruction, whether an instruction read out from the first flash memory is a branch instruction, and if it is determined to be the branch instruction, causes the second flash memory to perforin read-out operation using a branch destination address value indicated by the branch instruction, and if a value of a program counter of the CPU matches the branch destination address value, while the second flash memory is in a state of being ready for read-out operation in accordance with the instruction, starts reading out the second instructions from the second flash memory. | 09-24-2015 |
20150262363 | OBJECT DETECTION APPARATUS - In an object detection apparatus ( | 09-17-2015 |
20150262340 | IMAGE PROCESSOR - A setting circuit sets a quantization value per input image on the basis of a noise value of the whole input image, and a quantization circuit performs quantization on first image data to generate second image data. Quantization value based on the noise value the whole input image can realize appropriate denoising depending on the noise level of the whole input image. | 09-17-2015 |
20150243169 | TRAFFIC LANE SITUATION DETERMINING DEVICE AND METHOD FOR DETERMINING TRAFFIC LANE SITUATION - A technique of determining the situation of a traffic lane. A traffic lane situation determining device includes a camera that is mounted in a vehicle and obtains an image whose object is a road in a travelling direction of the vehicle, a straight line detecting section that extracts a plurality of lines defining a traffic lane of the road from the image to detect a plurality of straight lines that respectively approximate the plurality of lines, an intersection identifying section that identifies an intersection of extended lines respectively obtained by extending the plurality of straight lines, and a traffic lane situation determining section that compares a location of the intersection with a location of a point at infinity preset in the image to determine a situation of the traffic lane. | 08-27-2015 |
20150237375 | MOVING IMAGE CODING APPARATUS, MOVING IMAGE CODING METHOD, STORAGE MEDIUM, AND INTEGRATED CIRCUIT - A moving image coding apparatus performs efficient moving image compression on video with much noise (with a poor S/N ratio), and enables appropriate bit rate control (code amount control). A first orthogonal transform unit performs orthogonal transform of an input moving image. A complexity obtaining unit obtains a complexity of the input moving image based on frequency component data obtained through orthogonal transform by the first orthogonal transform unit. A noise determination unit determines noise in the input moving image based on the frequency component data obtained through orthogonal transform by the first orthogonal transform unit. A code amount adjustment unit generates a code amount adjustment signal based on the complexity obtained by the complexity obtaining unit and the noise determination result obtained by the noise determination unit. A coding unit subjects the input moving image to a coding process including quantization using a quantization parameter value determined based on the code amount adjustment signal generated by the code amount adjustment unit. | 08-20-2015 |
20150237349 | TRANSCODER - If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate S | 08-20-2015 |
20150237314 | PIXEL INTERPOLATION APPARATUS, IMAGING APPARATUS, PIXEL INTERPOLATION PROCESSING METHOD, INTEGRATED CIRCUIT, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM - A pixel interpolation apparatus, an imaging apparatus, a program, and an integrated circuit allow appropriate pixel interpolation processing on an image signal obtained by a single-chip image sensor having a WRGB color filter array. An imaging apparatus includes an imaging unit, a signal processing unit, and a pixel interpolation processing unit. The apparatus calculates a degree of correlation for pairs in two orthogonal directions for an image signal (Raw image) obtained by the imaging unit including a single-chip image sensor having a WRGB color filter array using pixel data in an area around a target pixel, using the correlation degree as a determination criterion in the interpolation processing. The imaging apparatus selectively uses a luminance signal generated from R, G, and B-component signals or a luminance signal generated from a W-component signal to perform pixel interpolation processing with higher accuracy and obtain a YCbCr signal with higher accuracy. | 08-20-2015 |
20150235631 | PORTABLE TERMINAL DEVICE, PROGRAM, DEVICE SHAKE COMPENSATION METHOD, AND CONDITION DETECTION METHOD - A portable terminal device operable by an operator is provided with a display unit which displays display data, an image capturing unit and an image signal processing unit which acquire image data containing the face of the operator, a detection unit which detects a relative positional change between the display data displayed on the display unit and the face of the operator based on the acquired image data to create change data, a determination unit which determines whether or not the operator is walking, and a display control unit which, in a case where the determination unit has determined that the operator is walking, controls a displaying position in the display unit of the display data displayed on the display unit so that the relative positional change detected by the detection unit is suppressed. | 08-20-2015 |
20150235382 | PIXEL INTERPOLATION APPARATUS, IMAGING APPARATUS, PIXEL INTERPOLATION PROCESSING METHOD, INTEGRATED CIRCUIT, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM - An imaging apparatus includes an imaging unit, a signal processing unit, and a pixel interpolation processing unit. The apparatus calculates a correlation degree for pairs in two orthogonal directions for an image signal obtained by the imaging unit including a single-chip image sensor having a four-color filter, such as a WRGB color filter, using pixel data in an area around a target pixel, using the correlation degree as a determination criterion in the interpolation. When a color component pixel with an identical color of a color component pixel subjected to pixel interpolation is not located in the direction having the high correlation, the pixel interpolation apparatus changes ratio in a direction orthogonal to the direction having the high correlation by using a pixel value resulting from color space conversion in the direction orthogonal to the direction having the high correlation, and performs pixel interpolation based on the change ratio. | 08-20-2015 |
20150222283 | CLOCK OPERATION METHOD AND CIRCUIT - In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules. | 08-06-2015 |
20150199799 | NOISE DETERMINATION APPARATUS AND METHOD, AND NOISE FILTER - A technique for determining noise is provided that suppresses misrecognition of significant components in an image as noise in any image captured under any condition. A noise determination apparatus for determining noise in image data that is input in units of frames decomposes the image data into frequency components, samples a predetermined number of data pieces for low-frequency components that have relatively low frequencies and a predetermined number of data pieces for high-frequency components that have relatively high frequencies from the frequency components, and analyzes whether or not the image data includes an edge image, on the basis of a ratio of high-frequency data to low-frequency data. | 07-16-2015 |
20150189288 | IMAGE PROCESSOR - An analyzing unit sets a threshold on the basis of a target compression ratio of a frame. The compression unit compresses a block having an attribute value larger than or equal to a threshold by applying a first compression format and a block having an attribute value smaller than the threshold by applying a second compression format having a higher compression ratio than the first compression format. | 07-02-2015 |
20150163495 | IMAGE CODING APPARATUS - In an image coding apparatus ( | 06-11-2015 |
20150156468 | PIXEL INTERPOLATION APPARATUS, IMAGE CAPTURE APPARATUS, STORAGE MEDIUM, AND INTEGRATED CIRCUIT - An image capture apparatus | 06-04-2015 |
20150146801 | COMMUNICATION NETWORK AND WIDE AREA COMMUNICATION NETWORK - A first communication device is connected in a conductive state to a first power line extending from a secondary side of a transformer in a high-voltage power receiving apparatus to a primary side of breakers in a plurality of distribution boards that receive power supply from the transformer. A plurality of second communication devices are respectively connected to a plurality of second power lines respectively extending from a secondary side of the breakers in the plurality of distribution boards. Each second communication device performs power line communication using the second power line connected thereto as a transmission path. Upon receipt of a communication signal, each of the first communication device and the plurality of second communication devices generates a new communication signal including information included in the communication signal and sends the new communication signal through power line communication. | 05-28-2015 |
20150102734 | LIGHT CONTROL SYSTEM, LIGHT CONTROL METHOD AND COMPUTER READABLE MEMORY - A plurality of lighting devices are respectively arranged, on a ceiling surface, at a plurality of grid points of the ceiling surface partitioned in a grid pattern. A detection unit detects occupancy statuses of a plurality of seats located correspondingly to positions of the plurality of grid points. A controller is capable of communicating with each of the plurality of lighting devices. The controller includes a light-control information generating unit that regards a block formed of a plurality of grid points centering around a grid point of an occupied location as one group to generate, for each of groups set correspondingly to occupied locations, light control information on a lighting device that becomes a dimming target in the group. The controller also includes a transmission unit that transmits the light control information. The lighting device being a dimming target among the plurality of lighting devices performs light control based on the received light control information. | 04-16-2015 |
20150088408 | PEDESTRIAN OBSERVATION SYSTEM, RECORDING MEDIUM, AND ESTIMATION OF DIRECTION OF TRAVEL - A pedestrian observation system includes a circuitry acquires an acceleration in accordance with a uniquely defined terminal coordinate system accompanying a pedestrian; obtains a power of an acceleration in a horizontal plane containing mutually perpendicular first and second directions based on acceleration components in the first and second directions, thereby acquiring an observation time of a maximum value of the power and acceleration components in the first and second directions at that time to acquire horizontal peak information; acquires times of observation of maximum and minimum values of a vertical acceleration component to acquire vertical peak information; chooses information on the maximum value of the power from the horizontal peak information based on the vertical peak information to acquire peak information for estimation; and acquires traveling direction information indicating a direction of travel of a pedestrian based on the peak information for estimation. | 03-26-2015 |
20150086136 | IMAGE SCALING PROCESSOR AND IMAGE SCALING PROCESSING METHOD - An image scaling processor includes: a coefficient computing circuit that calculates interpolation coefficients to be used in an image scaling process; a multiplier that multiplies input image data by the interpolation coefficients provided from the coefficient computing circuit such that the interpolation coefficients respectively correspond to input pixels constituting the input image data; an adder that iteratively adds pieces of multiplied data output from the multiplier and obtains a total sum of the pieces of multiplied data for a predetermined number of the input pixels; a selector that outputs a total sum of the multiplied data at a timing at which the total sum of the pieces of multiplied data is obtained for the predetermined number of the input pixels; and a shift circuit that shifts an output of the selector to adjust a bit count of the output image data to a bit count of the input image data. | 03-26-2015 |
20150078666 | OBJECT DETECTION APPARATUS AND STORAGE MEDIUM - Important information about an object is detected using less arithmetic processing. An object detection unit generates an edge image from a color image. The object detection unit evaluates symmetry of an image included in the edge image. The object detection unit identifies a symmetry center pixel forming an object having symmetry. The object detection unit detects an object width for each symmetry center pixel. The object detection unit identifies the width of the object in the vertical direction based on the width of the symmetry center pixels in the vertical direction, and identifies the width of the object in the horizontal direction based on the object width identified for each symmetry center pixel. | 03-19-2015 |
20150063470 | IMAGE ENCODING DEVICE - In an image encoding device, a variable-length encoder encodes a quantized macro blocks and generates encoded data. The variable-length encoder forcefully encodes an end macro block of a line group composed of macro block lines, as a non-skipped macro block. Each of macro blocks which are to be encoded subsequent to the end macro block is encoded as a non-skipped macro block until an amount of codes of the encoded data including the end macro block reaches the smallest unit of transmission of the transmission part. As a result, the encoded data including the end macro block is transmitted to the image decoding device by the smallest unit of transmission. | 03-05-2015 |
20150061505 | LUMINAIRE RECOGNITION DEVICE, LIGHTING SYSTEM, AND LUMINAIRE RECOGNITION METHOD - A luminaire recognition device in a lighting system having multiple luminaires with a dimming function installed in a predetermined area is configured to be arranged at a predetermined location in an area for associating identification information and installation site of each luminaire. The luminaire recognition device includes a controller configured to control an illuminance of each luminaire through communication, a detector configured to detect a brightness at the predetermined location, a memory configured to store correlation information between a brightness and distance from the predetermined location to each luminaire, and a processor configured to change an illuminance of a luminaire to be searched by a defined amount with the controller, calculate a change in brightness detected by the detector, and recognize the luminaire to be searched among the multiple luminaires, based on the change and the correlation information. | 03-05-2015 |
20150055825 | OBJECT DETECTION APPARATUS AND STORAGE MEDIUM - Important information about an object is detected using less arithmetic processing. An object detection unit generates an edge image from a color image. The object detection unit evaluates symmetry of an image included in the edge image by performing processing in accordance with the position of a target pixel. The object detection unit identifies a symmetry center pixel forming an object having symmetry. The object detection unit detects an object width for each symmetry center pixel. The object detection unit identifies the width of the object in the vertical direction based on the width of the symmetry center pixels in the vertical direction, and identifies the width of the object in the horizontal direction based on the object width identified for each symmetry center pixel. | 02-26-2015 |
20150042451 | POSITIONING SYSTEM, TERMINAL DEVICE, RECORDING MEDIUM, AND POSITIONING METHOD - A positioning system is provided with a cell phone, a ticket gate having a known absolute position, and a housing of the ticket gate which regulates a traveling direction of a user to be a reference direction. The cell phone is provided with a contactless IC card portion adapted to acquire individual information of the ticket gate, a position identification portion adapted to acquire the absolute position of the ticket gate in accordance with the individual information to identify an absolute position of the user, an acceleration sensor adapted to detect an acceleration, an angular velocity sensor adapted to detect an angular velocity, a calibration portion adapted to calibrate the acceleration sensor and the angular velocity sensor in accordance with detection results therefrom when the cell phone is substantially stationary, and an orientation identification portion adapted to identify an orientation in accordance with measured values of the acceleration sensor and the angular velocity sensor when the housing regulates the traveling direction of the user to be the reference direction. | 02-12-2015 |
20150030251 | OBJECT DETECTION APPARATUS AND STORAGE MEDIUM - Important information about an object is detected using less arithmetic processing. An object detection unit generates an edge image from a color image. The object detection unit evaluates symmetry of an image included in the edge image by performing processing in accordance with the position of a target pixel. The object detection unit identifies a symmetry center pixel forming an object having symmetry. The object detection unit detects an object width for each symmetry center pixel. The object detection unit identifies the width of the object in the vertical direction based on the width of the symmetry center pixels in the vertical direction, and identifies the width of the object in the horizontal direction based on the object width identified for each symmetry center pixel. | 01-29-2015 |
20150016750 | IMAGE PROCESSOR AND METHOD FOR MEMORY ACCESS CONTROL - An image processor includes a memory including multiple memory banks each having multiple unit storage areas and holding an image, an image processing unit that processes an image, and an access controller that controls an access from the image processing unit to the memory. In storing the image in the memory, the access controller splits the image in multiple groups of unit pixel data pieces including pixel data of multiple columns by multiple rows, and stores groups of unit pixel data pieces aligned in at least two columns in a pixel space in the same unit storage area in the same memory bank. | 01-15-2015 |
20150012968 | INFORMATION PROCESSING SYSTEM - The communication device sends an authentication code (N) to a semiconductor memory to instruct the semiconductor memory to authenticate the communication device. The semiconductor memory authenticates the communication device based on the authentication code (N), and if the communication device is determined to be valid, sends an authentication code (N+1) to the communication device to instruct the communication device to authenticate the semiconductor memory in response to the authentication code (N). The communication device authenticates the semiconductor memory based on the authentication code (N+1). | 01-08-2015 |
20140380119 | MEMORY CONTROLLER - An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data. | 12-25-2014 |
20140369562 | IMAGE PROCESSOR - An image processor includes an LSRAM accessible with a higher speed than a frame memory and configured to hold a second image in a predetermined range of a first image, an image production unit configured to read an image in a predetermined range of the second image and produce a third image for rough search based on the read image, an MSRAM accessible with a higher speed than the frame memory and configured to hold the third image, a first search unit configured to read the third image and perform first motion search based on the third image, and a second search unit configured to read a fourth image in a predetermined range of the second image based on a search result by the first search unit and perform second motion search that is more detailed than the first motion search based on the fourth image. | 12-18-2014 |
20140348437 | DATA STORAGE CONTROL APPARATUS, DATA STORAGE APPARATUS, DATA READOUT CONTROL APPARATUS, DATA STORAGE METHOD, COMPRESSION CIRCUIT, AND COMPRESSION METHOD - A data storage control apparatus includes a compression part that performs lossless compression for reducing a data amount on image data that is in units of blocks, a determination element for determining whether lossless compression is possible or not, and a storage control part that performs storage control for, if the determination element has determined that lossless compression is possible, causing data obtained through lossless compression to be stored as compressed data in a storage part, and if the determination element has determined that lossless compression is not possible, causing the image data in units of blocks to be stored in the storage part. | 11-27-2014 |
20140348435 | IMAGE PROCESSOR - In a high-speed mode, a software processing unit notifies a hardware processing unit of settings information about output pictures before the hardware processing unit starts to encode an input picture, and the hardware processing unit performs continuous encoding for the output pictures, based on the settings information notified of by the software processing unit, without a notification signifying a completion for every picture, and upon completion of encoding for all of a specified number of the output pictures, sends an interrupt notification signifying a completion of encoding to the software processing unit. | 11-27-2014 |
20140341375 | RANDOM NUMBER GENERATING DEVICE, CIPHER PROCESSING DEVICE, STORAGE DEVICE, AND INFORMATION PROCESSING SYSTEM - A random number generating device includes an uncertain circuit which outputs uncertain data, and a cipher processing device. The cipher processing device encrypts input data using a cipher function of the cipher processing device, and generates a random number including higher uniformity than data outputted from said uncertain circuit using the cipher function of the cipher processing device and the data outputted from the uncertain circuit. | 11-20-2014 |
20140334688 | IMAGE PROCESSOR - An image processor includes an LSRAM accessible with a higher speed than a frame memory and configured to hold a second image in a predetermined range of a first image, an image production unit configured to read an image in a predetermined range of the second image from the LSRAM and produce a third image for rough search based on the read image, an MSRAM accessible with a higher speed than the frame memory and configured to hold the third image produced by the image production unit, a search unit configured to read the third image from the MSRAM and perform first motion search based on the third image, and a search unit configured to read a fourth image in a predetermined range of the second image from the LSRAM based on a search result by the search unit and perform second motion search that is more detailed than the first motion search based on the fourth image. | 11-13-2014 |
20140328355 | COMMUNICATION SYSTEM, AND COMMUNICATION DEVICE - A communication device has a transmission/reception unit and a communication processing unit. The transmission/reception unit is configured to conform to a plurality of communication methods. The communication processing unit selects one of the plurality of communication methods with respect to each time slot based on device time in accordance with a predetermined selection rule, to perform communication via the transmission/reception unit by the selected communication method. The predetermined selection rule includes a random selection rule in which a communication method to be allocated to each time slot is selected at random out of the plurality of communication methods. | 11-06-2014 |
20140321769 | IMAGE PROCESSING APPARATUS HAVING A PLURALITY OF IMAGE PROCESSING BLOCKS THAT ARE CAPABLE OF REAL-TIME PROCESSING OF AN IMAGE SIGNAL - An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5H5 taps are connected in cascade in three stages, which enables low-pass filtering with 13H13 taps. | 10-30-2014 |
20140321745 | IMAGE PROCESSING APPARATUS HAVING A PLURALITY OF IMAGE PROCESSING BLOCKS THAT ARE CAPABLE OF REAL-TIME PROCESSING OF AN IMAGE SIGNAL - An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5H5 taps are connected in cascade in three stages, which enables low-pass filtering with 13H13 taps. | 10-30-2014 |
20140320693 | IMAGE PROCESSING APPARATUS HAVING A PLURALITY OF IMAGE PROCESSING BLOCKS THAT ARE CAPABLE OF REAL-TIME PROCESSING OF AN IMAGE SIGNAL - An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5H5 taps are connected in cascade in three stages, which enables low-pass filtering with 13H13 taps. | 10-30-2014 |
20140320522 | IMAGE PROCESSING APPARATUS HAVING A PLURALITY OF IMAGE PROCESSING BLOCKS THAT ARE CAPABLE OF REAL-TIME PROCESSING OF AN IMAGE SIGNAL - An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5H5 taps are connected in cascade in three stages, which enables low-pass filtering with 13H13 taps. | 10-30-2014 |
20140314073 | COMMUNICATION SYSTEM, AND COMMUNICATION DEVICE - A communication device has a transmission/reception unit and a communication processing unit. The transmission/reception unit is configured to conform to a plurality of communication methods. The communication processing unit selects one of the plurality of communication methods with respect to each time slot based on device time in accordance with a predetermined selection rule, to perform communication via the transmission/reception unit by the selected communication method. In time synchronization master processing, a first communication device gives device time of the device itself as a time stamp to a time synchronization request signal and transmits the time synchronization request signal. In time synchronization slave processing, a second communication device receives the time synchronization request signal and calibrates the device time of the device itself based on the time stamp in the time synchronization request signal. | 10-23-2014 |
20140307972 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - A WT unit performs wavelet transformation on original image data to generate first image data. An ROI developing unit, based on ROI information, specifies an ROI corresponding portion corresponding to an ROI and a non-ROI corresponding portion corresponding to a non-ROI to the first image data. A high-frequency cutting unit performs, on the first image data, a high-frequency cutting process that cuts a high-frequency component of the non-ROI corresponding portion. A low-frequency blurring unit performs, on the first image data, a low-frequency blurring process that blurs a low-frequency component of the non-ROI corresponding portion. The IWT unit performs inverse wavelet transformation on second image data (first image data obtained after the high-frequency cutting process and the low-frequency blurring process are performed) to generate third image data. | 10-16-2014 |
20140294309 | OBJECT DETECTION APPARATUS - In an object detection apparatus | 10-02-2014 |
20140294293 | IMAGE PROCESSING CIRCUIT AND IMAGE DETECTION DEVICE - Each second selection circuit selects, out of a plurality of evaluation values, an evaluation value being in a predetermined relative positional relation with a first evaluation value as an evaluation value outputted from a first selection circuit, and outputs the selected value. The predetermined relative positional relations are different from one another among a plurality of second selection circuits. Every time a second evaluation value is outputted from the second selection circuit corresponding to the integration circuit, the integration circuit reads a weigh value corresponding to a combination of the second evaluation value and the first evaluation, which makes a pair with the second evaluation and is outputted from the first selection circuit, from a storage circuit corresponding to the second selection circuit and integrates the read values. An addition circuit at least adds a plurality of integrated values outputted from a plurality of integration circuits, and an addition value obtained thereby becomes a probability value. | 10-02-2014 |
20140294098 | IMAGE PROCESSOR - In the multi mode, the software processing unit notifies the hardware processing unit by batch of multiple settings information sets about multiple output pictures before the hardware processing unit starts to encode an input picture, and the hardware processing unit performs continuous encoding for the output pictures, based on the settings information sets notified of by the software processing unit, without a notification signifying a completion for every picture, and upon completion of encoding for all of the output pictures, sends an interrupt notification signifying a completion of encoding to the software processing unit. | 10-02-2014 |
20140286532 | HUMAN DETECTION DEVICE - In a human detection device | 09-25-2014 |
20140286435 | IMAGE PROCESSOR - The image processor includes a ⅓ multiplier circuit that approximately multiplies an input value X by ⅓. The ⅓ multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register. | 09-25-2014 |
20140247987 | OBJECT DETECTION APPARATUS, STORAGE MEDIUM, AND INTEGRATED CIRCUIT - It is an object of the present invention to achieve an object detection apparatus, a program, and an integrated circuit each of which is capable of appropriately detecting an axially symmetric object in an image, whatever image is to be processed, without performing any complicated thresholding. The object detection apparatus includes a processing object region determination unit, a variance acquisition unit, a matching determination unit, and an object region detection unit. The processing object region determination unit sets a symmetry axis in an image region included in an image and divides the image region into a determination image region and a reference image region so as to be line symmetric with respect to the symmetry axis. The variance acquisition unit acquires a degree of variance of image feature amount in the image region. The matching determination unit acquires a matching value between the determination image region and the reference image region and determines the symmetry between the determination image region and the reference image region with respect to the symmetry axis on the basis of a corrected matching value which is obtained by correcting the acquired matching value in accordance with the degree of variance. The object region detection unit detects an image region which is line symmetric with respect to the symmetry axis on the basis of a determination result from the matching determination unit. | 09-04-2014 |
20140246588 | OPTICAL POSITION DETECTION DEVICE - The optical position detection device includes a light irradiation unit that irradiates a target object with light, and a light receiving unit that receives reflected light from the target object. The light receiving unit includes a segmented photodiode in which a light receiving surface is two-dimensionally segmented into a plurality of light receiving regions, the segmented photodiode outputting a current corresponding to the intensity of light received by each of the light receiving regions; a light receiving lens that condenses the reflected light from the target object and forms an image of the target object on the light receiving surface of the segmented photodiode; and an arithmetic unit that detects a position of the target object in a two-dimensional direction orthogonal to the optical axis of the light receiving lens, based on the output currents corresponding to the respective light receiving regions of the segmented photodiode. | 09-04-2014 |
20140219504 | OBJECT DETECTION DEVICE - It's an object of the invention to provide an object detection device capable of detecting an object for detection in an input image with high precision. In an object detection device | 08-07-2014 |
20140198862 | COMMUNICATION DEVICE AND COMMUNICATION SYSTEM - A transmitter includes a generation section that generates a baseband OFDM signal based on transmission data, and a transmission section that transmits a communication signal that is based on a real-part signal that is obtained by removing an imaginary-part signal from the baseband OFDM signal. In the baseband OFDM signal, the data signal including the transmission data is superimposed on subcarriers that are given numbers equal to or less than N/2−1, and the data signal is not superimposed on subcarriers that are given numbers more than N/2−1, where N (N is an integer) subcarriers included in the baseband OFDM signal are numbered by integers from 0 to N−1 in ascending order with respect to the center frequency of each subcarrier. | 07-17-2014 |
20140193096 | LINE SEGMENT AND ARC DETECTION APPARATUS - An apparatus and method to detect a line segment or arc using Hough transform. A Hough transform unit performs contour extraction on brightness image data to generate contour image data, with pixels having a pixel value of 0 to 255, performs the Hough transform on points in the contour image data, and counts additional values represented by pixel values of points in the contour image data in a Hough table. The Hough transform unit performs contour extraction on first to third component data to generate first to third contour data with pixels having a pixel value of 0 to 255, performs the Hough transform on points in the first to third contour data, and counts additional values represented by pixel values of points in the first to third contour data in the Hough table. The detection unit comprehensively evaluates the counts to detect a line segment or arc. | 07-10-2014 |
20140192864 | MOVING IMAGE CODING APPARATUS, CODE AMOUNT CONTROL METHOD, AND STORAGE MEDIUM - A moving image coding apparatus, a code amount control method, and a code amount control program enable appropriate code amount control to be performed in units shorter than frames. The moving image coding apparatus includes a coding unit, a quantization parameter determination unit, and a target code amount setting unit. The target code amount setting unit designates the number of macroblocks and sets a target code amount as a code amount to be allocated to the designated number of macroblocks. The quantization parameter determination unit calculates, for each macroblock, a quantization parameter to be used in quantization of a current macroblock based on a sum of absolute transformed differences SATD used in a motion estimate process. The moving image coding apparatus performs quantization using the calculated quantization parameter value. | 07-10-2014 |
20140169631 | IMAGE RECOGNITION APPARATUS - An image recognition apparatus determines whether an image of a pedestrian is captured in a frame of video data captured by a vehicle mounted camera. A pre-processing unit determines a detection block from within a frame, and cuts out block image data corresponding to the detection block from the frame. Block data with a predetermined size that is smaller than the size of the detection block is created from the block image data. A neuro calculation unit executes neuro calculation on the block data, and calculates an output synapse. A post-processing unit determines whether a pedestrian exists within the detection block on the basis of the output synapse. When a pedestrian is detected, the post-processing unit creates result data, which is obtained by superimposing the detection block within which the pedestrian was detected onto the frame. | 06-19-2014 |
20140167820 | PHASE COMPARISON DEVICE AND DLL CIRCUIT - A phase detection range is enabled to be expanded to an arbitrary number of times of a cycle of a reference clock, and in the case of application to a DLL circuit, an operation cycle is enabled to be freely selected. A phase comparison device includes a divider that generates a division clock obtained by receiving a reference clock and dividing it by two; an inverter that inverts a phase of the division clock to generate a division inverted clock; a DFF circuit that synchronizes the division inverted clock with a delay clock to generate a synchronized clock; a DFF circuit that synchronizes the clock with the feedback clock to generate a final synchronized clock; and a phase comparator that receives the division clock and the final synchronized clock to compare phases of the division clock and the final synchronized clock. | 06-19-2014 |
20140161349 | STRAIGHT LINE DETECTION APPARATUS AND STRAIGHT LINE DETECTION METHOD - To detect a straight line using the Hough transform taking into consideration not only the number of points but also other properties of the straight line, the Hough transform unit performs a Hough transform on contour-enhanced binary image data. The Hough table stores a count after the Hough transform. The adjustment unit adjusts the count. The straight line detection unit detects a straight line based on the adjusted count. Additionally, to detect a straight line, independent of its direction or location in the image, for each straight line in the binary image data, the straight line calculation unit determines the intersections where that straight line cuts up the binary image data to calculate the intersection distance. The normalization unit divides the count stored in the Hough table by the intersection distance to normalize the count. The straight line detection unit detects a straight line based on the normalized count. | 06-12-2014 |
20140161184 | MOVING IMAGE CODING APPARATUS, CODE AMOUNT CONTROL METHOD, AND STORAGE MEDIUM - A moving image coding apparatus, a code amount control method, and a code amount control program enable appropriate code amount control to be performed in units shorter than frames. The moving image coding apparatus includes a coding unit, a quantization parameter determination unit, and a target code amount setting unit. The target code amount setting unit designates the number of macroblocks and sets a target code amount as a code amount to be allocated to the designated number of macroblocks. The quantization parameter determination unit calculates, for each macroblock, a quantization parameter to be used in quantization of a current macroblock based on a sum of absolute transformed differences SATD used in a motion estimate process. The moving image coding apparatus performs quantization using the calculated quantization parameter value. | 06-12-2014 |
20140160915 | COMMUNICATION DEVICE AND COMMUNICATION SYSTEM - A preamble signal is an OFDM signal, and is a real-part signal obtained by removing an imaginary-part signal from a signal in the time domain that is generated by an IFFT process being performed on a signal in the frequency domain obtained by assigning preamble data to subcarriers in accordance with a predetermined arrangement pattern. The predetermined arrangement pattern indicates that preamble data is assigned to any of subcarriers given numbers equal to or less than N/2−1 and the preamble data is not assigned to subcarriers given numbers more than N/2−1, where a plurality of subcarriers are numbered by integers from 0 to N−1 (N is an integer) in ascending order with respect to the center frequency of each subcarrier. | 06-12-2014 |
20140154974 | COMMUNICATION SYSTEM, AND COMMUNICATION DEVICE - A communication system includes information acquisition devices having facility information and an information collection device for collecting the facility information from the information acquisition devices. The information collection device requests the information acquisition devices to send the facility information by using the first communication unit and the second communication unit of the information collection device. Each of the information acquisition devices includes a communication scheme specifying section for specifying which one of the first communication unit and the second communication unit in each of the information acquisition devices has first received the request to send from the information collection device, and a communication control section for making a reply to the request to send by using the communication unit specified by the communication scheme specifying section. | 06-05-2014 |
20140152868 | IMAGING DEVICE, IMAGE STORING METHOD, AND RECORDING MEDIUM FOR PROCESSING IMAGE CAPTURING LOCATION INFORMATION - An imaging device for capturing an image of a subject to acquire captured-image information, comprises: a positioning element to measure a location at which the image is captured and to acquire capturing location information indicating a capturing location when the captured-image is acquired; a creation element to create image information based on the acquired capturing location information; a memory element to store the created image information; a decision element to, when the image information stored in the memory element is output to outside, decide whether the capturing location information included in the image information is to be kept secret; and a fabricator element to fabricate the capturing location information included in the image information based on a result of the decision by the decision element. | 06-05-2014 |
20140112393 | IMAGE PROCESSING DEVICE - An image processing device includes: a first storage unit to store image data containing pixel data about a plurality of components of each pixel arranged according to a first rule; a second storage unit having a plurality of storage areas to individually store the image data read from the first storage unit; a process controller to control reading of the image data from the first storage unit to the second storage unit and to output a control signal containing information used to designate a specific storage area being one of the storage areas; a multiplexer to output pixel data in order according to a second rule by selecting, based on the control signal, pixel data stored in the specific storage area from pixel data stored in the storage areas; and a 4-tap filter to calculate pixel information about an interpolated pixel. | 04-24-2014 |
20140105614 | METHOD AND APPARATUS FOR RECEIVING BURST DATA WITHOUT USING EXTERNAL DETECTION SIGNAL - Apparatus and method for receiving burst data signal without using external detection signal are disclosed. The apparatus can include a clock data recovery (CDR) circuit to generate a clock signal, and a detection circuit to detect an initial portion in the data recovered from the input signal. The CDR circuit can have a first mode that attempts to synchronize the clock signal with a reference data signal, and a second mode that attempts to synchronize the clock signal with the burst data signal and to recover data based on the clock signal. The apparatus can include a controller to conduct a process including, in sequence, setting the CDR circuit in the first mode, setting the CDR circuit in the second mode, and keeping the CDR circuit in the second mode when the detection circuit detects the initial portion in the recovered data. | 04-17-2014 |
20140093001 | COMMUNICATION SYSTEM, COMMUNICATION DEVICE, AND METHOD FOR OPERATING COMMUNICATION SYSTEM - A communication system according to the present invention comprises a first communication device and a second communication device for performing power line communication using a power line as a transmission line with the first communication device, and in the communication system, the first communication device has a detection means for detecting a zero crossing timing of a commercial power supply and a transmitting means for transmitting a transmission signal modulated in OFDM mode at the zero crossing timing, the transmitting means first transmits a header signal (HS) having a preamble as the transmission signal when the power line communication is started, and the transmitting means transmits a data signal (DS) having no preamble as the transmission signal after the header signal (HS) is transmitted, and the second communication device has a receiving means for performing a demodulation process on the transmission signal which is received, to thereby obtain receive data. | 04-03-2014 |
20140092802 | COMMUNICATION SYSTEM - The purpose of this invention is to provide a technique for preventing collisions between a numerous response packets generated in broadcast communication. A communication device (A | 04-03-2014 |
20140079120 | MOVING IMAGE CODING APPARATUS AND MOVING IMAGE CODING METHOD - Moving images are coded with reduced deterioration in the image quality while variations in the amount of code per frame are being reduced. A moving image coding apparatus includes a remaining picture number obtaining unit, an activity calculation unit, an intra MB determination unit, and a coding unit. The remaining picture number obtaining unit detects the temporal position of the current frame image, and determines the reset timing at which an intra refresh process is reset in a manner that the reset timing differs for each macroblock line (MBL). The activity calculation unit calculates an activity value for each macroblock (MB). The intra MB determination unit determines a MB to be set as an intra MB based on the activity value calculated by the activity calculation unit. The coding unit codes the MB set as an intra MB through an intra coding process. | 03-20-2014 |
20140064744 | RECEPTION DEVICE - A first phase setting circuit generates a first phase setting signal. A first synchronous signal generator generates a first synchronous clock signal having a phase set by the first phase setting signal from a multi-phase local clock signal. By removing a phase fluctuation component representing phase fluctuation of the reception data signal from a first signal including a frequency component representing a frequency offset between a multi-phase local clock signal and a reception data signal and the phase fluctuation component, a second generation unit generates a second signal including the frequency component. The first phase setting circuit updates the first phase setting signal according to the second signal. | 03-06-2014 |
20140062568 | OUTPUT BUFFER CIRCUIT - A differential output buffer includes first and third switches and second and fourth switches which are connected in series respectively between a first voltage source and a current source, and a replica circuit includes a second voltage source which is equivalent to a first voltage source. A current control circuit controls a current flowing to the current source in such a manner that a voltage of a third node between two resistive elements connected in series between a first node between the first and third switches and a second node between the second and fourth switches and having an equal resistance value is equal to a reference voltage, for example, and a voltage control circuit generates a control signal in such a manner that a voltage of any node excluding an output terminal of the second voltage source in the current path is equal to a second reference voltage. | 03-06-2014 |
20140044371 | DATA STORAGE CONTROLLING DEVICE, DATA READING CONTROLLING DEVICE, AND DATA STORING METHOD - A data storage controlling device has: a compression unit which performs lossless compression on each compression object region; determination means which determines whether or not the lossless compression is possible in each compression determination region including a plurality of compression object regions; and a storage control unit which performs storage control in each compression determination region in such a manner that data after the lossless compression in a compression determination region is stored as compressed data into a storage unit when it is determined that the lossless compression in each compression object region included in the certain compression determination region is possible, and image data before the lossless compression in the certain compression determination region is stored into the storage unit when it is determined that the lossless compression in each compression object region included in the certain compression determination region is impossible. | 02-13-2014 |
20140043343 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING INTERFACE CIRCUIT - An image processing apparatus includes a plurality of image processing module parts, a module arbiter part, and a DMAC (Direct Memory Access Controller) part. Each of the image processing module parts includes a module core for executing a predetermined image processing. The plurality of image processing module parts is connected to the module arbiter part. The module arbiter part arbitrates memory access which is given by the plurality of image processing module parts through a bus. The DMAC part is connected between the module arbiter part and the bus, and executes memory access related to the arbitration result obtained by the module arbiter part. | 02-13-2014 |
20140003664 | DATA PROCESSOR, DATA PROCESSING SYSTEM, AND COMPUTER-READABLE RECORDING MEDIUM | 01-02-2014 |
20130336593 | IMAGE CODING APPARATUS - In an image coding apparatus ( | 12-19-2013 |
20130322533 | ENCODING DEVICE - A coding device that achieves reduction in a circuit size and in the number of processing cycles is obtained. A coding device includes a first arithmetic unit that calculates a first difference value between an input image and a predicted image with respect to each of blocks having a first block size included in a macroblock to be coded, and a second arithmetic unit that calculates a second difference value between an input image and a predicted image for each of blocks having a second block size larger than the first block size included in the macroblock, and a prediction mode determination unit that determines a prediction mode to be applied to the macroblock, based on the first difference values of the macroblock calculated by the first arithmetic unit and the second difference values of the macroblock calculated by the second arithmetic unit. | 12-05-2013 |
20130315266 | SNR IMPROVEMENT CIRCUIT, SYNCHRONIZATION INFORMATION DETECTION CIRCUIT, COMMUNICATION DEVICE, SNR IMPROVEMENT METHOD, AND SYNCHRONIZATION INFORMATION DETECTION METHOD - A technique capable of improving a packet catch rate when applied to a communication device, for example. An SNR improvement circuit for improving an SNR of an input signal includes a delay unit for delaying the input signal to generate one or more delay signals, and an adder for adding the one or more delay signals and the input signal before being delayed. The input signal contains a periodic signal in which the same signal is repeated a predetermined number of times with a predetermined period. The delay unit generates the one or more delay signals with delay time which is α times (α is a natural number, and is set at different values with respect to two or more delay signals) longer than the predetermined period. | 11-28-2013 |
20130300898 | IMAGE PROCESSING APPARATUS HAVING A BUFFER MEMORY FOR IMAGE DATA STORAGE - Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption. | 11-14-2013 |
20130300756 | IMAGE PROCESSING APPARATUS HAVING A BUFFER MEMORY FOR IMAGE DATA STORAGE - Two local buffers are provided between an image processing unit and an image compression and expansion unit for compression into a predetermined format. Write and read control units serve to alternately use the two local buffers. As a result, process flow starting from the image processing unit to generate compressed image data by the image compression and expansion unit requires no main memory, whereby high-speed image processing is allowed with low power consumption. | 11-14-2013 |
20130259108 | COMMUNICATION SYSTEM, COMMUNICATION DEVICE, AND METHOD FOR OPERATING COMMUNICATION SYSTEM - A communication system includes a first communication device and a second communication device that performs power line communication with the first communication device via an electric power line, wherein the first communication device transmits an initial packet signal added with an error detection code in each zero crossing period including zero crossing timing while changing transmission timing within the zero crossing period. The second communication device specifies optimum communication timing out of a plurality of pieces of transmission timing within the zero crossing periods based on a result of error detection on each initial packet signal, and transmits an ACK signal including timing information on the optimum communication timing. Then, the first communication device transmits a data packet signal in the optimum communication timing within the zero crossing period, which is specified based on the timing information. | 10-03-2013 |
20130259105 | COMMUNICATION SYSTEM, COMMUNICATION DEVICE, AND METHOD FOR OPERATING COMMUNICATION SYSTEM - A communication system includes a first communication device and a second communication device that performs power line communication with the first communication device via an electric power line, wherein the first communication device transmits a plurality of times an initial packet signal added with an error detection code in each of reference timing at regular intervals in the vicinity of zero crossing timing. The second communication device determines whether a reception state is good or poor based on a result of the error detection on each of the received initial packet signals, and when the reception state is poor, the second communication device transmits an ACK signal in timing shifted by micro time from the reference timing after receiving the initial packet signal. Then, the first communication device transmits a data packet signal in timing at the regular interval after the timing of receiving the ACK signal. | 10-03-2013 |
20130236118 | IMAGE PROCESSING APPARATUS AND METHOD OF OPERATING IMAGE PROCESSING APPARATUS - An image processing apparatus includes a relative coordinate acquiring portion for acquiring a corresponding position over the input image to a predetermined pixel in a rectangular region obtained by dividing the output image, a reference region specifying portion for specifying a reference region including a corresponding region over the input image of the rectangular region for a plurality of rectangular regions arranged continuously over the output image respectively, a reading region determining portion for merging each reference region related to each of the rectangular regions, thereby obtaining a merging region, reading control means for reading a pixel value of each pixel included in the merging region in the input image, and correction processing means for executing the distortion correction processing by using a pixel value of a pixel which is read through the reading control means, thereby acquiring a pixel value of the output image. | 09-12-2013 |
20130235235 | DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD - A data transfer apparatus includes a cache memory having a storing portion for writing and reading data at a higher speed than an image data storing portion which stores image data GD of an input image, and data transfer request means for outputting, to the cache memory, a transfer request for image data in a certain region of the input image. The cache memory reads unstored image data from the image data storing portion beyond a reading region corresponding to a transfer request every pixel row if image data in a pixel row included in the reading region is not stored in the storing portion of the cache memory. Moreover, the data transfer request means sequentially gives, in arrangement order in a horizontal direction of an input image, a transfer request for image data in each of reading regions arranged in the horizontal direction. | 09-12-2013 |
20130235035 | IMAGE PROCESSING SYSTEM, METHOD OF OPERATING IMAGE PROCESSING SYSTEM, HOST APPARATUS, PROGRAM, AND METHOD OF MAKING PROGRAM - An image processing system includes an image coding device serving as a host device that outputs image data, and an image decoding device serving as a client device and including a display part that displays an image based on image data transmitted from the image coding device. The image coding device includes an image quality controller that controls the image quality of an image displayed on the display part in accordance with an operation status A of the image processing system. When the operation status is a status under which a delay of displaying an image which is caused by transmission of image data from the image coding device to the image decoding device is allowed, the image quality controller increases the image quality of an image displayed on the display part. | 09-12-2013 |
20130234690 | POWER SUPPLY DEVICE - A power supply device includes a power supply circuit and a power information generation part. The power supply circuit performs voltage conversion in which an input voltage applied to a voltage input terminal is converted into a voltage having a predetermined voltage value, and outputs the voltage obtained as a result of the voltage conversion to a voltage output terminal. The power supply circuit includes a switching part for, by a switching operation thereof, chopping a voltage of the voltage input terminal side, and a control circuit that controls the switching operation of the switching part. The power information generation part generates power information concerning power that is outputted from the voltage output terminal based on a content of the switching operation. | 09-12-2013 |
20130195179 | IMAGE PROCESSOR - An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter in the quantization. The controller determines a quantization parameter of a currently target macroblock, based on a difference between a target amount of code for a specified number of macroblocks and an amount of code generated for a predetermined number of macroblocks processed immediately before. The controller variably sets the specified number. | 08-01-2013 |
20130185069 | AMUSEMENT SYSTEM - A technique for allowing a virtual experience of more realistic live performance. A main apparatus reproduces music data and audience video data recording a video image of audience. A user holds a microphone and makes a live performance for the audience displayed on a monitor. The microphone sends voice data and motion information of the microphone to the main apparatus. The main apparatus determines that the user makes a live performance when the user calls on the audience with a specific phrase and performs an action corresponding to the specific phrase. The main apparatus reproduces reaction data recording a video image and sound indicating a reaction of the audience to the live performance. | 07-18-2013 |
20130182781 | PLC/POWER-SUPPLY HYBRID DEVICE AND DEVICE WITH COMMUNICATION FUNCTION - A PLC/power-supply hybrid device includes a power supply circuit. The power supply circuit includes a switching part for chopping a voltage of a voltage input terminal side, and a control circuit that controls the chopping by controlling switching of the switching part. The control circuit is operated in a normal mode and a transmission mode. The normal mode is a mode in which voltage conversion is performed. The transmission mode is a mode in which data transmission is performed through PLC using a power line that leads to the voltage input terminal. In the transmission mode, the control circuit modulates the switching of the switching part in accordance with transmission data. | 07-18-2013 |
20130145082 | MEMORY ACCESS CONTROL APPARATUS AND MEMORY ACCESS CONTROL METHOD - A memory is readable by page and erasable by block including a plurality of pages. After a read request to the memory is issued, a memory controller specifies all blocks which can be accessed based on an address specified by a read command, as candidate blocks, and specifies an inspection target page out of pages included in the candidate blocks on the basis of a predetermined rule. The memory controller inspects whether or not there is an error in the inspection target page. | 06-06-2013 |
20130124743 | COMMUNICATION DEVICE AND METHOD FOR OPERATING COMMUNICATION DEVICE - A communication device includes: a first communication element configured to perform communication in a first communication scheme; a second communication element configured to perform communication in a second communication scheme different from the first communication scheme by using, as common hardware, at least part among hardware that implements the communication in the first communication scheme; a schedule management section that manages which of the first communication element and the second communication element is to be used; and a sequence control section that, in accordance with an instruction given from the schedule management section, sets the common hardware so as to enable the communication in the first communication scheme or the communication in the second communication scheme to be performed. | 05-16-2013 |
20130107976 | COMMUNICATION DEVICE AND COMMUNICATION SYSTEM | 05-02-2013 |
20130028534 | IMAGE PROCESSOR - An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame, is obtained. The controller includes a first processing unit that obtains a generated amount of code used for a first predetermined number of immediately preceding macroblocks, a second processing unit that obtains an allowable amount of code available for a third predetermined number of immediately subsequent macroblocks including a currently target macroblock, based on a target amount of code for not more than a second predetermined number of macroblocks less than a total number of macroblocks included in one frame, and the generated amount of code obtained by the first processing unit, a third processing unit that obtains an expected amount of code expected to be used for the third predetermined number of macroblocks, and a fourth processing unit that sets a quantization parameter of a currently target macroblock, based on the allowable amount of code obtained by the second processing unit and the expected amount of code obtained by the third processing unit. | 01-31-2013 |
20130013887 | MEMORY CONTROLLER - An address comparator stores an address of data read out by a host system. Also, a buffer reads out the data from a memory and stores the data. If an address of data which is expected to be newly read out by the host system is included in addresses which have already been stored in the address comparator, the host system | 01-10-2013 |
20120321207 | IMAGE CODING APPARATUS - It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A numerical value (Ftk) is generated from the lower-order six bits of the frame number (Ft) of a coding object frame. A numerical value (Fs) is generated by shifting the numerical value (Ftk) leftward by two bits. An exclusive OR of the numerical value (Ftk) and the numerical value (Fs) is calculated, to thereby generate a numerical value (A). A numerical value (Ytk) is generated from the lower-order six bits of the Y coordinate (Yt) of a coding object macroblock. The upper-order bits of the numerical value (Ytk) and the lower-order bits thereof are inverted, to thereby generate a numerical value (Yr). Further, an exclusive OR of the numerical value (Yr) and the numerical value (A) is calculated, to thereby generate a numerical value (B). A numerical value (Xtk) is generated from the lower-order six bits of the X coordinate (Xt) of the coding object macroblock. When the numerical value (Xtk) and the numerical value (B) are identical to each other, the coding object macroblock is intra-coded. | 12-20-2012 |
20120317463 | MEMORY CONTROLLER - An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data. | 12-13-2012 |
20120308151 | IMAGE CODING APPARATUS - An image coding apparatus calculates the activity of each macroblock. All the macroblocks of block lines are set as intra-candidate macroblocks (intra-candidate MBs) which are candidates for intra coding. Every other macroblock is set as an intra-candidate MB in block lines. One of the intra-candidate MBs in each block line, which has the minimum activity, is determined as an intra macroblock of a frame. The macroblock determined as the intra MB is changed from the intra-candidate MB to an intra-forbidden macroblock. After changing the setting of the intra-candidate MBs, intra macroblocks are determined for a frame inputted subsequent to the frame. | 12-06-2012 |
20120307881 | IMAGE CODING DEVICE, IMAGE CODING/DECODING SYSTEM, IMAGE CODING METHOD, AND IMAGE DISPLAY METHOD - A device preventing degradation of image quality caused by coding of a moving image. A compression coder performs compression coding on image data of respective pictures constituting an input moving image to generate inter-coded data or intra-coded data, and outputs the coded data to a wire or wireless transmission line. In a case of causing the compression coder to generate the inter-coded data, a controller sets a code amount equal to or smaller than a maximum code amount given by a value obtained by multiplying an upper limit transmission rate of a transmission line and a permissible time allocated per picture based on a picture rate of the input moving image. Meanwhile, in a case of causing the compression coder to generate the intra-coded data, the controller sets a code amount larger than the maximum code amount and equal to or smaller than N-times (N is an integer equal to or larger than two) the maximum code amount. | 12-06-2012 |
20120294361 | IMAGE CODING APPARATUS - An image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part determines the number of intra macroblocks to be allocated in each frame. A position determination part arranges the intra macroblocks at random positions in each frame. A coding part performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part, and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part, to thereby output compressed image data. | 11-22-2012 |
20120287990 | IMAGE PROCESSOR - An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value. | 11-15-2012 |
20120281782 | COMMUNICATION SYSTEM, COMMUNICATION APPARATUS, AND COMMUNICATION INTEGRATED CIRCUIT - A communication system includes a first communication apparatus and a second communication apparatus. The first communication apparatus generates and transmits communication data in accordance with a predetermined protocol. The second communication apparatus includes a power circuit section having a switching regulator, and is configured to receive the communication data transmitted from the first communication apparatus. The predetermined protocol includes a protocol defining that at least one portion of a bit sequence constituting the communication data should be associated with an operation of the switching regulator. The second communication apparatus causes the switching regulator to operate in a time period in which the at least one portion of the communication data is received, in a state where the communication data is received. | 11-08-2012 |
20120147969 | TRANSCODER - If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate S | 06-14-2012 |
20120128315 | DISPLAY SYSTEM AND IMAGE REPRODUCTION DEVICE - Image reproduction devices ( | 05-24-2012 |
20120119977 | DISPLAY DEVICE - A display device has liquid crystal display panels aligned in a horizontal scan direction. The liquid crystal display panels constitute one virtual display area. A decoder decodes image data, to thereby generate pieces of pixel data having addressees corresponding to the virtual display area. A bridge circuit specifies a target (display destination) on which the pixel data is to be displayed on the basis of a parameter table indicating a correspondence between the virtual display area and each of display areas of the liquid crystal display panels. The pixel data are stored in line buffers corresponding to the specified display destinations and outputted to the liquid crystal display panels. Out of the pixel data, pixel data corresponding to a gap formed between two liquid crystal display panels are discarded. | 05-17-2012 |
20120093410 | IMAGE PROCESSING APPARATUS AND METHOD FOR OPERATING IMAGE PROCESSING APPARATUS - An image processing apparatus includes a first storage section and a second storage section, a storage control section, and a computation section. The storage control section sequentially acquires block images obtained as a result of dividing an input image, and stores the block image as a target block image in the first storage section, while storing, in the second storage section, image data of, in a region of the target block image, a region abutting un-inputted block images in the input image, as image data of an abuttal region. The computation section implements a resizing process for changing the size of the target block image by performing an interpolation calculation using image data of the target block image stored in the first storage section and the image data of the abuttal region stored in the second storage section. | 04-19-2012 |
20120081372 | IMAGE PROCESSOR - An image processing unit includes a computing unit, a data input unit that inputs image data to the computing unit, a data output unit that outputs the image data computed by the computing unit, and a setting unit. The computing unit includes computing cells including multiple types of computing cells, input domain selectors, and at least one of output domain selectors. The setting unit sets the input domain selectors and the output domain selectors so that image data inputted by the data input unit to the computing unit on which desired computing has been performed by at least one computing cell among the computing cells is outputted from the data output unit. | 04-05-2012 |
20120023338 | MEMORY CONTROL DEVICE, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND MEMORY CONTROL METHOD - A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols. | 01-26-2012 |
20120008772 | MEMORY CONTROLLER, MEMORY CONTROL DEVICE MEMORY DEVICE, MEMORY INFORMATION PROTECTION SYSTEM, CONTROL METHOD FOR MEMORY CONTROL DEVICE, AND CONTROL METHOD FOR MEMORY DEVICE - A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information. | 01-12-2012 |
20110305402 | IMAGE PROCESSOR - The image processor | 12-15-2011 |
20110268366 | IMAGE PROCESSING APPARATUS AND IMAGE CONVERSION APPARATUS - It is an object of the present invention to provide a technique for eliminating the unnaturalness in a generated moving image while achieving high speed processing in an image processing apparatus comprising a deblocking filter. A transcoder ( | 11-03-2011 |
20110267509 | IMAGE PROCESSING METHOD AND IMAGE PROCESSING DEVICE - An imaging device made of a single-chip type including a RGB Bayer pattern color filter is where pixel signals outputted from the imaging device are inputted through a signal processing part to an image processing part. A correlation judgment part judges a correlation between the pixel signals, and an interpolation processing part performs a pixel interpolation process based on a correlation result. Thus, each pixel signal becomes a perfect signal having all R, G and B color components. Filter factors for a filter are determined based on the correlation result, and a filtering process is performed on the pixel signals subjected to the pixel interpolation. | 11-03-2011 |
20110267496 | IMAGING DEVICE, IMAGE STORING METHOD AND RECORDING MEDIUM - An imaging device for capturing an image of a subject to acquire captured-image information, comprises: a positioning element arranged to measure a location at which the image is captured, to acquire capturing location information indicating a capturing location when the captured-image is acquired; a creation element arranged to create image information based on the capturing location information acquired by the positioning element and the captured-image information; a memory element arranged to store the image information created by the creation element; a decision element arranged to, when the image information stored in the memory element is output to the outside, decide whether or not the capturing location information included in the image information is to be kept secret; and a fabricator element arranged to fabricate the capturing location information included in the image information in accordance with a result of the decision by the decision element. Thus, it is possible to prevent leaking of information on the capturing location that is a kind of private information, minimizing reduction of convenience and versatility of the image information including the information on the capturing location. | 11-03-2011 |
20110200102 | IMAGE CODING APPARATUS AND IMAGE CONVERSION APPARATUS - An image coding apparatus obtains a quantization parameter of a macroblock to be encoded. The quantization parameter is corrected by adding a correction value thereto. An encoding part encodes the macroblock by using the corrected quantization parameter. After the encoding, a quantization parameter correction part calculates the cumulative target amount of codes by accumulating the target amounts of codes set for the encoded macroblocks, respectively, and calculates the cumulative amount of generated codes by accumulating the respective amounts of generated codes of the encoded macroblocks. If the cumulative amount of generated codes is larger than the cumulative target amount of codes, the quantization parameter correction part increments the correction value. A new macroblock to be encoded is quantized more coarsely than the encoded macroblocks. | 08-18-2011 |
20110194765 | IMAGE PROCESSING APPARATUS - An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5×5 taps are connected in cascade in three stages, which enables low-pass filtering with 13×13 taps. | 08-11-2011 |
20110182343 | ENCODER - An average quantization error value of each of I, P, and B pictures in an encoded unit of processing is calculated as an actually measured value having a large variation. An average quantization error value of each of I, P, and B pictures in an uncoded unit of processing is set as a target value having a small variation. In the encoding of the uncoded unit of processing, a result of the encoding of the encoded unit of processing is referenced and fed back thereto. By uniformly setting respective quantization errors of images and further by uniformly setting the respective qualities of the images, the image quality of a whole stream can be subjectively improved. Since the prefetch of the uncoded unit of processing is not needed, it is possible to perform real-time processing without any increase in the circuit scale. | 07-28-2011 |
20110161574 | SETTING CONTROL APPARATUS AND METHOD FOR OPERATING SETTING CONTROL APPARATUS - A setting control apparatus includes a setting control part, a special register, and a read-out control part. The setting control part makes stored in a temporary storage part a control value used in a processing circuit, in response to an input of the control value. The special register is electrically connected to the processing circuit and serving as a storage element capable of storing the control value. The read-out control part controls a read-out operation for reading out the control value from the temporary storage part into the special register. The read-out control part performs the read-out operation at a predetermined timing after storing of the control value in the temporary storage part is completed. | 06-30-2011 |
20110158325 | IMAGE CODING APPARATUS AND IMAGE CONVERSION APPARATUS - A statistical value calculation part specifies macroblocks positioned around an object macroblock and calculates a minimum average value of activities of the macroblocks. When images of the macroblocks are flat and the minimum average value is smaller than an activity of the object macroblock, the minimum average value is set as an adjustment value. A correction factor determination part determines a correction factor on the basis of the adjustment value and a factor determination table. By multiplying a reference quantization step value by the correction factor, a quantization step value of the object macroblock is determined. Since the quantization step value reflects a distribution of the activities of the macroblocks, it is possible to suppress a local change of the quantization step value. | 06-30-2011 |
20110122298 | IMAGE PROCESSING APPARATUS, AND METHOD OF OPERATING AN IMAGE PROCESSING APPARATUS - An image processing apparatus includes: a relative coordinate acquisition part acquiring a corresponding position on an input image with respect to a predetermined pixel on an output image; a first storage part storing position information of the corresponding position; a reading control part causing pixel values of input pixels on the input image to be sequentially read; an organization part organizing a set of grid points formed of input pixels among input pixels read by the reading control part; a judgment part judging, based on the position information, whether or not pixel values of pixels in the vicinity of the corresponding position used in calculating a pixel value of the predetermined pixel have been read; a local memory storing, in a case where judgment is made that pixels in the vicinity of the corresponding position have been read, pixel values of pixels forming the set of grid points as pixel values of surrounding pixels regarding the predetermined pixel; and a pixel value calculation part calculating a pixel value of the predetermined pixel by interpolation using the pixel values of the surrounding pixels. | 05-26-2011 |
20110075737 | TRANSCODER - A generated code amount accumulation part adds up the amounts of generated codes of pictures in 1 GOP which are encoded up to the current stage. An upper limit code amount accumulation part adds up the upper limit amounts of codes of the pictures in the 1 GOP which are encoded up to the current stage. A transmission load of an image transmission system is taken into consideration in the setting of the upper limit amount of codes. An update ratio setting part outputs an update instruction to lower a target rate when the accumulated amount of generated codes exceeds the accumulated upper limit amount of codes. The update ratio setting part does not output the update instruction for lowering the target rate when the accumulated amount of generated codes does not exceed the accumulated upper limit amount of codes. A transcoder can predict whether or not there is a possibility that the load of transmitting image data will increase while each picture in 1 GOP is encoded. | 03-31-2011 |
20110075731 | TRANSCODER - A transcoder that controls the amount of generated codes of an output stream toward a target bit rate without degradation of image quality. The transcoder decodes a first stream and encodes the decoded image again to thereby output a second stream. The transcoder calculates a distortion evaluation value from the image obtained by decoding the first stream and an image obtained by decoding the second stream. Assuming that a ratio between the distortion evaluation value and a total target distortion evaluation value is determined as a target distortion ratio, a target setting bit rate of a second stream in the period can be obtained by multiplying a total target bit rate of the second stream by the target distortion ratio. Alternatively, the target setting bit rate can be obtained by adjusting the target distortion ratio with an appropriate function and adding the target distortion ratio to the total target bit rate of the second stream. | 03-31-2011 |
20100293171 | IMAGE PROCESSOR - A first sorting unit includes a second sorting unit that sorts first frequency data for luminance based on a first table, a third sorting unit that sorts second frequency data for chrominance based on a second table, a fourth sorting unit that sorts third frequency data for chrominance based on a third table, and an updating unit that updates the second and third tables based on nonzero information on the first and second frequency data before the third and fourth sorting units start sorting. | 11-18-2010 |
20100278266 | METHOD OF GENERATING IMAGE DATA - Search is performed on Intra 16 to obtain a prediction mode leading to a minimum cost, and the minimum cost in Intra 16 and a corresponding prediction mode are stored. Search is performed on Intra 8 to obtain a prediction mode leading to a minimum cost, and then a relationship of magnitude between the stored minimum cost in Intra 16 and the minimum cost in Intra 8 is judged. After that, the minimum cost in Intra 8 and a corresponding prediction mode are stored, and search is performed on Intra 4 to obtain a prediction mode leading to a minimum cost. A relationship of magnitude between cost_intra and the minimum cost in Intra 4 is judged, and Intra 4 is determined as an optimum prediction mode in a case where Intra 4 is smaller. | 11-04-2010 |
20100268729 | MULTIMEDIA SYNTHETIC DATA GENERATING APPARATUS - A technique for drawing or managing multimedia data by desired groups. In a built-in memory of a cellular phone terminal, thirteen picked-up image data are stored. In tag information of each of the thirteen picked-up image data, information on date and time is recorded when an image of the data is picked up. When a user specifies the range of image pickup date and time, eight picked-up image data that match the specified range of image pickup date and time are selected and synthetic image data is generated from these eight picked-up image data. | 10-21-2010 |
20100162040 | MEMORY SYSTEM AND COMPUTER SYSTEM - A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks. | 06-24-2010 |
20100161937 | MEMORY SYSTEM AND COMPUTER SYSTEM - A memory system of the present invention comprises a plurality of first blocks provided for storing user information therein, to which first physical addresses which are not duplicate are assigned, respectively, a plurality of second blocks provided for individually storing therein the first physical addresses of initial defective blocks out of the plurality of first blocks, and a plurality of third blocks provided for individually storing therein the first physical addresses of late defective blocks out of the plurality of first blocks. The memory system further comprises a computing device for obtaining the first physical address corresponding to a logical address on the basis of the logical address, information stored in the second blocks, and information stored in the third blocks. | 06-24-2010 |
20100135589 | IMAGE PROCESSOR - An image processor includes a frequency transform unit performing frequency transform on a first pixel block as a target block, and a pre-filter performing prefiltering with a region which overlaps with plural unit regions for processing by the frequency transform unit as a unit region for processing, before frequency transform is performed. The pre-filter performs prefiltering on a second pixel block being a predetermined number of pixels each larger horizontally and vertically than the first pixel block as a target block. The pre-filter performs prefiltering sequentially on a plurality of second pixel blocks aligned horizontally. The number of pixel signals in a vertical direction within a group of pixel signals continuously inputted to the pre-filter for prefiltering is equal to the number of rows in the second pixel block. | 06-03-2010 |
20100128999 | IMAGE COMPRESSION APPARATUS - A symbol generation part serially inputs a data string of quantization data. If quantization data of non-zero coefficient is inputted, respective information on an absolute value, a zero run and a sign of the non-zero coefficient are stored in registers. When quantization data of the next non-zero coefficient is inputted, the respective information on the absolute value, the zero run and the sign stored in the registers are updated. At that time, the contents of the registers which have been stored immediately before the input are outputted as symbol data of the immediately preceding non-zero coefficient. | 05-27-2010 |
20100104206 | IMAGE COMPRESSION APPARATUS - An image compression apparatus performs quantization of DC component data, low-pass component data and high-pass component data which are generated by frequency conversion of still image data. An extracting part extracts additional data and coding object data which is to be entropy coded, from quantization data. An entropy coding part performs entropy coding of the coding object data stored in a coding object data memory. An additional data processing part generates a flex bit from the additional data. A pattern information generation part acquires the coding object data directly from the extracting part, to generate pattern information indicating whether the coding object data is zero or not. A bit stream generation part outputs the pattern information, the coding object data and the flex bit in a predetermined order, to output a bit stream. | 04-29-2010 |
20100104183 | IMAGE ENLARGEMENT METHOD - A correlation value calculation circuit calculates respective correlation values of each pixel for color image or for gray image in four directions. A selection circuit determines respective correlation values (Cv, Ch, Cd | 04-29-2010 |
20100086223 | IMAGE PROCESSOR - A decoding unit includes a first processing unit including ND decoding units and decoding a group of Normal Data, a second processing unit decoding a group of Flex Bits, and a selector. The ND decoding units perform decoding of the group of Normal Data, stepwise varying a start position of decoding in the data stream, concurrently with decoding of the group of Flex Bits by the second processing unit. The selector selects one ND decoding unit with a start position of decoding being set at a position immediately following an end position of the group of Flex Bits, from the ND decoding units, based on a result of decoding of the group of Flex Bits. | 04-08-2010 |
20100037013 | MEMORY ACCESS METHOD - A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive occurrences of access to allow for improved performance. Pieces of data are written into 0th, the first, the second, and the third banks, respectively. No idle time is caused between successive occurrences of access because different banks are successively accessed. Since a burst length of each of the pieces of data is eight, an interval of 16 cycles which is longer than 15 cycles is provided between a start of writing of first data and a start of second writing of data. Accordingly, no idle time is caused also between completion of writing of the first data and start of writing of the second data. | 02-11-2010 |
20090256932 | SINGLE-LENS REFLEX DIGITAL CAMERA - The single-lens reflex digital camera includes a CCD for imaging an image for storage and a CCD for imaging an image for live view. A pixel signal output from the CCD is processed in an image preprocessing unit, an image general processing unit, and a JPEG processing unit and stored in a memory card as JPEG data. A pixel signal output from the CCD is processed in a live image processing unit and stored in the memory card as YUV data for display. A display control unit reads the YUV data for display from the main memory and outputs the data to a LCD. The CPU adjusts frame rate of the live view image depending on the usage rate of the band of a main bus. | 10-15-2009 |
20090245674 | IMAGE PROCESSOR - An image processor includes a quantization unit receiving first data before quantization and outputting second data after quantization, a prediction unit obtaining a difference value between the second data and third data being prediction data and outputting the difference value as fourth data, and an encoding unit encoding the fourth data. The quantization unit includes a first processing unit dividing the first data by a quantization coefficient, so as to obtain fifth data including a fraction as a result of division and a second processing unit rounding up or rounding off the fraction such that a value of the fourth data becomes smaller based on comparison between the third data and the fifth data, so as to obtain the second data. | 10-01-2009 |
20090245669 | IMAGE PROCESSOR - An image processor includes an encoding unit encoding inputted data. The encoding unit includes a first processing unit splitting the data into a first partial data in a first digit range on an upper side and a second partial data in a second digit range on a lower side, a second processing unit encoding only the first partial data between the first partial data and the second partial data, and a third processing unit performing correction to set a value of the first partial data at “0”. | 10-01-2009 |
20090238477 | IMAGE PROCESSOR - An image processor includes an encoder and a decoder. The encoder includes a frequency transform unit, a pre-filter, and a color conversion unit that converts a pixel signal of a first color space inputted from outside into a pixel signal of a second color space including a luminance signal and chrominance signals. The decoder includes a frequency inverse transform unit, a post-filter, and a color inverse conversion unit that inversely converts a pixel signal of the second color space into a pixel signal of the first color space. The pre-filter performs prefiltering on one or plural specific signals among the luminance and chrominance signals. The post-filter does not perform postfiltering on the above specific signals. | 09-24-2009 |
20090238447 | IMAGE PROCESSOR - An image processor includes a frequency transform unit performing frequency transform independently on a luminance signal and plural chrominance signals and outputting an item of frequency data of the luminance signal and plural items of frequency data of the chrominance signals, and a quantization unit performing quantization independently on plural items of frequency data inputted from the frequency transform unit. The quantization unit performs quantization on one or plural specific items of frequency data corresponding to a signal with noise among the frequency data of the luminance signal and the chrominance signals, employing a quantization coefficient having a value greater than “1”, and performs quantization on frequency data apart from the specific items of frequency data, employing a quantization coefficient having a value “1”. | 09-24-2009 |
20090238266 | TRANSCODER - A category setting part sets a type of a decoded image based on characteristics of the decoded image which are fineness of the decoded image and an intensity of movement of the decoded image. A code amount setting part sets a target code amount of an output image based on the type of the decoded image. A quantization step value setting part sets a quantization step value of the output image based on the target code amount of the output image. A transcoder can set the target code amount of the output image depending on fineness of the decoded image. The transcoder can distribute the target code amount of the output image to a reference image and a predicted image depending on the intensity of movement of the decoded image. | 09-24-2009 |
20090237569 | TRANSCODER - A scene change detection part detects a scene change based on a characteristic amount of an input image. A target code amount setting part executes correction by a correction code amount on a target code amount previously set for suppressing variation of an output code amount around the time of scene change. A quantization step value setting part sets a quantization step value based on the target code amount. That is to say, a transcoder | 09-24-2009 |
20090237532 | NOISE REDUCTION DEVICE AND DIGITAL CAMERA - The first array register stores neighboring pixels of the same color as the pixel of interest, which are sorted according to the size of the pixel value. The maximum signal comparison circuit compares the value obtained by adding the threshold ThB to the pixel value maxC, which is the (b | 09-24-2009 |
20090232393 | IMAGE PROCESSOR - In a first input step from outside to an image processor, a signal input unit inputs to a pre-filter a first part of first luminance signals inputted from outside, which is a part to be processed by the pre-filter in the first input step, and stores a remaining second part of the first luminance signals in the memory unit. In a second input step following the first input step, the signal input unit inputs to the pre-filter the second part of the first luminance signals read from the memory unit and a first part of second luminance signals inputted from outside, which is a part to be processed by the pre-filter in the second input step, and stores a remaining second part of the second luminance signals in the memory unit. | 09-17-2009 |
20090213929 | TRANSCODER - In a transcoder, a decoder decodes a stream and an encoder encodes the stream again. The encoder calculates the quantization step value by using an average period bit rate (AS | 08-27-2009 |
20090213928 | TRANSCODER - If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate S | 08-27-2009 |
20090136153 | PIXEL INTERPOLATION METHOD - An image processing circuit inputs pixels of an RGB Bayer array therein. A chroma value calculation circuit calculates a chroma factor (K | 05-28-2009 |
20090103821 | FREQUENCY CONVERTER AND FREQUENCY INVERTER - On the first hierarchical layer, the input image adjuster selects an overlap processing area from a frequency-unconverted image. On the first hierarchical layer, the overlap processor performs overlap processing on the overlap processing area, and holds the image data of the remaining processing areas, which cannot be frequency-converted. The remaining processing area, which is a linear area, can have an image width reduced down to the displacement between the overlap processing area and the block areas. The processes on the second hierarchical layer are identical to those on the first hierarchical layer. As a result, the encoder maximizes the advantage of the high performance achieved by hardware implementation. | 04-23-2009 |
20090070501 | DATA PROCESSOR - A format converter includes a first input buffer for storing input data, an output buffer for storing output data, a converter connected between the first input buffer and the output buffer, and a register that the converter refers to. The register allows plural kinds of conversion patterns to be defined in conformity with a desired data format conversion. The converter generates the output data based on the input data, in accordance with the conversion pattern defined in the register. | 03-12-2009 |
20090067015 | BLOCK MATCHING CIRCUIT AND DATA UPDATE METHOD - Scanning image data and target image data are respectively stored in a first storage area and a second storage area. In one case, (J−M+1)×(K−N+1)×M×N pieces of pixel data are stored as comparison image data relating to all comparison areas, and M×N pieces of pixel data are stored as target image data. In contrast, the present invention requires the storage only of J×K pieces of pixel data as scanning image data, and M×N pieces of pixel data as target image data. This means the number of pieces of pixel data to be stored is reduced. In the case discussed above, one piece of target image data and (J−M+ | 03-12-2009 |
20090060389 | IMAGE PROCESSING APPARATUS - From an image pickup element, pixel signals of Bayer array are outputted. A correlation calculation part calculates correlation values with respect to a specified pixel in vertical and horizontal directions. A first interpolation part performs a pixel interpolation process while evaluating the correlation highly. A second interpolation part performs a pixel interpolation process while evaluating the correlation relatively low. A complete signal of RGB outputted from the first interpolation part is converted into a luminance signal in a first color space conversion part, and a complete signal of RGB outputted from the second interpolation part is converted into a color difference signal in a second color space conversion part. | 03-05-2009 |
20090044076 | MEMORY ACCESS SYSTEM - The ECC circuit generates the first syndrome of write data, which have not been written to the memory. The EDC circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced. | 02-12-2009 |
20090041371 | IMAGE PROCESSING APPARATUS - A correlation judgment part judges a correlation direction on each pixel. In a case where a correlation direction of a specified pixel is a vertical direction and the correlation thereof is small in any other direction, it is judged that the specified pixel is a pixel on an edge in the vertical direction. Then, a noise removal filtering operation is performed on the specified pixel by using pixels on a line in the vertical direction and an edge enhancement operation is performed by using pixels on a line in a horizontal direction. | 02-12-2009 |
20090040321 | DIGITAL CAMERA SYSTEM - The present invention provides a technique capable of generating an image having a portrait effect without complicating a configuration of a digital camera system. An image capturing apparatus has an optical system including a zoom lens, a correction lens, and a focus lens; and an image sensor for converting subject light which is incident via the optical system into an electric signal. The image capturing apparatus captures a blurred image in which a blurring is generally caused intentionally by changing a relative positional relation between any one of the zoom lens, the correction lens, and the focus lens and the image sensor, and also captures a normal image in which a blurring is not caused intentionally. An image processing apparatus combines the normal image and the blurred image, thereby generating a composite image having a no-blurring area in which a blurring is not intentionally caused and a blurred area in which a blurring is intentionally caused. | 02-12-2009 |
20090034620 | MOTION ESTIMATION METHOD - A motion estimation method capable of reducing the amount of calculation as compared to a full search method. In the method, a coarse search block and fine search blocks are defined. The fine search blocks are given by dividing the coarse search block into a plurality of blocks so that the fine search blocks are contained in the coarse search block. A sparsely interpolated image and a densely interpolated image are defined. A first search is performed using the defined coarse search block and the defined sparsely interpolated image. A second search is performed using the defined coarse search block and the defined densely interpolated image. With regard to search blocks belonging to the fine search blocks, only a surrounding region of an optimal point obtained in the first search is searched. | 02-05-2009 |
20080320342 | MEMORY CONTROLLER - A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address. | 12-25-2008 |
20080294949 | MEMORY ACCESS SYSTEM - When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts. | 11-27-2008 |
20080259708 | MEMORY CONTROLLER - A memory controller for controlling data access to a memory comprises a refresh controller. A read count memory part included in the refresh controller counts the number of read operations on each page of the memory and stores the read count therein. If the read count for any page exceeds a predetermined number, the refresh controller rewrites data stored in this page into the memory. | 10-23-2008 |
20080244175 | MEMORY SYSTEM AND COMPUTER SYSTEM - When a memory card is inserted into a computer, a memory controller sends command information stored in a memory array to the computer. Then, the computer stores the command information received from the memory card into a RAM. The computer generates a command as needed on the basis of the stored command information and sends the generated command to the memory card. When the memory card receives the command from the computer, the memory controller analyzes the received command and performs it while making reference to command analysis information. This makes it possible to reduce a load accompanying the change and addition of commands in a semiconductor memory. | 10-02-2008 |
20080229002 | SEMICONDUCTOR MEMORY AND INFORMATION PROCESSING SYSTEM - A semiconductor memory ( | 09-18-2008 |
20080215954 | BIT ERROR REPAIR METHOD AND INFORMATION PROCESSING APPARATUS - An information processing apparatus has an error correction function for checking an error of stored data read out from a flash memory. If an error is found, error information thereof is temporarily stored into a register and then stored in a nonvolatile memory at an appropriate timing. At an appropriate timing such as power-on, the information processing apparatus reads the stored data in which the error is found again on the basis of the error information stored in the nonvolatile memory, corrects the error and then rewrites the stored data into the flash memory. It is thereby possible to repair a recoverable bit error such as a read disturb. Therefore, a normal read operation can be performed without a hitch, and this can avoid giving any uncomfortable feeling to users. | 09-04-2008 |
20080211967 | IMAGING UNIT, PORTABLE TERMINAL DEVICE, AND PORTABLE TERMINAL SYSTEM - The present invention provides an imaging unit, a portable terminal device, and a portable terminal system capable of performing a satisfactory key synthesizing process. An imaging unit mainly includes an imaging section, a conversion section, and a key signal generating section. The conversion section converts the format of the imaged image data output from the imaging section from YUV format to RGB format. The key signal generating section generates a key signal based on each pixel data configuring the imaged image data and the reference data for the imaged image data input from the imaging section. The key signal generating section also outputs foreground image data having the generated key signal and the corresponding pixel data of RGB format as minimum configuring unit. An image synthesizing section of a main unit generates synthesized image data by overlapping the foreground image data from the imaging unit and the background image data stored in a RAM based on the key signal contained in the foreground image data. | 09-04-2008 |
20080201546 | MEMORY SYSTEM, COMPUTER SYSTEM AND MEMORY - The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with the physical addresses of defective blocks in a memory skipped. Then, the physical addresses of the defective blocks in ascending order are sequentially stored into the second blocks in ascending order of the physical addresses of the second blocks, respectively. To obtain a physical address from a logical address, a target block is retrieved out of a plurality of second blocks on the basis of the logical address, and the physical address of the target block is added to the logical address to obtain the physical address. Thus, it is possible to reduce the required capacity of a reserve storage region used for conversion of logical addresses into physical addresses without deteriorating the access speed. | 08-21-2008 |
20080201538 | MEMORY CONTROL METHOD AND MEMORY SYSTEM - Error-tolerant code conversion is carried out on original data including a large amount of binary data which is apt to be unintentionally rewritten, to produce converted data including a smaller amount of binary data which is apt to be unintentionally rewritten, and the converted data is written into a memory. While a host system is processing the original data, the memory reads out the converted data and the code inverse transformation part carries out inverse transformation of error-tolerant code conversion on the converted data, to output reproduced data which is identical to the original data, to the host system. As a result, it is possible to avoid or suppress the possibility that data is unintentionally rewritten due to repeated readout of the same data. | 08-21-2008 |
20080199005 | SIGNAL PROCESSOR - Original data to be a source for an encryption key is read from a memory cell array and stored in a buffer region. An encryption key generation unit generates a plurality of encryption keys by variously modifying the original data read from the buffer region based on a predetermined generation rule. The encryption unit generates an encrypted command by encrypting commands individually with an encryption key different for each command, out of the plurality of encryption keys generated by the encryption key generation unit. | 08-21-2008 |