SILICON LABORATORIES, INC. Patent applications |
Patent application number | Title | Published |
20160131536 | Temperature Measurement Circuitry and Method - A method includes alternately coupling a selected one of a plurality of current sources and two or more of the plurality of current sources to a first terminal of a bipolar device during first and second phases of a modulator cycle of a plurality of modulator cycles. The method further includes providing sampled voltages from the first terminal of the bipolar device to a modulator to produce a modulator output signal, filtering the modulator output signal to produce a filtered output signal using a back-end filter having an impulse response, and determining a temperature in response to the filtered output signal. | 05-12-2016 |
20160105629 | MULTI-CHIP MODULE FOR A MULTI-MODE RECEIVER AND METHOD THEREFOR - In one form, a multi-chip module for a multi-mode receiver includes an MCM substrate and first and second demodulator die. The MCM substrate has first and second satellite input ports, first and second terrestrial/cable input ports, and first and second transport stream ports. The first demodulator die has a satellite port coupled to the first satellite input port of the MCM substrate, a terrestrial/cable port coupled to the first terrestrial/cable input port of the MCM substrate, and first and second transport stream ports coupled to the first and second transport stream ports of the MCM substrate. The second demodulator die has a satellite port coupled to the second satellite input port of the MCM substrate, a terrestrial/cable port coupled to the second terrestrial/cable input port of the MCM substrate, and first and second transport stream ports coupled to the first and second transport stream ports of the MCM substrate. | 04-14-2016 |
20160105157 | CIRCUITS AND METHODS FOR PROVIDING AN IMPEDANCE ADJUSTMENT - An apparatus includes a signal generator and a control circuit. The signal generator includes a control terminal and includes a current electrode coupled to a terminal that is configured to couple to a power line to receive direct current (DC) power from a power generator. The control circuit is coupled to the current electrode and the control terminal of the signal generator. The control circuit determines an impedance associated with the power generator and applies a control signal to the control terminal of the signal generator to produce an impedance adjustment signal on the current electrode for communication to the power generator through the power line in response determining the impedance. | 04-14-2016 |
20160105148 | RC OSCILLATOR - A method includes using a current source to provide a charging current to a capacitor of a resistor-capacitor (RC) tank of an RC oscillator. The method includes using a resistor of the current source as a resistor for the RC tank. | 04-14-2016 |
20160104543 | Multi-Stage Sample and Hold Circuit - A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node. | 04-14-2016 |
20160056845 | LOW-COST RECEIVER USING INTEGRATED INDUCTORS - A receiver includes a first amplifier having an input for receiving a radio frequency (RF) signal, and an output for providing an amplified RF signal, a switch section for selectively switching the RF signal onto one of a plurality of nodes, and a filter section comprising a plurality of filters coupled to respective ones of the plurality of nodes. A first filter of the plurality of filters comprises a first variable capacitor coupled in parallel with an inductance leg between a corresponding one of the plurality of nodes and a power supply voltage terminal, wherein the first variable capacitor has a capacitance that varies in response to a tuning signal, and the inductance leg comprises a first inductorin series with an effective resistance, wherein the effective resistance has a value related to an upper cutoff frequency to be tuned by the first filter. | 02-25-2016 |
20160028405 | CLOCK GENERATOR USING FREE-RUNNING OSCILLATOR AND METHOD THEREFOR - A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator. | 01-28-2016 |
20150341063 | Updating A Filter Of An Equalizer - In one aspect, a tuner includes an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal, a digitizer to convert the second frequency signal to a digitized signal, a channel equalizer including a filter to filter the digitized signal, and a first controller to update the filter according to a frequency response of the filter. | 11-26-2015 |
20150285691 | STRAIN-INSENSITIVE TEMPERATURE SENSOR - An apparatus includes a thermistor having a variable resistance with a first dependence on absolute temperature. The apparatus includes a reference resistor having a resistance with a second dependence on absolute temperature, the second dependence being less than or having opposite polarity to the first dependence. The reference resistor includes a switched-capacitor circuit. The apparatus includes a node coupled between the thermistor and the reference resistor. The node is configured to provide a signal indicative of absolute temperature based on the variable resistance and the reference resistance. The signal may be strain-invariant, proportional to a reference voltage, and indicative of a ratio of the variable resistance to the reference resistance. The apparatus may include a feedback circuit configured to maintain the node at a predetermined voltage level. | 10-08-2015 |
20150271756 | Low-Power Communication Apparatus and Associated Methods - An apparatus includes a detector to detect an idle state of a communication link that communicates bursts or packets of information. The apparatus also includes an oscillator having low-power and normal modes of operation. The oscillator makes a transition to the low-power mode during the idle state of the communication link. The oscillator leaves the low-power mode of operation and enters the normal mode of operation when the communication link is in a non-idle state. | 09-24-2015 |
20150269106 | Communication Apparatus with Improved Performance and Associated Methods - A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state. | 09-24-2015 |
20150249856 | DEMODULATOR AND MULTI-CHIP MODULE FOR A MULTI-MODE RECEIVER AND METHOD THEREFOR - In one form, a multi-chip module for a multi-mode receiver includes an MCM substrate and first and second demodulator die. The MCM substrate has first and second satellite input ports, first and second terrestrial/cable input ports, and first and second transport stream ports. The first demodulator die has a satellite port coupled to the first satellite input port of the MCM substrate, a terrestrial/cable port coupled to the first terrestrial/cable input port of the MCM substrate, and first and second transport stream ports coupled to the first and second transport stream ports of the MCM substrate. The second demodulator die has a satellite port coupled to the second satellite input port of the MCM substrate, a terrestrial/cable port coupled to the second terrestrial/cable input port of the MCM substrate, and first and second transport stream ports coupled to the first and second transport stream ports of the MCM substrate. | 09-03-2015 |
20150228638 | Diode Circuit Layout Topology With Reduced Lateral Parasitic Bipolar Action - Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device. | 08-13-2015 |
20150222305 | REDUCING SECOND ORDER DISTORTION IN AN AMPLIFIER - In an embodiment, an apparatus includes a component of a receiver path to receive and process an incoming signal. At least one element of the component is controllable based on a DC output of the component, to compensate for a second order intermodulation product of the apparatus. As one example, the component is a differential amplifier including a first transistor and a second transistor. | 08-06-2015 |
20150222278 | Apparatus and Methods for Phase-Locked Loop Oscillator Calibration and Lock Detection - A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active. | 08-06-2015 |
20150222275 | Apparatus and Methods for Phase-Locked Loop Startup Operation - A phase-locked loop (PLL) is provided. The PLL may include a local oscillator configured to generate an output signal, a feedback divider configured to generate a feedback signal in response to the output signal, a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and a reset controller in communication with each of the phase detector and the feedback divider. The reset controller may be configured to hold each of the phase detector and the frequency divider in reset, and enable each of the phase detector and the frequency divider such that at least the feedback signal is in substantial synchronization with the reference signal. | 08-06-2015 |
20150214826 | SOFT-START FOR ISOLATED POWER CONVERTER - Current flowing through an inductor on a primary side of a voltage converter is sensed and compared to a threshold peak current value to determine when to end an ON portion of the voltage converter. The secondary side of the voltage converter supplies an indication of output voltage for use in determining the threshold peak current value. On start-up the primary side detects when the indication of output voltage is supplied by the secondary side across on isolation channel. Prior to detecting the indicating is being supplied, the primary side uses an increasing threshold peak current as the threshold peak current value. After detection that the indication of output voltage is being provided by the secondary side, the threshold peak current value is based on the indication of the output voltage. | 07-30-2015 |
20150214825 | PSEUDO-CONSTANT FREQUENCY CONTROL FOR VOLTAGE CONVERTER - A pseudo-constant portion of a switching cycle (ON time or OFF time) is constant over short periods of time but the pseudo-constant portion is controlled over longer periods of time in a slow frequency control loop to maintain a desired frequency. The average frequency is maintained at or near a desired frequency but when there is a transient, local disturbance, or load change, or other occurrence, then for a short period of time the frequency will vary as the non pseudo-constant portion of the switching cycle changes to address the transient or other occurrence. The frequency control loop will slowly adjust the pseudo-constant portion of the switching cycle to return to the desired frequency. | 07-30-2015 |
20150200649 | FREQUENCY MANAGEMENT USING SAMPLE RATE CONVERSION - In one embodiment, an apparatus includes a first receiver path with a first digitizer to digitize an incoming signal obtained from a radio frequency signal including at least a first desired channel into samples, the first digitizer to operate at a first sampling frequency, a first sample rate converter coupled to an output of the first digitizer to receive the samples at the first sampling frequency and to output the samples at a fixed sampling frequency, and a first digital processor to receive and process the samples at the fixed sampling frequency. The apparatus may further include a controller to receive a frequency change indication and to dynamically control the first sample rate converter to accommodate a change in the first sampling frequency from a first rate to a second rate. | 07-16-2015 |
20150195725 | Apparatus and Methods for Radio Frequency Ranging - A radio frequency (RF) device is provided. The RF device includes an antenna interface, a receive circuit configured to extract data from incoming signals, a playback circuit configured to associate a predefined delay with the data, a transmit circuit configured to generate outgoing signals based on the data and the predefined delay, and a control circuit configured to calculate range based in part on the predefined delay and phase differences between incoming signals and outgoing signals. | 07-09-2015 |
20150194417 | Snapback Inhibiting Clamp Circuitry For Mosfet ESD Protection Circuits - Circuit configurations and related methods are disclosed that may be implemented to protect circuitry from adverse effects of transistor snapback that may occur during ESD events. The circuitry and methods may be implemented as part of distributed ESD rail clamping circuitry that includes ESD circuit elements that are coupled to power nodes or supply rails and not to signal nodes or signal pads of the circuitry in a manner that reduces parasitic loading on signal pads to reduce or substantially eliminate NMOS and/or PMOS transistor snapback occurrence, while at the same time providing rail-clamping capability during occurrence of ESD events. Using the disclosed circuitry and methods, at least a portion of ESD current may be diverted by clamp circuitry from or to a supply rail to reduce voltage differential across the sources of CMOS output transistors relative to their bulk terminals in a manner that reduces forward biasing of parasitic BJTs present at each of the CMOS output transistors, thus reducing or substantially eliminating occurrence of transistor snapback during an ESD event. | 07-09-2015 |
20150189788 | TRANSMISSION-BASED TEMPERATURE CONTROL FOR AN ELECTRICAL DEVICE - A method includes estimating a temperature change to an integrated circuit, which is associated with a pending transmission from the integrated circuit. The method includes, based on the estimated temperature change, regulating at least one parameter that is associated with the pending transmission to maintain a temperature of the integrated circuit below a temperature threshold | 07-02-2015 |
20150188465 | SENSING A BACK ELECTROMOTIVE FORCE OF A MOTOR - An apparatus includes a controller and a comparator. The controller generates pulse width modulation (PWM) signals to drive stator windings of a brushless direct current (BLDC) motor in a commutation sequence such that one of the stator windings at a given time is open; and generates a tracking signal synchronized to the PWM signals and indicative of times when a leakage current is present in the open stator winding. The comparator senses when a back electromotive force of the open stator winding has an associated zero crossing. The sensing by the comparator is selectively enabled and disabled by the tracking signal. | 07-02-2015 |
20150188463 | CONTROLLER FOR BRUSHLESS DC MOTOR WITH LOW TORQUE RIPPLE AND METHOD THEREFOR - A controller for a BLDC motor includes a pulse width modulator and a control circuit. The pulse width modulator provides at least one phase control signal for a corresponding phase of the BLDC motor with a pulse width determined by a duty cycle signal. The duty cycle adjustment circuit has an input for receiving the at least one phase control signal, and an output for providing a corresponding modified phase control signal by adjusting widths of pulses of the at least one phase control signal when an average current in said corresponding phase exceeds a threshold. | 07-02-2015 |
20150188462 | CONTROLLER FOR BRUSHLESS DC MOTOR WITH FLEXIBLE STARTUP AND METHOD THEREFOR - A controller for a brushless direct current (BLDC) motor includes a pulse width modulator and a control circuit. The pulse width modulator provides a plurality of phase control signals to control corresponding ones of a plurality of phases of the BLDC motor. The control circuit controls the pulse width modulator to provide pulses to the plurality of phases to control a speed of the BLDC motor by causing the pulse width modulator to adjust widths of the pulses when a measured current in an active one of a corresponding phase exceeds a threshold in a startup mode. In one form, the controller is part of a BLDC motor system which also includes a plurality of phase drivers each having inputs for receiving respective ones of said plurality of phase control signals, and outputs adapted to couple to corresponding phases of the BLDC motor. | 07-02-2015 |
20150180479 | Metering Circuit Including a Floating Count Window to Determine a Count - A method includes receiving a count corresponding to a number of peaks of a resonant signal that exceed a reference signal and comparing the count to a floating count window defined by a first count threshold and a second count threshold, the first count threshold is larger than the second count threshold. The method further includes selectively shifting the floating count window in a direction of the count when the count falls outside of the floating count window. | 06-25-2015 |
20150180457 | Circuits and Methods of Automatically Adjusting a Discriminator Threshold - A circuit includes a discriminator to store a threshold. The circuit further includes a comparator including a first input to receive a count, a second input to receive the threshold, and an output to provide an output signal representing a result of the comparison between the count and the threshold. The circuit also includes a controller to automatically adjust the threshold when the count exceeds a first threshold or falls below a second threshold. | 06-25-2015 |
20150177280 | Metering Circuit Including a Time-Varying Reference and Method - A metering circuit includes a comparator including a first input to receive an input signal, and including a second input and an output. The metering circuit further includes a reference source to provide a time-varying reference signal to the second input during a peak counting operation. | 06-25-2015 |
20150147992 | INTEGRATED RECEIVER AND INTEGRATED CIRCUIT HAVING INTEGRATED INDUCTORS AND METHOD THEREFOR - In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal. | 05-28-2015 |
20150147991 | LOW-COST RECEIVER USING INTEGRATED INDUCTORS - A receiver includes a first amplifier having an input for receiving an RF signal, and an output for providing an amplified RF signal, a switch section that selectively switches the amplified RF signal onto a selected one of a plurality of nodes, and a filter section comprising a plurality of filters coupled to respective ones of the plurality of nodes. A first filter of the plurality of filters comprises a first variable capacitor coupled in parallel with an inductance leg between a corresponding one of the plurality of nodes and a power supply voltage terminal. The first variable capacitor has a capacitance that varies in response to a tuning signal. The inductance leg includes a first inductor in series with an effective resistance, wherein the effective resistance has a value related to an upper cutoff frequency to be tuned by the first filter. | 05-28-2015 |
20150145607 | PEAK DETECTORS FOR AMPLITUDE CONTROL OF OSCILLATORS - Various techniques for automatic amplitude control of an oscillator are described. An apparatus includes an oscillator circuit configured to generate an oscillating signal. The apparatus includes a feedback circuit configured to control a bias signal of the oscillator circuit to maintain a target peak amplitude of the oscillating signal based on a current-mode indicator of a peak amplitude of the oscillating signal and a reference current. The feedback loop includes a rectifier circuit configured to generate the current-mode indicator and a summing node configured to provide a bias control signal based on a difference between the current-mode indicator and the reference current. The feedback circuit may include a capacitor coupled to the summing node and configured to accumulate charge according to the difference. A magnitude of the current-mode indicator may be at least two orders of magnitude less than a magnitude of the current through an output node of the oscillator circuit. | 05-28-2015 |
20150139370 | INTEGRATED CIRCUIT WITH INTER-CHIP LINK FOR BOOT-UP - An integrated circuit includes a first port for conducting a first plurality of signals, a second port for conducting a second plurality of signals, a data path coupled between the first port and the second port, a controller, and a processor having an input and an output. In a first mode, the controller causes the data path to conduct at least one signal received on the first port to the second port. In a second mode, the controller controls the processor to output signals to the second port. | 05-21-2015 |
20150131683 | RECEIVER WITH SIGNAL ARRIVAL DETECTION CAPABILITY - A receiver includes first, second, and third signal processors and a controller. The first signal processor provides a first signal in response to detecting a first attribute of a received signal. The second signal processor provides a second signal in response to detecting a second attribute of the received signal. The third signal processor provides a third signal in response to detecting a third attribute of the received signal and provides packet data. The controller enables the first signal processor in response to a receive enable signal, controls the third signal processor to provide the packet data in response to receiving the first signal and the third signal, and initializes the first signal processor and the third signal processor in response to receiving the first signal and the second signal. | 05-14-2015 |
20150124914 | Spur Cancellation Systems and Related Methods - Spur cancellation systems and related methods are disclosed for radio frequency (RF) receivers and other implementations. Disclosed embodiments effectively remove spurs caused by digital clock signals or other spur sources by determining which spurs will fall within a channel selected to be tuned, utilizing a spur cancellation module to generate a cancellation signal, and subtracting this cancellation signal from the digital information. The cancellation signal can be initially generated with a known frequency and estimated values for unknown spur parameters, such as amplitude and phase. Digital feedback signals are then used to adjust the spur parameters. If the spur frequency is not known precisely, digital feedback signals can also be used to adjust the frequency of the cancellation signal. Where multiple receive paths are provided within a multi-receiver system, multiple spur cancellation modules can be used to remove spurs generated by digital clocks within each of the receive paths. | 05-07-2015 |
20150123714 | HIGHLY LINEAR BUFFER - Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor. | 05-07-2015 |
20150117573 | Radio Frequency (RF) Receivers With Whitened Digital Clocks And Related Methods - Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit. | 04-30-2015 |
20150111514 | HIGH PERFORMANCE, LOW COST RECEIVER FRONT END - A radio frequency (RF) receiver front end includes an RF attenuator for receiving an RF input signal and a low noise amplifier (LNA). In one form, the LNA provides a differential output signal and includes a first polarity amplifier and a plurality of second polarity amplifiers. The first polarity amplifier has an input terminal coupled to the output of the RF attenuator, an output terminal for providing a first component of the differential RF output signal, and has a first input impedance. Each of the plurality of second polarity amplifiers has an input terminal coupled to the output of said RF attenuator, and an output terminal. The output terminals of said plurality of second polarity amplifiers are coupled together and form a second component of the differential RF output signal. Each of the plurality of second polarity amplifiers has a second input impedance higher than the first input impedance. | 04-23-2015 |
20150110228 | SYNCHRONIZING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXED (OFDM) SYMBOLS IN A RECEIVER - In an embodiment, an apparatus includes a buffer to store incoming orthogonal frequency division multiplexed (OFDM) samples. This buffer is configured to output the OFDM samples according to a read pointer that can be adjusted by a sum value corresponding to a sum of a length of a symbol and a feedback value, to align the read pointer with the symbol. In addition, the apparatus further includes a feedback circuit coupled to the buffer to receive the output OFDM samples and generate the feedback value based at least in part on the output OFDM samples. | 04-23-2015 |
20150094007 | Receiver Chip with Multiple Independent Loop-Through Paths - A radio receiver and method of operating the same are disclosed. In one embodiment, the radio receiver may include a RF receive path configured to convey a first radio signal within a first band to a radio tuning circuit. The RF receive path may be controllable using a first AGC circuit. The radio receiver may also include a loop-through path configured to convey a second radio signal within a second band between an input and an output of the radio receiver. The second band may be different from the first band. The loop-through path may be controllable using a second AGC circuit. | 04-02-2015 |
20150092586 | RECEIVER WITH FREQUENCY DEVIATION DETECTION CAPABILITY AND METHOD THEREFOR - A receiver includes an analog receiver and a digital processor. The analog receiver has an input for receiving a radio frequency (RF) signal, and an output for providing a digital intermediate frequency signal. The digital processor has an input for receiving the digital intermediate frequency signal, and an output for providing digital symbols. The digital processor measures peak-to-peak frequency deviation of the digital intermediate frequency signal, and performs a digital signal processing function on the digital intermediate frequency signal to provide the digital symbols based on the peak-to-peak frequency deviation so measured. | 04-02-2015 |
20150092530 | Mesh Network Defragmentation - Methods of reassembling a mesh network which has been disrupted by the unavailability of a node or a link are disclosed. Nodes continuously receive beacon messages originating from a leader node. These beacon messages may be transmitted directly by the leader node, or may have been retransmitted by an intermediate node. When a node determines that it has not received a beacon message in a certain time period, it concludes that it is now disconnected from that leader node. At this point, it may choose to act as a leader node and form a new network, or may join with another network. The determination of which network to join may be based on some indicia associated with the leader node of that network. | 04-02-2015 |
20150091746 | Successive Approximation Register Analog-to-Digital Converter With Single-Ended Measurement - A circuit may include a comparator having a first input, a second input, and an output. The circuit further may further include a successive approximation register (SAR) circuit coupled to the output of the comparator, the first input, and the second input. The SAR circuit may be configured to program one or more capacitors to selectively bias the first input to provide a single-ended measurement of a voltage at the second input. | 04-02-2015 |
20150091537 | USE OF A THERMISTOR WITHIN A REFERENCE SIGNAL GENERATOR - Reference signal generators using thermistors are disclosed. An apparatus includes a first device having a first temperature coefficient and a thermistor having a second temperature coefficient having a sign opposite to that of the first temperature coefficient. A circuit maintains equivalence of a first signal and a second signal and offsets a first temperature variation of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature coefficient. The first device may be a bipolar transistor configured to generate a base-emitter voltage and coupled in series with the thermistor. The first signal may be a first voltage on a first node. The second signal may be a second voltage on a second node. The circuit may be configured to maintain effective equivalence of the first voltage and the second voltage. The apparatus may include a resistor coupled to the second node. | 04-02-2015 |
20150063434 | TRANSPORT OF AN ANALOG SIGNAL ACROSS AN ISOLATION BARRIER - An analog signal is transported across an isolation channel using edge modulation/demodulation of a pulse width modulated (PWM) signal. An edge modulator is responsive to rising edges of the PWM signal to generate first pulses having a first predetermined pulse width and is responsive to receipt of falling edges of the PWM signal to generate second pulses having a second predetermined pulse width with the same polarity as the first pulses. On the opposite side of the isolation channel an edge demodulating circuit recreates the PWM signal using the first and second pulses. The rise and falling edges of the PWM signals can be distinguished based on the pulse width of the first and second pulses. A second order pulse width modulator may be used to generate the PWM signal. | 03-05-2015 |
20150061913 | Dual-Path Comparator and Method - A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value. | 03-05-2015 |
20150048895 | ACCURATE FREQUENCY CONTROL USING A MEMS-BASED OSCILLATOR - A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference. | 02-19-2015 |
20150048878 | Apparatus and Method of Background Temperature Calibration - A circuit includes a controller configured to determine a calibration state of a circuit, to determine an active mode state of the circuit, and to select a type of calibration operation based on the calibration state. The controller is configured to control timing of the selected type of calibration operation in response to determining the calibration state to correspond to a time when the circuit is not active. | 02-19-2015 |
20150042498 | DAC CURRENT SOURCE MATRIX PATTERNS WITH GRADIENT ERROR CANCELLATION - First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation. | 02-12-2015 |
20150035595 | LOW-NOISE RECEIVER WITH COMPLEX RF ATTENUATOR - An apparatus includes an integrated circuit. The integrated circuit includes a low-noise amplifier having a first complex input impedance. The integrated circuit includes a complex attenuator coupled to an input terminal of the integrated circuit. The complex attenuator has a second complex input impedance and a first complex output impedance. The apparatus may include a matching network coupled to the input terminal of the integrated circuit. The matching network is external to the integrated circuit. The matching network may have a first real input impedance and a second complex output impedance. The second complex output impedance is matched to the second complex input impedance. | 02-05-2015 |
20150030061 | RECEIVER WITH SIGNAL ARRIVAL DETECTION CAPABILITY - A receiver includes a phase click detector, a controller, and a comparator. The phase click detector detects phase clicks in an input signal, where a phase click corresponds to a change in phase of at least a first threshold. The controller is coupled to the phase click detector for calculating a number of phase clicks within one or more time periods. The comparator compares the number of phase clicks within the one or more time periods, and provides an arrival signal if the number of phase clicks is less than a second threshold. | 01-29-2015 |
20140375374 | Capacitance to Digital Converter and Method - An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval. | 12-25-2014 |
20140370832 | Efficient Dual Channel Conversion In A Multi-Band Radio Receiver - In an embodiment, an apparatus includes a first signal path to receive and process a radio frequency (RF) signal of a first band and which has a first programmable digitizer to convert the RF signal of the first band into a digitized signal without downconversion. In addition, the apparatus further includes a second signal path to receive and process an RF signal of a second band, where at least portions of one or more of the paths may be shared during operation in the different bands. | 12-18-2014 |
20140361844 | SUSPENDED PASSIVE ELEMENT FOR MEMS DEVICES - A technique decouples a MEMS device from sources of strain by forming a MEMS structure with suspended electrodes that are mechanically anchored in a manner that reduces or eliminates transfer of strain from the substrate into the structure, or transfers strain to electrodes and body so that a transducer is strain-tolerant. The technique includes using an electrically insulating material embedded in a conductive structural material for mechanical coupling and electrical isolation. An apparatus includes a MEMS device including a first electrode and a second electrode, and a body suspended from a substrate of the MEMS device. The body and the first electrode form a first electrostatic transducer. The body and the second electrode form a second electrostatic transducer. The apparatus includes a suspended passive element mechanically coupled to the body and electrically isolated from the body. | 12-11-2014 |
20140361661 | TEMPERATURE COMPENSATION FOR MEMS DEVICES - A microelectromechanical system (MEMS) device includes a temperature compensating structure including a first beam suspended from a substrate and a second beam suspended from the substrate. The first beam is formed from a first material having a first Young's modulus temperature coefficient. The second beam is formed from a second material having a second Young's modulus temperature coefficient. The body may include a routing spring suspended from the substrate. The routing spring may be coupled to the first beam and the second beam. The routing spring may be formed from the second material. The first beam and the second beam may have lower spring compliance than the routing spring. The MEMS device may be a resonator and the temperature compensating structure may have dimensions and a location such that the temperature compensation structure modifies a temperature coefficient of frequency of the resonator independent of a mode shape of the resonator. | 12-11-2014 |
20140357211 | Radio Receiver Having Enhanced Automatic Gain Control Circuitry - An apparatus includes an input terminal to receive a radio frequency (RF) signal and to communicate the RF signal to a low noise amplifier (LNA) via an input signal path, and a capacitor attenuator coupled to the input terminal to attenuate the RF signal by a controllable amount and having a first portion controllable to include a used part configured on the input signal path and an unused part coupled between the input signal path and an AC reference node, and a second portion coupled between the LNA and the AC reference node. | 12-04-2014 |
20140354582 | Touch Sensor For Mobile Device With Radio - An integrated circuit that includes a wireless transceiver and a touchpad detection circuit is disclosed. The integrated circuit includes oscillators in the pad area of the device, thus minimizing silicon area used for this function. The oscillators consist of an inverting input buffer, such as a Schmidt trigger with a resistive feedback path from the output of the input buffer back to its input. The input of the buffer is also in communication with the external connection pad within the pad area. This allows an external component, such as a capacitor or touch sensor to be coupled to the oscillator. The method of operating a touchpad is also disclosed, where the oscillators may be selectively enabled. | 12-04-2014 |
20140307842 | GENERATING COMPATIBLE CLOCKING SIGNALS - Techniques are disclosed relating to generating compatible clock signals. In one embodiment, an apparatus is configured to receive an input clock signal and a reference clock signal. In this embodiment, the apparatus includes a rate estimation unit and a phase-locked loop (PLL) unit. In this embodiment, the PLL unit is configured to generate, using a control signal from the rate estimation unit and the input clock signal, a PLL output clock signal. In this embodiment, the rate estimation unit is configured to adjust the control signal such that the PLL output clock signal and the reference clock signal are compatible. In this embodiment, the rate estimation unit is configured to adjust the control signal based on the reference clock signal and a comparison clock signal generated by the apparatus based on the PLL output clock signal. | 10-16-2014 |
20140307759 | Isolated Serializer-Deserializer - A first integrated circuit die receives input data from a plurality of input channels and combines the input data from the plurality of input channels into combined data. The first integrated circuit die transmits the combined data across an isolation communication channel. A second integrated circuit die that is coupled to the isolation communication channel decodes the transmitted combined data and supplies the decoded transmitted combined data to respective output channels corresponding to the input channels. | 10-16-2014 |
20140306623 | INTEGRATED MEMS DESIGN FOR MANUFACTURING - A method of operating a system including a MEMS device of an integrated circuit die includes generating an indicator of a device parameter of the MEMS device in a first mode of operating the system using a monitor structure formed using a MEMS structural layer of the integrated circuit die. The method includes generating, using a CMOS device of the integrated circuit die, a signal indicative of the device parameter and based on the indicator. The device parameter may be a geometric dimension of the MEMS device. The method may include, in a second mode of operating the system, compensating for a difference between a value of the signal and a target value of the signal. The method may include re-generating the indicator after exposing the MEMS device to stress and generating a second signal indicating a change in the device parameter. | 10-16-2014 |
20140267928 | Television Tuner To Capture A Cable Spectrum - A method includes receiving a request to tune to a first desired television channel of a cable spectrum provided in a radio frequency (RF) signal received in a multi-tuner circuit configured to receive and process the entire cable spectrum, determining a channel of the channels including the first desired television channel, disabling the channels other than the determined channel, and processing the RF signal in the determined channel. | 09-18-2014 |
20140267925 | Multi-Tuner Using Interpolative Dividers - An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels. | 09-18-2014 |
20140266509 | ROTATIONAL MEMS RESONATOR FOR OSCILLATOR APPLICATIONS - An apparatus includes a microelectromechanical system (MEMS) device. The MEMS device includes a resonator suspended from a substrate, an anchor disposed at a center of the resonator, a plurality of suspended beams radiating between the anchor and the resonator, a plurality of first electrodes disposed about the anchor, and a plurality of second electrodes disposed about the anchor. The plurality of first electrodes and the resonator form a first electrostatic transducer. The plurality of second electrodes and the resonator form a second electrostatic transducer. The first electrostatic transducer and the second electrostatic transducer are configured to sustain rotational vibrations of the resonator at a predetermined frequency about an axis through the center of the resonator and orthogonal to a plane of the substrate in response to a signal on the first electrode. | 09-18-2014 |
20140266370 | Multi-Stage Delay-Locked Loop Phase Detector - A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another. | 09-18-2014 |
20140266336 | CLOCK SIGNAL TIMING-BASED NOISE SUPPRESSION - A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system. | 09-18-2014 |
20140256279 | Partitioned radio-frequency apparatus and associated methods - Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced. | 09-11-2014 |
20140254729 | Detecting Digital Radio Signals - In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence. | 09-11-2014 |
20140253219 | COMPENSATION OF CHANGES IN MEMS CAPACITIVE TRANSDUCTION - A method for compensating for strain on a MEMS device includes generating a signal indicative of a strain on the MEMS device in a first mode of operating a system including the MEMS device. The method includes compensating for the strain in a second mode of operating the system based on the signal. Generating the signal may include comparing an indicator of a resonant frequency of the MEMS device to a predetermined resonant frequency of the MEMS device. Generating the signal may include comparing a first output of a strain-sensitive device to a second output of a strain-insensitive device and generating an indicator thereof. Generating the signal may include sensing a first capacitive transduction of strain-sensitive electrodes of the MEMS device in the first mode and generating the signal based thereon. The strain-sensitive electrodes of the MEMS device may be disabled in the second mode. | 09-11-2014 |
20140237285 | SINGLE-PIN COMMAND TECHNIQUE FOR MODE SELECTION AND INTERNAL DATA ACCESS - A single pin is used to control an operating mode of an integrated circuit and to supply serial data to a host controller. The internal operating mode can be changed by changing a static level on an input/output terminal and maintaining that static level longer than a first time threshold. A read transaction from the integrated circuit can be performed in response to a predetermined sequence on the input/output terminal that includes a pulse that lasts a first predetermined time, the first predetermined time being less than the first time threshold. | 08-21-2014 |
20140232425 | MULTI-PURPOSE INTEGRATED CIRCUIT DEVICE CONTACTOR - A contactor uses a pogo block in a first configuration as a direct integrated circuit test socket and the contactor can be reconfigured to provide a pogo block assembly to interface between a main test printed circuit board (PCB) and a daughter card that is dedicated to a specific device handler and/or a specific package type that can be different from the main test PCB. A pogo block is inserted into a thick frame with an alignment plate for contactor use in which a device under test fits into a recess in the frame through an alignment plate to align the device under test to make contact with electrical contacts of the contactor. The frame and guide plate can be removed and a thinner frame coupled to the contactor, which changes its function to a pogo block assembly. | 08-21-2014 |
20140189169 | REGULATING DIRECT MEMORY ACCESS DESCRIPTOR EXECUTION - An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths. | 07-03-2014 |
20140189162 | REGULATING AN INPUT/OUTPUT INTERFACE - An apparatus includes an input/output (I/O) interface circuit that includes a memory and a controller. The memory stores a plurality of commands to regulate an input/output (I/O) interface. The commands indicate at least one I/O state of at least one I/O terminal of the I/O interface circuit and a time duration that is associated with the I/O state. The controller executes the commands to place the I/O interface in the the I/O state(s) in a predetermined sequence. | 07-03-2014 |
20140184116 | APPARATUS FOR MOTOR CONTROL SYSTEM AND ASSOCIATED METHODS - A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation. | 07-03-2014 |
20140184115 | APPARATUS FOR INTEGRATED CIRCUIT INTERFACE AND ASSOCIATED METHODS - An apparatus includes an integrated circuit (IC) adapted to be powered by a positive supply voltage. The IC includes a charge pump that is adapted to convert the positive supply voltage of the IC to a negative bias voltage. The IC further includes a bidirectional interface circuit. The bidirectional interface circuit includes an amplifier coupled to the negative bias voltage to accommodate a bidirectional input voltage of the IC. The bidirectional interface circuit further includes a comparator coupled to the negative bias voltage to accommodate the bidirectional input voltage of the IC. | 07-03-2014 |
20140176806 | INTEGRATED RECEIVER AND INTEGRATED CIRCUIT HAVING INTEGRATED INDUCTORS AND METHOD THEREFOR - An integrated receiver includes a first signal processing path, a second signal processing path, and a controller. The first signal processing path has an input and an output for providing a first processed signal, and comprises a first tracking bandpass filter having a first integrated inductor formed with windings in a first number of metal layers of the integrated receiver. The second signal processing path has an input and an output for providing a second processed signal, and comprises a second tracking bandpass filter having a second integrated inductor formed with windings in a second number of metal layers of the integrated receiver. The second number of windings is lower than the first number. The controller enables one of the first and second signal processing paths corresponding to a selected channel of a radio frequency (RF) input signal to provide an output signal. | 06-26-2014 |
20140176251 | MEMS MASS BIAS TO TRACK CHANGES IN BIAS CONDITIONS AND REDUCE EFFECTS OF FLICKER NOISE - A technique for tracking changes in bias conditions of a microelectromechanical system (MEMS) device includes applying an electrode bias signal to an electrode of the MEMS device. The technique includes applying a mass bias signal to a mass of the MEMS device suspended from a substrate of the MEMS device. The technique includes generating the mass bias signal based on a target mass-to-electrode bias signal level and a signal level of the electrode bias signal. | 06-26-2014 |
20140176248 | USE OF ELECTRONIC ATTENUATOR FOR MEMS OSCILLATOR OVERDRIVE PROTECTION - An apparatus includes a microelectromechanical system (MEMS) device configured as part of an oscillator. The MEMS device includes a mass suspended from a substrate of the MEMS, a first electrode configured to provide a first signal based on a displacement of the mass, and a second electrode configured to receive a second signal based on the first signal. The apparatus includes an amplifier coupled to the first electrode and a first node. The amplifier is configured to generate an output signal, the output signal being based on the first signal and a first gain. The apparatus includes an attenuator configured to attenuate the output signal based on a second gain and provide as the second signal an attenuated version of the output signal. | 06-26-2014 |
20140176201 | TIME-INTERLEAVED DIGITAL-TO-TIME CONVERTER - A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage. | 06-26-2014 |
20140176115 | Resonant Signal Sensing Circuit Having a Low Power Mode - An apparatus includes a sensor circuit to receive a varying signal at an input of the apparatus. The sensor circuit provides a sensor signal corresponding to a measurement of the varying signal. The apparatus further includes a timer circuit to generate a signal at various intervals of a plurality of intervals and a controller coupled to the sensor circuit. The controller has a first power mode and a second power mode, where the first power mode has a lower power consumption than the second power mode. The controller enters the second power mode in response to the signal from the timer circuit. The controller enables the sensor circuit, captures a plurality of measurements of the varying signal, and returns to the first power mode. | 06-26-2014 |
20140176004 | LIGHT CONTROL CIRCUIT AND METHOD - A system and method for controlling the dimming of a lighting element, or other electrical load, that uses a timer synchronized to the AC waveform is disclosed. The timer is set up to repeatedly count at a rate equal to twice the frequency of the AC waveform. An output from the timer logic is asserted when the timer value exceeds a predetermined value, stored in a compare register. This output is connected to the gate of a triac, which controls the passage of current from the AC power source to the electrical load. A capture register is used to determine the temporal relationship between the restart of the timer and the AC waveform. This system and method reduces the real time requirements of an associated processing unit, and improves consistency, thereby reducing flicker. | 06-26-2014 |
20140168551 | CONTROLLER AND DISPLAY APPARATUS WITH IMPROVED PERFORMANCE AND ASSOCIATED METHODS - An apparatus includes a multiplexed liquid crystal display (LCD) controller. The LCD controller is adapted to operate in at least first and second phases of operation. The LCD controller is adapted to drive a plurality of signal lines to a first set of voltages during the first phase of operation and to a second set of voltages during the second phase of operation. The LCD controller is further adapted to couple to a node at least some of the plurality of signal lines between the first and second phases of operation. | 06-19-2014 |
20140167509 | CHARGE PUMP FOR LOW POWER CONSUMPTION APPARATUS AND ASSOCIATED METHODS - An apparatus includes a first set of circuits adapted to operate in a first mode of operation of the apparatus. The apparatus further includes a second set of circuits adapted to operate in a second mode of operation of the apparatus, where a power consumption of the apparatus is lower in the second mode of operation of the apparatus than in the first mode of operation of the apparatus. The apparatus also includes a charge pump adapted to convert a first supply voltage of the apparatus to a second supply voltage, and the second supply voltage powers the second set of circuits. | 06-19-2014 |
20140151820 | GAS-DIFFUSION BARRIERS FOR MEMS ENCAPSULATION - A technique for forming an encapsulated microelectromechanical system (MEMS) device includes forming an integrated circuit using a substrate, forming a barrier using the substrate, and forming a MEMS device using the substrate. The method includes encapsulating the MEMS device in a cavity. The barrier is disposed between the integrated circuit and the cavity and inhibits the integrated circuit from outgassing into the cavity. The barrier may be substantially impermeable to gas migration from the integrated circuit. | 06-05-2014 |
20140118172 | MODIFIED FIRST-ORDER NOISE-SHAPING DYNAMIC-ELEMENT-MATCHING TECHNIQUE - A technique includes selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to convert a digital code to a plurality of analog signals in response to a plurality of control signals. Individual control signals of the plurality of control signals and individual analog signals of the plurality of analog signals correspond to respective unit elements of the plurality of unit elements. The technique includes generating the plurality of control signals based on the digital code, a random digital code having a number of bits based on a feedback signal, and an indicator of a second sequence of unit elements of the plurality of unit elements enabled in response to a prior digital code. | 05-01-2014 |
20140118033 | GLITCHLESS CLOCK SWITCHING THAT HANDLES STOPPED CLOCKS - An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent. | 05-01-2014 |
20140117497 | Decoupling Capacitors For Integrated Circuits - On-chip decoupling capacitors and methods for placing the same are disclosed in which designated spaces are created between the active circuits to insert designated capacitor cells. The designated capacitor cells may be placed in designated areas of the integrated circuit that are not simply spaces left empty by cell placement or frontier areas in or around the route, and the dimensions (e.g., height) of the designated capacitor cells may be selected to optimize (increase) capacitance efficiency. The capacitor cells may also be placed to target and reduce the interference between a digital core (aggressor) circuit and a victim analog circuit. | 05-01-2014 |
20140098974 | Pop/Click Noise Reduction Circuitry For Power-Up And Power-Down of Audio Output Circuitry - Pop/clock noise reduction circuitry is disclosed for audio output circuitry. After audio output circuitry is enabled, reference voltage generator circuitry is then enabled to produce a reference voltage that ramps from a first voltage level to a second voltage level at a smooth rate. The ramping reference voltage is applied to the input of the audio output circuitry to reduce or prevent pop/click noise for the audio output circuitry. Further, negative offset control circuitry can also be used to provide a negative offset input to the audio output circuitry to remove initial step-up voltage levels that may exist at operational power-up for the audio output circuitry. Still further, current control circuitry can also be used that limits the available current flowing to the output node for the audio output circuitry, thereby further reducing and/or preventing potential pop/click noise in the audio output signals. | 04-10-2014 |
20140094130 | Time-Domain Diversity Combining of Signals For Broadcast Receivers - Systems and methods are disclosed for time-domain diversity combining of radio frequency (RF) broadcast signals. Two channelized quadrature (I/Q) signals are generated by different tuner circuitry coupled to two different antennas, are converted to frequency-domain signals, and are used to generate frequency-domain diversity weighting signals. The frequency-domain diversity weighting signals are then converted to time-domain weights and applied to the channelized I/Q signals. The weighted and channelized I/Q signals are then combined in the time-domain to provide a time-domain diversity combined signal. The resulting combined signal can be further processed, as desired, such as by using a demodulator to generate demodulated output signals. Disclosed methods and systems can be applied to a variety of receiver systems configured to receive RF broadcast signals. | 04-03-2014 |
20140049256 | RESONANT MEMS LORENTZ-FORCE MAGNETOMETER USING FORCE-FEEDBACK AND FREQUENCY-LOCKED COIL EXCITATION - A method includes supplying a current to at least one conductive path integral with a MEMS device to thereby exert a Lorentz force on the MEMS device in the presence of a magnetic field. The method includes determining the magnetic field based on a control value in a control loop configured to maintain a constrained range of motion of the MEMS device. The control loop may be configured to maintain the MEMS device in a stationary position. The current may have a frequency equal to a resonant frequency of the MEMS device. | 02-20-2014 |
20140038542 | Rotating Harmonic Rejection Mixer - In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages. | 02-06-2014 |
20140026653 | Radiation-Blocking Structures - Stacked layers of non-continuous opaque layer structures are disclosed herein that may be configured to block radiation such as visible light or other forms of light, while at the same time allowing penetration of ambient gases. In one example, such non-continuous opaque layer structures may be configured as stacked non-continuous metal layer structures that together fully block penetration of radiation while at the same provide sufficient open spaces between and/or within the metal layer segments of a given integrated circuit layer to meet maximum metal spacing rules. In another example, such non-continuous opaque layer structures may be configured as capacitive structures. | 01-30-2014 |
20140002184 | APPARATUS FOR MIXED SIGNAL INTERFACE CIRCUITRY AND ASSOCIATED METHODS | 01-02-2014 |
20140002162 | APPARATUS FOR IMPROVED SIGNAL COMMUNICATION IN ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS | 01-02-2014 |
20130321051 | DIGITAL LOCKED LOOP FOR PRODUCING A CLOCK HAVING A SELECTED FREQUENCY RATIO RELATIVE TO A CLOCK PRODUCED BY A MEMS-BASED OSCILLATOR - A Micro Electrical Mechanical System (MEMS) oscillator supplies a MEMS clock signal to a digital locked loop that generates an output clock signal having a frequency that corresponds to a desired frequency ratio between the MEMS oscillator output signal and the digital locked loop output signal. The frequency ratio may be determined, at least in part, as a function of temperature. | 12-05-2013 |
20130250638 | AC POWER CONTROLLER - A low voltage AC power controller uses a line coupled capacitor AC to DC converter circuit to obtain energy from AC line power supplied to an AC load and may be used with an external high voltage AC switching device to control power supplied to the AC load. The line coupled capacitor AC to DC converter circuit provides a low power device that senses characteristics of the power supplied to the load and can communicate sensed information and/or receive control information related to the power supplied to load. | 09-26-2013 |
20130249604 | ADAPTIVE TRIAC CONTROLLER - A low voltage AC power controller uses a line coupled capacitor AC to DC converter circuit to obtain energy from AC line power supplied to an AC load and may be used with an external high voltage AC switching device to control power supplied to the AC load. The line coupled capacitor AC to DC converter circuit provides a low power device that senses characteristics of the power supplied to the load and can communicate sensed information and/or receive control information related to the power supplied to load. | 09-26-2013 |
20130208832 | Partitioned radio-frequency apparatus and associated methods - Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced. | 08-15-2013 |
20130118795 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 05-16-2013 |
20130112472 | METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another. | 05-09-2013 |
20130001738 | HIGH BREAKDOWN VOLTAGE INTEGRATED CIRCUIT ISOLATION STRUCTURE - A high breakdown voltage integrated circuit isolator device communicates a digital signal from a signal input on one semiconductor die to a signal output on another semiconductor die while providing high voltage isolation between the signal input and the signal output. Each die may include a respective capacitive isolation barrier structure that couple together via a bonding wire between combined top metal/bonding pads of the capacitive isolation barrier structures. | 01-03-2013 |
20120250809 | RADIO FREQUENCY (RF) RECEIVER WITH DYNAMIC FREQUENCY PLANNING AND METHOD THEREFOR - A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver. | 10-04-2012 |
20120183102 | Receiver Circuits and Systems for Receiving Medium Wave and Short Wave Signals - A receiver includes a first terminal for receiving an RF signal having a frequency of less than approximately 60 MHz, a second terminal, and a receive path having an input coupled to the first terminal and an output for providing a demodulated RF signal. The receiver further includes a detector coupled to the receive path for detecting a signal parameter in the RF signal and a controller coupled to the detector and to the second terminal. The controller provides the multiplex signal in a tuning state to the second terminal to selectively provide one of a first RF signal and a second RF signal to the first terminal and to determine at least one of a first parameter of the first RF signal and a second parameter of the second RF signal. The controller provides the multiplex signal in an operating state based on the first parameter and the second parameter. | 07-19-2012 |
20120162636 | PROXIMITY DETECTOR INCLUDING ANTI-FALSING MECHANISM - A proximity detector transmits light to an object near the proximity detector, thus providing transmitted light. A photo-sensor in the proximity detector receives transmitted light reflected by the object. The proximity detector tests the transmitted light reflected by the object to determine if the reflected light exceeds a predetermined brightness threshold value to provide preliminary object detection. The proximity detector confirms object detection by further testing ambient light received by the photo-sensor to determine if there is a substantial decrease in the amount of ambient light detected by the photo-sensor as the distance between the object and the proximity detector decreases. | 06-28-2012 |
20120157031 | Circuits and Methods of Low-Frequency Noise Filtering - A circuit includes an input terminal for receiving a radio frequency (RF) signal and a noise mitigation circuit coupled to the input terminal. The noise mitigation circuit is configured to detect a low-frequency noise signature in the RF signal and to automatically adjust an attenuation network to filter low-frequency noise from the RF signal in response to detecting the low-frequency noise signature. | 06-21-2012 |
20120001862 | CAPACITIVE TOUCH SWITCH DISPLAY CONTROL SYSTEM AND METHOD - A capacitive touch switch display control system includes multiple capacitive touch switches and respective LED displays that light to indicate the status of the system. A microcontroller unit (MCU) interface includes a shared function pin for each touch switch-LED pair. The MCU configures the shared function pin as an analog pin for very brief first time periods during which the MCU disables the LED displays and conducts capacitive sensing of the touch switches connected thereto to determine their status. After the first time period, the MCU enables the LED displays for potential lighting during a second time period. During the second time period, the MCU configures the shared function pin as a digital I/O LED control pin to either light or not light the LED display to indicate the status of the system. The first time period during which the MCU conducts capacitive sensing of the touch switches is sufficiently brief that it does not interfere with LED lighting function. | 01-05-2012 |
20120001659 | Voltage-to-Current Converter with Feedback - A voltage-to-current converter includes a transconductance stage including an input configured to receive a scaled voltage signal, a first output to carry a first current based on the scaled voltage signal, and a second output to carry a second current that is proportional to the first current. The voltage-to-current converter further includes a digital feedback loop coupled to the second output of the transconductance stage and configured to adjust the scaled voltage signal based on an error between an external reference voltage and a sense voltage derived from the second current to compensate for changes in the scaled voltage signal. | 01-05-2012 |
20110316631 | LNA CIRCUIT FOR USE IN A LOW-COST RECEIVER CIRCUIT - A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal. | 12-29-2011 |
20110298509 | TIME-SHARED LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT - In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs. | 12-08-2011 |
20110298505 | LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT - In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal. | 12-08-2011 |
20110266128 | Keypad System and Keypad with Enhanced Secutiry - In one form, a keypad includes a substrate and a flexible membrane disposed above a top surface of the substrate. The substrate has the top surface, a first conductor below the top surface, an insulator layer separating the first conductor from the top surface, and a second conductor disposed in proximity to the first conductor and to the top surface and coupled to a voltage terminal. The flexible membrane is disposed above the top surface of the substrate and has a third conductor forming a key. The third conductor is movable relative to the top surface. In another form, a keypad system includes such a keypad and a capacitive sensing circuit coupled to the first conductor for sensing a change in capacitance between the first conductor and the voltage terminal when the third conductor moves relative to the top surface. | 11-03-2011 |
20110258464 | Circuit and Method for Detecting a Legacy Powered Device in a Power over Ethernet System - In an embodiment, a power source equipment (PSE) device includes a network port configurable to couple to a network cable and a detection circuit coupled to the network port. The detection circuit is configured to apply a powered device (PD) detection voltage signal including first and second voltages to the network port and to sample a line current of the network port in response to the first and second voltages to detect a complex impedance indicating that a legacy PD is coupled to the network port. | 10-20-2011 |
20110254720 | Mismatch-Immune Digital-to-Analog Converter - In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier. | 10-20-2011 |
20110248865 | SENSOR DEVICE WITH FLEXIBLE INTERFACE AND UPDATABLE INFORMATION STORE - A sensor device includes an interface that receives a request. The sensor device includes an updatable information store that responds to the request if the request is directed to the updatable information store, the updatable information store being in a first power domain of the sensor device. The sensor device also includes a power manager that activates a sensor element in the sensor device in response to receiving the request if the request is a request for measurement of a parameter by the sensor element. The sensor element is in a second power domain of the sensor device. The sensor element communicates measured parameter information to the updatable information store. | 10-13-2011 |
20110248152 | Apparatus and Circuit with a Multi-Directional Arrangement of Optical Elements - An apparatus includes a housing having a front surface, a rear surface, and at least one sidewall therebetween and a plurality of optical windows formed in the housing to allow light to pass through from multiple directions. The apparatus further includes a plurality of photo detectors to generate electrical signals based on received light, where each of the plurality of photo detectors is disposed within a respective one of the plurality of optical windows. The apparatus also includes a control circuit coupled to the plurality of photo detectors to receive the electrical signals, determine light variations from the electrical signals, and determine a change in position of an object based on variation ratios of the light variations received by at least one pair of photo detectors within the plurality of photo detectors in response to determining the light variations. | 10-13-2011 |
20110235758 | Mixed-Mode Receiver Circuit Including Digital Gain Control - A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages. | 09-29-2011 |
20110215848 | FREQUENCY SYNTHESIZER - A frequency synthesizer includes a controlled oscillator configured to extend a temperature range and phase noise of the synthesizer without compromising the frequency coverage of the synthesizer. The frequency synthesizer also includes bias generation circuitry that sets a bias current of a charge pump to reduce bandwidth variations of the synthesizer. The frequency synthesizer further includes switching circuitry to dynamically turn a charge pump on and off to reduce effects of current leakage in the charge pump. | 09-08-2011 |
20110181325 | CIRCUIT AND METHOD OF CLOCKING MULITIPLE DIGITAL CIRCUITS IN MULTIPLE PHASES - A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits. | 07-28-2011 |
20110158357 | ANTENNA DIVERSITY SYSTEM WITH FRAME SYNCHRONIZATION - In an embodiment, a tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor is to synchronize the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset, the digital signal processor configured to perform a selected antenna diversity operation on the first and second DSP frames to produce an output signal. | 06-30-2011 |
20110158339 | ANTENNA DIVERSITY SYSTEM WITH MULTIPLE TUNER CIRCUITS HAVING MULTIPLE OPERATING MODES AND METHODS - In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode. | 06-30-2011 |
20110158298 | TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME - A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link. | 06-30-2011 |
20110157140 | VOLTAGE CONTROL ON N-WELLS IN MULTI-VOLTAGE ENVIRONMENTS - An output pad control logic comprises an output buffer including a plurality of transistors connected to drive signals for an output pad. Each of the plurality of transistors includes an n-well. An n-well generator connects a first voltage to the n-wells of the plurality of transistors of the output buffer in a first mode of operation when a system rail voltage exceeds a pad voltage applied to the output pad. The n-well generator connects the pad voltage to the n-wells of the plurality of transistors of the output buffer in a second mode of operation when the pad voltage applied to the output buffer exceeds the system rail voltage. A switching circuit is responsive to at least one control signal to connect the system rail voltage as the first voltage when the output pad is not driving an LCD display and to connect a larger of the system rail voltage and an LCD drive voltage as the first voltage when the output pad is driving the LCD display. | 06-30-2011 |
20110157109 | HIGH-VOLTAGE CONSTANT-CURRENT LED DRIVER FOR OPTICAL PROCESSOR - An LED driver comprises a first transistor for setting an output current level at an output of the LED driver that is responsive to a programmable current and an input signal. A second transistor in series with the first transistor provides voltage protection for the first transistor. The first transistor and the second transistor support an output voltage higher than a maximum operating voltage of either of the first or the second transistor alone. Biasing circuitry generates an adaptive bias voltage for the second transistor to protect the first transistor and the second transistor from high voltage levels at the output of the LED driver. | 06-30-2011 |
20110157070 | SYSTEM AND METHOD FOR CONFIGURING CAPACITIVE SENSING SPEED - A system and method for configuring capacitive sensing speed are provided. In one example, a circuit includes first and second circuitry and control logic. The first circuitry controls a first current provided to a reference capacitor having a known capacitance. The second circuitry controls a second current to an external capacitor having an unknown capacitance. The control logic is configured to receive input defining a period of time at which to set the charge time of the reference capacitor, control the first circuitry to provide a minimum amount of the first current needed to charge the reference capacitor within the defined period of time, and control the second circuitry to provide an amount of the second current needed to normalize the charge time of the external capacitor with the charge time of the reference capacitor. | 06-30-2011 |
20110157068 | TOUCH SCREEN POWER-SAVING SCREEN SCANNING ALGORITHM - A method for detecting touch locations on a capacitive array includes the steps of scanning for at least one touch location on an entire capacitive array using a first sensing circuitry and detecting the at least one touch location with the first sensing circuitry. A smaller portion of the capacitive array is determined responsive to the detection of the at least one touch location. The at least one touch location is scanned only within smaller portion of the capacitive array using a second sensing circuitry. The at least one touch location is detected with the second sensing circuitry and output for use. | 06-30-2011 |
20110156839 | CAPACITIVE SENSOR WITH VARIABLE CORNER FREQUENCY FILTER - A system and method for configuring a variable filter in a capacitive sensing circuit are provided. In one example, the circuit includes first and second circuitry and control logic. The first circuitry is configured to provide a variable resistance path that is coupled to an external capacitor that is to be sensed by the capacitive sensing circuit. The second circuitry controls actuation of the first circuitry and is responsive to a voltage change that occurs when a charge level of the external capacitor is altered. The second circuitry actuates the first circuitry when the voltage change causes a voltage supplied to the second circuitry to pass a predefined threshold. The control logic receives input identifying a desired corner frequency, determines a resistance setting for the first circuitry corresponding to the corner frequency, and applies the resistance setting to the first circuitry to configure the first circuitry at the corner frequency. | 06-30-2011 |
20110156802 | CHARGE PUMP WITH LOW POWER, HIGH VOLTAGE PROTECTION CIRCUITRY - A charge pump circuitry for generating a charging voltage for programming a one time programmable (OTP) memory includes a charge pump sub-circuit for generating the charging voltage in a second voltage range when the charging voltage exceeds a threshold level. A precharge circuit generates the charging voltage in a first voltage range when the charging voltage is below the threshold level. A voltage measurement circuit determines the charging voltage. A first control circuit enables the precharge circuit and disables the charge pump sub-circuit in a first mode of operation responsive to the charging voltage being determined to be below the threshold level and disables the precharge circuit and enables the charge pump sub-circuit in a second mode of operation responsive to the charging voltage being determined to exceed the threshold level. A second control circuit provides an indication that the charging voltage has reached a charging level for programming the OTP memory responsive to the determined charging voltage. | 06-30-2011 |
20110151819 | Radio Frequency (RF) Receiver with Dynamic Frequency Planning and Method Therefor - A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver. | 06-23-2011 |
20110151816 | Radio Frequency (RF) Receiver with Frequency Planning and Method Therefor - A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal. | 06-23-2011 |
20110150135 | ELECTROSTATIC DISCHARGE CIRCUITRY WITH DAMPING RESISTOR - An apparatus formed on a substrate includes a pad, electrostatic discharge circuitry, and a metal damping resistor connected between the pad and the electrostatic discharge circuitry. | 06-23-2011 |
20110115556 | CIRCUIT DEVICES AND METHODS OF PROVIDING A REGULATED POWER SUPPLY - In an embodiment, a circuit includes a regulated power supply terminal, a processing circuit coupled to the regulated power supply terminal, and a low frequency responsive circuit having a first transistor adapted to be coupled to a power source and having first circuitry configured to control current flow from the power source through the first transistor to supply a low frequency current to the regulated power supply terminal. The circuit device further includes a high frequency responsive circuit having a second transistor coupled to the regulated power supply terminal and having second circuitry configured to control the second transistor to selectively modulate high frequency current components at the regulated power supply terminal to reduce voltage variations on the regulated power supply. | 05-19-2011 |
20110115537 | CIRCUIT DEVICES AND METHODS FOR RE-CLOCKING AN INPUT SIGNAL - Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate. | 05-19-2011 |
20110102047 | Radio Frequency (RF) Power Detector Suitable for Use in Automatic Gain Control (AGC) - In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators. | 05-05-2011 |
20110076979 | SHIELDED DIFFERENTIAL INDUCTOR - A shielded differential inductor forms a high quality factor (high-Q) inductor that is configured to attenuate frequency spurs and/or noise from magnetic coupling generated by electrical structures on or off of a substrate as well as interference received by other components from magnetic coupling generated by the inductor. The shielded differential inductor includes a differential inductor and a shield that substantially isolates the electrical field between the inductor and the substrate to reduce substrate current loss. The shield includes sets of finger structures that extend beyond the width of the inductor and a hub and spoke configuration of ground conductors that connect the sets of finger structures to ground. | 03-31-2011 |
20110076977 | Signal Processor Suitable for Low Intermediate Frequency (LIF) or Zero Intermediate Frequency (ZIF) Operation - A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops. | 03-31-2011 |
20110075775 | ANALOG TO DIGITAL CONVERTER WITH LOW OUT OF BAND PEAKING - An analog to digital converter includes a delta sigma modulator with a modified distributed feed-forward (DFF) topology. The modulator includes low pass filter circuitry that provides a first path to a first integrator and a second, feed-forward path to a second integrator that significantly reduce the out of band signal transfer function (STF) peaking of the modulator. | 03-31-2011 |
20110075720 | Radio Receiver Having a Multipath Equalizer - A radio receiver has a multipath equalizer that includes a filter and a coefficient estimator. The filter provides a reconstructed signal by applying a transfer function including a reflection coefficient and a delay coefficient to a multipath radio signal. The coefficient estimator adapts the reflection coefficient and the delay coefficient in response to a deviation in magnitude of the reconstructed signal from a normalized value. In one form, the coefficient estimator adapts at least one of the reflection coefficient and the delay coefficient by estimating a partial derivative using a predetermined number of terms. In another form, the coefficient estimator acquires an initial value of the delay coefficient by determining a global minimum as a lowest one of a plurality of local minimums, each determined using a plurality of values of the delay coefficient, and selecting the initial value of the delay coefficient as its value at the global minimum. | 03-31-2011 |
20110075719 | Radio Receiver Having a Multipath Equalizer - A radio receiver has a multipath equalizer that includes a filter and a coefficient estimator. The filter provides a reconstructed signal by applying a transfer function including a reflection coefficient and a delay coefficient to a multipath radio signal. The coefficient estimator adapts the reflection coefficient and the delay coefficient in response to a deviation in magnitude of the reconstructed signal from a normalized value. In one form, the filter evaluates the transfer function by truncating it to eight terms. In another form, the filter includes a delay line having delay elements for storing samples of the multipath radio signal received both before and after a current sample. In yet another form, the multipath equalizer further includes a normalizer that receives the multipath radio signal and provides a normalized multipath radio signal having a normalized magnitude to an input of the filter. | 03-31-2011 |
20110073996 | MULTIPLE DIE LAYOUT FOR FACILITATING THE COMBINING OF AN INDIVIDUAL DIE INTO A SINGLE DIE - A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die. | 03-31-2011 |
20110065399 | SYSTEM AND METHOD FOR DYNAMICALLY REGULATING VOLTAGE TO MINIMIZE POWER CONSUMPTION - A system includes a voltage regulator connected to a voltage source for providing a regulated voltage at a first level in a first mode of operation and at least one second level in a second mode of operation. The second voltage level is higher than the first voltage level. A control processor provides control signals to select between the first and the second modes of operation. A component associated with the voltage regulator. The component is disabled in the first mode of operation and enabled in the second mode of operation. The control processor generates control signals to configure the voltage regulator to generate the voltage at the first level in the first mode of operation when the component is disabled and to configure the voltage regulator to generate the voltage at the at least one second level in the second mode of operation when the component is enabled. | 03-17-2011 |
20110062785 | SYSTEM AND METHOD FOR SUPPORTING HIGH BURST CURRENT IN A CURRENT LIMITED SYSTEM - A current limited system for providing a burst current capability comprises a variable load having a first mode of operation requiring a first current level and a burst current mode of operation requiring a second current level. The second current level is greater than the first current level. A control processor provides control signals for the current limited system. A voltage source is connected to the variable load to provide a source current. The source current provides the variable load the first current level in the first mode of operation. A burst mode circuit provides the second current level to the variable load in the burst current mode of operation, responsive to the control signals from the control processor and the voltage source. | 03-17-2011 |
20110019728 | SYSTEM AND METHOD OF ALTERING A PWM CARRIER POWER SPECTRUM - In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal. | 01-27-2011 |
20110019205 | Apparatus and method for implementing a touchless slider - A method for gesture recognition in an optical system using a touchless slider is shown. The touchless slider has first and second reference points positioned along an axis in an optical system. The method includes obtaining a plurality of first and second reflectance values by measuring an amplitude of light reflected from an object relative to the first and second reference points, respectively, wherein each first and second reflectance value corresponds to a different point in time. The plurality of first and second reflectance values are compared to identify a plurality of ratio values between the first and second reflectance values, wherein each of the plurality of ratio values corresponds to one of the points in time. At least one of a position and a direction of movement of the object relative to the first and second reference points is determined based on the identified plurality of ratio values. | 01-27-2011 |
20100328542 | Low-Noise Amplifier Suitable for Use in a Television Receiver - A low-noise amplifier includes a first resistor that receives a first signal of a differential input signal, and a second resistor that receives a second signal of the differential input signal. The amplifier includes a first transconductance device coupled to the first resistor that provides a first signal of a differential output signal, and a second transconductance device coupled to the second resistor, that provides a second signal of the differential output signal. The receiver also includes a first capacitor coupled between the first resistor input and a control electrode on the second transconductance device, and a second capacitor coupled between the second resistor input and a control electrode on the first transconductance device. The low-noise amplifier can include additional gain stages. | 12-30-2010 |
20100328295 | SYSTEM AND METHOD FOR LCD LOOP CONTROL - An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator. | 12-30-2010 |
20100328286 | LCD CONTROLLER WITH OSCILLATOR PREBIAS CONTROL - An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage. | 12-30-2010 |
20100328199 | LCD CONTROLLER WITH BYPASS MODE - An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage. | 12-30-2010 |
20100327930 | SCHMITT TRIGGER WITH GATED TRANSITION LEVEL CONTROL - A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level. | 12-30-2010 |
20100321129 | CIRCUIT DEVICE AND METHOD OF COUPLING TO AN ANTENNA - In an embodiment, a circuit device for coupling to an antenna includes a first impedance matching circuit configured to couple to the antenna and a second impedance matching circuit configured to couple to the antenna. The circuit device further includes a power amplifier coupled to the first impedance matching circuit and includes a low-noise amplifier coupled to the second impedance matching circuit. Additionally, the circuit device includes a selectable impedance adjustment circuit coupled between the low-noise amplifier and the second impedance matching circuit, which selectable impedance adjustment circuit is configured to selectively adjust an impedance associated with the low-noise amplifier when the power amplifier is transmitting a signal through the antenna. | 12-23-2010 |
20100314939 | POWER SOURCING EQUIPMENT DEVICE INCLUDING A SERIAL INTERFACE - In a particular embodiment, a circuit device is disclosed that includes a power sourcing equipment (PSE) circuit having a plurality of high-voltage line circuits adapted to communicate with a respective plurality of powered devices via network cables. The PSE circuit includes a serial interface circuit and includes a common controller coupled to the serial interface circuit and to the plurality of high-voltage line circuits. The circuit device also includes a low-voltage circuit having a programmable controller adapted to transmit control signals to the common controller via the serial interface circuit to control operation of the plurality of high-voltage line circuits. | 12-16-2010 |
20100296671 | System and Method of Changing a PWM Power Spectrum - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 11-25-2010 |
20100293399 | SYSTEM AND METHOD OF CLASSIFICATION IN POWER OVER ETHERNET SYSTEMS - A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number. | 11-18-2010 |
20100283760 | METHOD AND APPARATUS FOR SCANNING A TOUCHSCREEN WITH MULTI-TOUCH DETECTION USING MASTER/SLAVE DEVICES - A touch panel scan system is disclosed for detecting a change in mutual capacitance on the surface of a touch panel. A first touch detect device is provided having a transmitter for transmitting a transmit signal to a select one of a plurality of first lines on a first edge of a touch panel to facilitate a single line scan operation. A second touch detect device is interfaced with a select one or ones of second lines on a second edge of the touch panel having a receiver for receiving therefrom and processing thereof transmit signals coupled thereto from the select one or ones of the first lines to detect changes in a mutual capacitance associated with the select one or ones of the second lines and the first line. At least one of the first or second touch detect devices functions as a master and the other functions as a slave, with the master coupled to the slave and generating a SYNC signal to initiate a single scan operation of a select one of the first lines. | 11-11-2010 |
20100271742 | Electrical Over-Stress Detection Circuit - In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled between first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals or between a supply voltage potential and a pad voltage of a bond pad. The EOS circuit further includes an alert generation circuit configured to store data indicating an EOS event in response to detecting the perturbation. | 10-28-2010 |
20100267350 | TUNING CIRCUITRY IN A COMMUNICATIONS DEVICE - A communications device is provided. The communications device includes a first antenna port coupled to a signal line, transmitter circuitry coupled to the signal line and configured to broadcast a radio frequency (RF) output signal across the first antenna port, tuning circuitry coupled to the signal line, and a controller configured to adjust a tuning of the tuning circuitry. The first antenna port, the transmitter circuitry, the tuning circuitry, and the controller are at least partially integrated on the same integrated circuit. | 10-21-2010 |
20100250875 | EEPROM EMULATION USING FLASH MEMORY - A device is provided wherein a traditional EEPROM device is emulated by using two or more pages of block-erasable memory and mapping each traditional EEPROM write instruction to an incremented active data sector in a first page of the block-erasable memory while a second page of the block-erasable memory is being partially or fully erased. Then, when the first page of block-erasable memory has had its plurality of data sectors written, changing the active page to the second block-erasable memory and mapping traditional EEPROM writes to incremented data sectors therein while the previously written block-erasable memory is being partially or fully erased. | 09-30-2010 |
20100246995 | Method for Performing Dual Mode Image Rejection Calibration in a Receiver - A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired using a first known signal associated with a first signal band during a startup mode. The first image correction factor has a plurality of bits including most significant bits (MSBs) and least significant bits (LSBs). The LSBs of the first image correction factor are adjusted incrementally during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received using the first image correction factor during the normal operation mode. | 09-30-2010 |
20100246649 | Circuit device including peak and average detectors - In a particular embodiment, a circuit device includes a peak detector to receive a signal and to generate peak output data related to the received signal and an average detector to generate average output data related to the received signal. The circuit device further includes a logic circuit to generate a data output related to the received signal based on the generated peak output data and the generated average output data. | 09-30-2010 |
20100238036 | Use of optical reflectance proximity detector for nuisance mitigation in smoke alarms - A smoke alarm comprises smoke detection circuitry for detecting smoke and generating a detection signal responsive thereto. Proximity detection circuitry generates a proximity detection signal responsive to detection of an object within in a selected distance of the smoke alarm. Alarm generation circuitry generates an audible alarm responsive to the detection signal. The audible alarm may be deactivated for a predetermined period of time responsive to at least one proximity detection signal. | 09-23-2010 |
20100225638 | SYSTEM AND METHOD FOR PROVIDING BIAS VOLTAGES TO PAD LOGIC OF AN LCD CONTROLLER - An LCD controller includes at least one I/O pad for providing an LCD drive voltage in an LCD mode of operation. I/O pad logic drives the at least one I/O pad responsive to a provided bias voltage. Voltage selection logic selects a higher voltage between an LCD drive voltage and an externally provided system voltage as a first voltage. Bias voltage logic selects one of the system voltage or the first voltage as the bias voltage for the I/O pad logic. The system voltage is selected as the bias voltage for the I/O pad logic in a non-LCD mode of operation for the I/O pad and the first voltage is selected for the bias voltage for the I/O pad logic in the LCD mode of operation for the I/O pad. | 09-09-2010 |
20100207699 | System and Method of Shaping a Power Spectrum in PWM Amplifiers - In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape. | 08-19-2010 |
20100201382 | SYSTEM AND METHOD FOR DETERMINING CAPACITANCE VALUE - A circuit for determining a value of a variable capacitor comprises first circuitry for generating a first indication when a variable voltage across the variable capacitor exceeds a threshold voltage. Second circuitry generates a second indication when a reference voltage across a reference capacitor exceeds the threshold voltage. Control logic responsive to the first and second indications generate a control signal indicating whether the first indication or the second indication occurs first. A successive approximation engine generates an N-bit control value responsive to the control signal. A variable current source is responsive to the N-bit control value for generating a variable current to the first circuitry. A reference current source generates a reference current to the second circuitry. | 08-12-2010 |
20100171540 | System and Method of Changing a PWM Power Spectrum - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 07-08-2010 |
20100156839 | METHOD AND APPARATUS FOR IMPLEMENTING A CAPACITIVE TOUCH SLIDER - A capacitive touch slider array comprises a first conductive trace associated with a first sensing node. The first conductive trace includes a first conductive line and a plurality of first conductive fingers extending from the first conductive line. The plurality of first conductive fingers have lengths that increase from a first end of the capacitive touch slider array to a second end of the capacitive touch slider array. A second conductive trace associated with a second sensing node includes a second conductive line and a plurality of second conductive fingers extending from the second conductive line. The plurality of second conductive fingers have lengths that increase from the second end of the capacitive touch slider array to the first end of the capacitive touch slider array. | 06-24-2010 |
20100156685 | SAR ANALOG-TO-DIGITAL CONVERTER HAVING VARIABLE CURRENTS FOR LOW POWER MODE OF OPERATION - A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SARADC. | 06-24-2010 |
20100156684 | SAR ANALOG-TO-DIGITAL CONVERTER HAVING DIFFERING BIT MODES OF OPERATION - A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC. | 06-24-2010 |
20100156493 | Circuit device to produce an output signal including dither - In a particular embodiment, a circuit device includes a count zero circuit having a first counter to receive a clock signal and to produce a count zero signal based on the clock signal and having a second counter to generate a reset control signal to control a reset of the count zero circuit. The circuit device further includes a turnoff circuit to receive the clock signal and to produce a turn off signal based on the clock signal. Further, the circuit device includes a pulse width modulated (PWM) latch circuit adapted to produce a gate drive signal based on the count zero signal and the turn off signal, where timing of an edge of the gate drive signal varies based on the reset control signal. | 06-24-2010 |
20100156175 | DC/DC BOOST CONVERTER WITH BYPASS FEATURE - An integrated circuit package includes a DC/DC boost converter for providing an output voltage at a program level to associated components of the integrated circuit package. The DC/DC boost converter includes a first mode of operation wherein the DC/DC boost converter is enabled responsive to an input battery voltage falling below a programmed level of the output voltage. The DC/DC boost converter also includes a second mode of operation wherein the DC/DC boost converter is disabled responsive to the input battery voltage being above the programmed level of the output voltage. | 06-24-2010 |
20100150338 | Circuit device with serial bus isolation - In a particular embodiment, a circuit device includes a first circuit having a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal. The first plurality of serial terminals is communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data. The circuit device further includes a second circuit having a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals. | 06-17-2010 |
20100130158 | Low-Cost Receiver Using Tracking Filter - A receiver ( | 05-27-2010 |
20100130155 | Low-Cost Receiver Using Tracking Bandpass Filter and Lowpass Filter - A receiver ( | 05-27-2010 |
20100130153 | Low-Cost Receiver Using Automatic Gain Control - A receiver ( | 05-27-2010 |
20100125776 | Multi-syndrome error correction circuit - In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream. | 05-20-2010 |
20100118918 | SPREAD SPECTRUM ISOLATOR - An apparatus comprising a functional circuitry on a first die. Said function circuitry configured to drive an RF voltage isolation link with an RF signal responsive to receipt of a logic signal at a first logic state. Control circuitry modifies the frequency of the RF signal to spread harmonics to other than a fundamental frequency. | 05-13-2010 |
20100080336 | CIRCUIT DEVICE TO GENERATE A HIGH PRECISION CONTROL SIGNAL - In an embodiment, a circuit device includes a first counter responsive to a clock signal and to a first control word having a first precision. The counter produces a first control signal related to the first control word at a first output. The circuit device farther includes a second counter responsive to the clock signal and to a second control word having the first precision. The second counter produces a second control signal related to the second control word at a second output. The circuit device also includes a filtering circuit responsive to the first output and the second output to receive the first and second control words. The filtering circuit is adapted to produce an output control signal related to the first and second control words, where the output control signal has a second precision that is greater than the first precision. | 04-01-2010 |
20100080326 | RDS/RBDS DECODER WITH RELIABLE VALUES - A method is provided that contemplates including filtered decode values in an RDS/RBDS output signal. The filtered decode values are generated from reliable values. The reliable values are generated from corresponding received values from each of at least two groups of RDS/RBDS data in an RDS/RBDS input signal. The method also comprises preventing an error correction code (ECC) unit from modifying the filtered decode values in the RDS/RBDS output signal. | 04-01-2010 |
20100079439 | METHOD AND APPARATUS TO SUPPORT VARIOUS SPEEDS OF LCD DRIVER - Charge pump circuitry comprises a voltage for generating a first regulated voltage. A low drop out regulator generates a second regulated voltage responsive to the first regulated voltage. A charge pump voltage generation circuit generates a voltage. First and second resistor strings are responsive to the generated voltage. The first resistor string provides a first plurality of bias voltages to an LCD responsive to the voltage in a first mode of operation and the second resistor string provides faster charging and discharging of the connected LCD elements responsive to a second mode of operation. | 04-01-2010 |
20100078992 | CIRCUIT DEVICE AND METHOD OF CURRENT LIMIT-BASED DISCONNECT DETECTION - In a particular embodiment, a power sourcing equipment (PSE) device includes at least one network port adapted to couple to a powered device to provide power and optionally data to the powered device via a network cable. The PSE device further includes a current limiter circuit coupled to the at least one network port and having an adjustable threshold. The PSE device also includes a logic circuit coupled to the current limiter circuit and adapted to reduce the adjustable threshold of the current limiter circuit to have a threshold level that is below a nominal operating current level. After a period of time has elapsed during which the current limiter circuit is not activated, the logic circuit is adapted to determine that the powered device is disconnected from the at least one network port. | 04-01-2010 |
20100077245 | SYSTEM AND METHOD OF CLASSIFICATION IN POWER OVER ETHERNET SYSTEMS - A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number. | 03-25-2010 |
20100066169 | CIRCUIT DEVICE INCLUDING MULTIPLE PARAMETERIZED POWER REGULATORS - In a particular embodiment, a circuit device includes a plurality of programmable voltage regulator circuits adapted to produce one or more unique power supplies. Each programmable voltage regulator circuit includes a power supply output terminal and a base regulator circuit module that has multiple configurable parameters to support a plurality of regulator configurations. The base regulator circuit module includes a plurality of leads. Each programmable voltage regulator circuit further includes selected circuitry coupled to the plurality of leads and to the power supply output terminal. The selected circuitry is adapted to cooperate with the base regulator circuit module to provide a selected type of regulator circuit and to apply a power supply to the power supply output terminal. | 03-18-2010 |
20100052826 | ISOLATOR WITH COMPLEMENTARY CONFIGURABLE MEMORY - An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary. | 03-04-2010 |
20100007334 | POWER SOURCING EQUIPMENT DEVICE AND METHOD OF PROVIDING A POWER SUPPLY TO A POWERED DEVICE - In a particular embodiment, a power sourcing equipment (PSE) device includes a plurality of network ports adapted to communicate data and to selectively provide power to one or more powered devices via a plurality of channels. The PSE device further includes a plurality of sense elements, where each sense element is coupled to a respective network port of the plurality of network ports. The PSE also includes a power sensing circuit having an analog-to-digital converter (ADC) adapted to be selectively coupled to a selected network port of the plurality of network ports. The power sensing circuit selectively measures at least one electrical parameter associated with the selected network port. | 01-14-2010 |
20090327558 | SYSTEM AND METHOD OF PROVIDING ELECTRICAL ISOLATION - In a particular embodiment, a power sourcing equipment (PSE) device is disclosed that includes a plurality of network input/output (I/O) interfaces adapted to physically and electrically connect to a respective plurality of cables. The PSE device further includes a plurality of driver circuits. Each driver circuit of the plurality of driver circuits is coupled to a respective network I/O interface of the plurality of network I/O interfaces to send and receive data via a respective cable of the respective plurality of cables. Further, the PSE device includes a shared isolation barrier to electrically isolate control circuitry from the plurality of driver circuits. | 12-31-2009 |
20090323717 | SYSTEM AND METHOD OF PROVIDING ELECTRICAL ISOLATION - In a particular embodiment, a system includes an input/output (I/O) interface adapted to couple to a network cable to receive power and data and includes a physical transport layer (PHY) circuit including multiple channels coupled to the I/O interface. The PHY circuit is adapted to send data to and receive data from a network device via the multiple channels. The system further includes a multiplexer circuit coupled to the PHY circuit to multiplex data from the multiple channels into a multiplexed data stream and includes an isolation barrier circuit coupled to the multiplexer circuit and to a particular circuit. The isolation barrier is adapted to electrically isolate a particular circuit from the multiplexer circuit, the PHY circuit, and the I/O interface. | 12-31-2009 |
20090322725 | LCD CONTROLLER WITH LOW POWER MODE - An LCD controller comprises a host interface control block for providing a connection between the LCD controller and a master controller. The master controller initiates a low power mode of operation for the LCD controller through the host interface control block. At least a portion of a plurality of input/output pins provide a connection to at least one LCD display for the LCD controller. An LCD static display controller within the LCD controller drives the at least one LCD display in a static display mode responsive to entry of the LCD controller into the low power mode of operation. A real time clock provides a clock signal to the LCD static display controller in the low power mode of operation. Power circuitry within the LCD controller selectively disables a regulated voltage provided to circuitry in the LCD controller that is not required to operate the LCD static display controller and the real time clock circuit in the low power mode of operation. | 12-31-2009 |
20090322711 | LCD CONTROLLER CHIP - An integrated circuit comprises a host interface control block for providing a connection between the integrated circuit and a master controller device. The integrated circuit further includes a plurality of I/O pins. A capacitive touch sense circuitry enables detection of actuation of at least one capacitor switch of a capacitive sensor array connected to at least a portion of the plurality of I/O pins. An LCD controller drives at least one LCD connected to at least a portion of the plurality of I/O pins. The integrated circuit, responsive to signals received from the master controller device over the host interface control block, may be configured to monitor outputs from the capacitive sensor array in a first mode of operation. In a second mode of operation, the capacitive sensor array may be configured to drive at least one LCD. Finally, in a third mode of operation, the integrated circuit may be configured to both monitor outputs of the capacitive sensor array and drive the at least one LCD. | 12-31-2009 |
20090322410 | SYSTEM AND METHOD FOR MONITORING A CAPACITIVE SENSOR ARRAY - A capacitive touch sensor circuitry comprises an interface for interconnecting with a plurality of I/O pins that connect to rows and columns of a capacitive sensor array. Monitoring circuitry, responsive to inputs from the plurality of I/O pins, determines when a capacitive switch in the capacitive sensor array has been actuated and stores an indication of the actuation of the capacitive switch. The monitoring circuitry then generates an interrupt responsive to the determined actuation. A control engine controls a manner in which the monitoring circuitry monitors the plurality of I/O pins. The control engine and the monitoring circuitry may be configured to monitor the plurality of I/O pins in a plurality of operating modes. | 12-31-2009 |
20090319814 | MEMORY POWER CONTROLLER - A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock. | 12-24-2009 |
20090309654 | SYSTEM AND METHOD OF ALTERING A PWM CARRIER POWER SPECTRUM - In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal. | 12-17-2009 |
20090273238 | POWER SOURCING EQUIPMENT DEVICE INCLUDING A SERIAL INTERFACE - In a particular embodiment, a circuit device is disclosed that includes a power sourcing equipment (PSE) circuit having a plurality of high-voltage line circuits adapted to communicate with a respective plurality of powered devices via network cables. The PSE circuit includes a serial interface circuit and includes a common controller coupled to the serial interface circuit and to the plurality of high-voltage line circuits. The circuit device also includes a low-voltage circuit having a programmable controller adapted to transmit control signals to the common controller via the serial interface circuit to control operation of the plurality of high-voltage line circuits. | 11-05-2009 |
20090267224 | CIRCUIT DEVICE INCLUDING ROTATED STACKED DIE - In a particular embodiment, a circuit device includes a first die coupled to a circuit substrate and having a substantially planar surface. The first die includes electrical contacts distributed on the substantially planar surface adjacent to at least three edges of the first die. The circuit device further includes a second die attached to the substantially planar surface of the first die. The second die is rotated by an offset angle about an axis relative to the first die. The offset angle is selected to allow horizontal and vertical access to the electrical contacts. | 10-29-2009 |
20090248930 | USB TRANSCEIVER CIRCUITRY INCLUDING 5 VOLT TOLERANCE PROTECTION - An integrated circuit includes USB communication circuitry for communicating via a USB interface. The USB transceiver circuitry transmits data to and from the integrated circuit over the USB interface. The USB transceiver circuitry further provides protection to internal circuitry of the integrated circuit from a 5 volt short circuit on the USB interface. | 10-01-2009 |
20090243903 | SYSTEM AND METHOD OF ALTERING A PWM CARRIER POWER SPECTRUM - In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal. | 10-01-2009 |
20090243745 | SYSTEM AND METHOD OF SHAPING A POWER SPECTRUM IN PWM AMPLIFIERS - In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape. | 10-01-2009 |
20090243744 | SYSTEM AND METHOD OF CHANGING A PWM POWER SPECTRUM - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 10-01-2009 |
20090243688 | SYSTEM AND METHOD OF CHANGING A PWM POWER SPECTRUM - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 10-01-2009 |
20090243570 | 5 VOLT TOLERANT VOLTAGE REGULATOR - A voltage regulator circuit comprises an error amplifier for generating an error signal responsive to a reference voltage in a feedback signal. A feedback circuit provides the feedback voltage signal to the error amplifier and a driver circuit provides regulated output voltage responsive to the input voltage in the error signal. Short circuit protection circuitry selectively protects transistors within the error amplifier, the feedback amplifier and the driver circuit responsive to a short circuit protection enablement signal. | 10-01-2009 |
20090243028 | CAPACITIVE ISOLATION CIRCUITRY WITH IMPROVED COMMON MODE DETECTOR - An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver detects the received data. The detector circuit monitors the differential signal and generates a first logical output when a voltage generated responsive to the differential signal exceeds a programmable voltage threshold level and generates a second logical output when the voltage generated responsive to the differential signal falls below the programmable voltage threshold level. | 10-01-2009 |
20090213914 | CAPACITIVE ISOLATION CIRCUITRY - An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link. A differential transmitter on each of the plurality of communications channels transmits the data on the first link at a selected one of a first phase and a second phase and for transmitting the data on the second link at the selected one of the first phase and the second phase. The second phase is 180 degrees out of phase with the first phase. Each of the differential transmitters controls the selection of the first phase and the second phase on each of the first link and the second link such that only the first phase or the second phase is cross coupled onto a selected communications channel from adjacent communications channels. | 08-27-2009 |
20090187773 | MCU WITH POWER SAVING MODE - A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level. | 07-23-2009 |
20090172656 | CIRCUIT DEVICE AND METHOD OF PROVIDING A PROGRAMMABLE POWER SUPPLY - In a particular embodiment, a circuit device includes a plurality of network ports, power regulator circuitry coupled to the plurality of network ports, and a control input adapted to receive software updates. The circuit device further includes a memory adapted to store a plurality of instructions, including processor operating system instructions and an upgrade routine. The circuit device further includes a programmable processor that is coupled to the memory and to the control input. The programmable processor is adapted to receive software updates via the control input and to execute the upgrade routine to upgrade the processor operating system instructions to reprogram the programmable processor. Further, the programmable processor is adapted to control the power regulator circuitry to selectively provide a power supply to a network device via a selected network port of the plurality of network ports. | 07-02-2009 |
20090172242 | SYSTEM AND METHOD FOR CONNECTING A MASTER DEVICE WITH MULTIPLE GROUPINGS OF SLAVE DEVICES VIA A LINBUS NETWORK - A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces selectively connects one of a plurality of groups of slave devices to the LINBUS network communications hardware. | 07-02-2009 |