X-FAB SEMICONDUCTOR FOUNDRIES AG Patent applications |
Patent application number | Title | Published |
20160056305 | SEMICONDUCTOR DEVICE - A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously. | 02-25-2016 |
20150108559 | Method of Fabricating a Tunnel Oxide Layer and a Tunnel Oxide Layer for a Semiconductor Device - A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer. | 04-23-2015 |
20140367796 | MOS DEVICE ASSEMBLY - A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage. | 12-18-2014 |
20140264740 | Semiconductor Device - A semiconductor device comprising:
| 09-18-2014 |
20140231905 | SEMICONDUCTOR DEVICE - A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface; where the first and second interfaces are substantially aligned or are at substantially the same level. | 08-21-2014 |
20140183618 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: at least one strained semiconductor layer to change the probability of an electron tunnelling from a first area to a second area. | 07-03-2014 |
20140061729 | ION SENSITIVE FIELD EFFECT TRANSISTOR - A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilizing CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor. | 03-06-2014 |
20140042592 | Bipolar transistor - A bipolar junction transistor is provided with an emitter region, an oxide region, a base region and a collector region. The base region is located between the emitter region and the oxide region and has a junction with the emitter region and an interface with the oxide region. An at least partially conductive element such as metal or silicon is positioned to overlap with at least part of the junction between the base region and the emitter region, thereby forming a gate. The gate also overlaps with at least part of the interface between the base region and the oxide region. When a suitable bias voltage is applied to the gate, the gain of the transistor can be increased. | 02-13-2014 |
20130320511 | SEMICONDUCTOR DEVICE - A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure. | 12-05-2013 |
20130320485 | SEMICONDUCTOR DEVICE - An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches. | 12-05-2013 |
20130228868 | ELECTROSTATIC DISCHARGE PROTECTION DEVICES - A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion. | 09-05-2013 |
20130175615 | LDMOS Transistors For CMOS Technologies And An Associated Production Method - In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region ( | 07-11-2013 |
20130140677 | CAPACITOR STRUCTURES FOR SEMICONDUCTOR DEVICE - A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors. | 06-06-2013 |
20130093015 | HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal oxide semiconductor (HVMOS) transistor ( | 04-18-2013 |
20120241914 | REDUCTION OF FLUORINE CONTAMINATION OF BOND PADS OF SEMICONDUCTOR DEVICES - A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications. | 09-27-2012 |
20120241887 | VERTICAL HALL SENSOR AND METHOD FOR PRODUCING A VERTICAL HALL SENSOR - The invention relates to a vertical Hall sensor integrated in a semiconductor chip and a method for the production thereof. The vertical Hall sensor has an electrically conductive well of a first conductivity type, which is embedded in an electrically conductive region of a second conductivity type. The electrical contacts are arranged along a straight line on a planar surface of the electrically conductive well. The electrically conductive well is generated by means of high-energy ion implantation and subsequent heating, so that it has a doping profile which either has a maximum which is located at a depth T | 09-27-2012 |
20120232855 | METHOD FOR THE CONSTRUCTION OF VERTICAL POWER TRANSISTORS WITH DIFFERING POWERS BY COMBINATION OF PRE-DEFINED PART PIECES - A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces. | 09-13-2012 |
20120223367 | Method For Fabricating Semiconductor Wafers For The Integration of Silicon Components With Hemts, And Appropriate Semiconductor Layer Arrangement - The invention describes a method for fabricating silicon semiconductor waferswith the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafersare used, the active semiconductor layer of which has the III-V semiconductor layers ( | 09-06-2012 |
20120211868 | ULTRA-LOW VOLTAGE COEFFICIENT CAPACITORS - A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor ( | 08-23-2012 |
20120211747 | PN JUNCTIONS AND METHODS - A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area. | 08-23-2012 |
20120193646 | METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DIODE BY LIFT-OFF - A method of manufacturing an Organic Light Emitting Diode (OLED). The method comprises using a solution or a solvent for removing a photo-resist used for patterning, which photo-resist is at least partly covered with a material other than photo-resist. The method of manufacturing the OLED thus comprises a lift-off process. The new method provides the benefits of low cost manufacturing and high OLED performance. | 08-02-2012 |
20120187461 | SEMICONDUCTOR COMPONENT WITH A WINDOW OPENING AS AN INTERFACE FOR AMBIENT COUPLING - A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material. | 07-26-2012 |
20120126377 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions. | 05-24-2012 |
20120032356 | PRODUCTION OF HIGH ALIGNMENT MARKS AND SUCH ALIGNMENT MARKS ON A SEMICONDUCTOR WAFER - The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer ( | 02-09-2012 |
20120032204 | METHOD OF MANUFACTURING OLED-ON-SILICON - A method of manufacturing an Organic Light Emitting Diode (OLED). A substrate ( | 02-09-2012 |
20110156093 | HIGH-VOLTAGE POWER TRANSISTOR USING SOI TECHNOLOGY - The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 μm. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT. | 06-30-2011 |
20110127641 | SELF-ORGANIZED PIN-TYPE NANOSTRUCTURES, AND PRODUCTION THEREOF ON SILICON - By means of an RIE etch process for silicon ( | 06-02-2011 |
20110127583 | SEMICONDUCTOR COMPONENT WITH INTEGRATED HALL EFFECT SENSOR - A semiconductor device with an integrated circuit on a semiconductor substrate comprises a Hall effect sensor in a first active region and a lateral high voltage MOS transistor in a second active region. The semiconductor device of the present invention is characterized in that the structure of the integrated Hall effect sensor is strongly related with the structure of a high-voltage DMOS transistor. The integrated Hall effect sensor is in some features similar to a per se known high-voltage DMOS transistor having a double RESURF structure. The control contacts of the Hall effect sensor correspond to the source and drain contacts of the high-voltage DMOS transistor. The semiconductor device of the present invention allows a simplification of the process integration. | 06-02-2011 |
20110102059 | Location-Related Adjustment of the Operatng Temperature Distribution or Power Distribution of a Semiconductor Power Component, and Component for Carrying Out Said Method - Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network ( | 05-05-2011 |
20110016440 | CHECKING AN ESD BEHAVIOR OF INTEGRATED CIRCUITS ON THE CIRCUIT LEVEL - A system and a method for testing the ESD behaviour, wherein a circuit ( | 01-20-2011 |
20100330506 | METHOD FOR TRANSFERRING AN EPITAXIAL LAYER FROM A DONOR WAFER TO A SYSTEM WAFER APPERTAINING TO MICROSYSTEMS TECHNOLOGY - For bonding a donor wafer ( | 12-30-2010 |
20100311248 | STRUCTURED LAYER DEPOSITION ON PROCESSED WAFERS USED IN MICROSYSTEM TECHNOLOGY - The invention relates to a method and a through-vapor mask for depositing layers in a structured manner by means of a specially designed coating mask which has structures that accurately fit into complementary alignment structures of the microsystem wafer to be coated in a structured manner such that the mask and the wafer can be accurately aligned relative to one another. Very precisely defined portions on the microsystem wafer are coated through holes in the coating mask, e.g. by mans of sputtering, CVD, or to evaporation processes. | 12-09-2010 |
20100308432 | SEMICONDUCTOR STRUCTURE FOR THE PRODUCTION OF A CARRIER WAFER CONTACT IN A TRENCH-INSULATED SOI DISK - Disclosed is a semiconductor structure for producing a handle wafer contact in trench insulated SOI discs which may be used as a deep contact ( | 12-09-2010 |
20100301483 | LIGHT-BLOCKING LAYER SEQUENCE HAVING ONE OR MORE METAL LAYERS FOR AN INTEGRATED CIRCUIT AND METHOD FOR THE PRODUCTION OF THE LAYER SEQUENCE - In an integrated circuit, a light sensitive area is protected against radiation by arranging a light blocking layer sequence ( | 12-02-2010 |
20100295124 | MOS-POWER TRANSISTORS WITH EDGE TERMINATION WITH SMALL AREA REQUIREMENT - It is the purpose of the invention to provide a MOS transistor ( | 11-25-2010 |
20100282165 | PRODUCTION OF ADJUSTMENT STRUCTURES FOR A STRUCTURED LAYER DEPOSITION ON A MICROSYSTEM TECHNOLOGY WAFER - The invention relates to a method for selective material deposition for sensitive structures in micro systems technology for producing mechanical adjustment structures ( | 11-11-2010 |
20100252880 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region. | 10-07-2010 |
20100237465 | CAPACITOR AND A METHOD OF MANUFACTURING A CAPACITOR - A device comprises a substrate ( | 09-23-2010 |
20100213545 | MOS TRANSISTOR WITH A P-FIELD IMPLANT OVERLYING EACH END OF A GATE THEREOF - The present invention provides a method for fabricating a MOS transistor ( | 08-26-2010 |
20100155910 | METHOD FOR THE SELECTIVE ANTIREFLECTION COATING OF A SEMICONDUCTOR INTERFACE BY A PARTICULAR PROCESS IMPLEMENTATION - The invention refers to an efficient process for selectively rendering a semiconductor surface antireflective which is part of integrated circuits. The antireflective effect is based interference effects of a simple layer or a layer system. For example, an oxide layer and super-imposed silicon nitride layer form the system, wherein the silicon nitride layer is deposited in an earlier phase of the fabrication of the integrated circuit as a protective layer (“silicide block layer”) and also serves as an etch stop layer for the optical window. | 06-24-2010 |
20100117108 | USES OF SELF-ORGANIZED NEEDLE-TYPE NANOSTRUCTURES - The invention relates to processes for the production and elements (components) with a nanostructure ( | 05-13-2010 |
20100059851 | CMOS CIRCUITS COMBINING HIGH VOLTAGE AND RF TECHNOLOGIES - A CMOS circuit comprises at least one high voltage transistor (having gate and drain operating voltages of greater than 8V) and at least one high frequency capable transistor (having a maximum switching frequency of between 100 MHz and 1000 GHz) wherein said transistors are integrated on the same semiconductor substrate so as to allow the simple integration of high voltage circuits and RF (radio frequency) CMOS circuits on the same integrated circuit. | 03-11-2010 |
20100035366 | Production of VDMOS-Transistors Having Optimized Gate Contact - The invention relates to a method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask). | 02-11-2010 |
20090315119 | CMOS CIRCUITS SUITABLE FOR LOW NOISE RF APPLICATIONS - A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion. | 12-24-2009 |
20090315080 | TRANSISTOR ARRAY WITH SHARED BODY CONTACT AND METHOD OF MANUFACTURING - An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate. | 12-24-2009 |
20090294893 | ISOLATION TRENCH INTERSECTION STRUCTURE WITH REDUCED GAP WIDTH - The invention relates to isolation trenches having a high aspect ratio for trench-insulated smart power technologies in Silicon On Insulator (SOI) silicon wafers. The specific geometric layout of the intersections and junctions of the isolation trenches allows error rate reduction and simplification of manufacture. | 12-03-2009 |
20090261353 | PRODUCTION OF SELF-ORGANIZED PIN-TYPE NANOSTRUCTURES, AND THE RATHER EXTENSIVE APPLICATIONS THEREOF - The invention relates to methods and devices comprising a nanostructure ( | 10-22-2009 |
20090250724 | BIPOLAR TRANSISTOR AND METHOD OF MAKING SUCH A TRANSISTOR - A bipolar transistor is formed on a heavily doped silicon substrate ( | 10-08-2009 |
20090243034 | SEMICONDUCTOR DEVICE - A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate form a diode. The semiconductor device further includes an inductor on or above the semiconductor material, and a pattern in the semiconductor material for reducing eddy currents. The pattern includes a doped semiconductor material of the first doping polarity and a least one trench within the doped semiconductor material of the first doping polarity, wherein, at least at a depth at which the trench is closest to the inductor, the doped semiconductor material of the first doping polarity fully surrounds the trench so that, at least at the depth, the trench does not touch the doped semiconductor material of the second doping polarity. | 10-01-2009 |
20090180188 | BROADBAND ANTIREFLECTIVE OPTICAL COMPONENTS WITH CURVED SURFACES AND THEIR PRODUCTION - Methods and optical devices are proposed, which comprise a nanostructure ( | 07-16-2009 |
20090174418 | Method and Device for Electrically Determining the Thickness of Semiconductor Membranes by Means of an Energy Input - A method and device for determining the thicknesses of semiconductor membranes uses electrical measurements. Energy is coupled into the membrane in a defined manner and the membrane thickness is determined from the distribution or diffusion of the energy. A change of state of the membrane is detected by measuring electroconductivity of measuring resistances at least one of which is on the membrane. The electroconductivity varies according to the temperature and the mechanical strain of the membrane, which both depend on the thickness of the membrane. | 07-09-2009 |
20090090992 | ISOLATION TRENCH STRUCTURE FOR HIGH ELECTRIC STRENGTH - The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches ( | 04-09-2009 |
20090001434 | Vertical Pin or Nip Photodiode and Method for the Production which is Compatible with a Conventional Cmos-Process - The invention relates to a fast photodiode and to a method for the production thereof in CMOS technology. The integrated PIN photodiode, which is formed or can be formed by CMOS technology, consists of an anode corresponding to a highly doped p-type substrate with a specific electric resistance of less than 50 mOhm*cm, a lightly p-doped l-region which is adjacent to the anode, and an n-type cathode which corresponds to the doping in the n-well region. The lightly doped l-region has a doping concentration of less than 10 | 01-01-2009 |
20080305602 | Transistor Manufacture - An oxide layer is formed on material defining and surrounding an emitter window. The technique comprises depositing a non-conformal oxide layer on the surrounding material and in the emitter window, whereby the thickness of at least a portion of the oxide layer in the emitter window is smaller than the thickness of the oxide layer on the surrounding material outside the emitter window; and removing at least a portion of the oxide layer in the emitter window so as to reveal at least a portion of the bottom of the emitter window whilst permitting at least a portion of the oxide layer to remain on the surrounding material. The technique can be used in the manufacture of a self-aligned epitaxial base BJT (bipolar junction transistor) or SiGe HBT (hetero junction bipolar transistor). | 12-11-2008 |
20080265364 | Creation of Dielectrically Insulating Soi-Technlogical Trenches Comprising Rounded Edges for Allowing Higher Voltages - The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches ( | 10-30-2008 |
20080243443 | Method for the Construction of Vertical Power Transistors with Differing Powers by Combination of Pre-Defined Part Pieces - A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces. | 10-02-2008 |