HORIZON SEMICONDUCTORS LTD. Patent applications |
Patent application number | Title | Published |
20100302235 | efficient composition of a stereoscopic image for a 3-D TV - The present invention relates to a method for efficiently composing multiple images into one stereoscopic image comprising the steps of: (a) receiving a first image of said multiple images; (b) blending said first image with a mask, using a pixel base blender, for producing a first blended image; (c) receiving a second image of said multiple images; and (d) blending said second image with said first blended image, using a pixel base blender, for composing said stereoscopic image. | 12-02-2010 |
20100284537 | Method for efficiently decoding a number of data channels - The present invention relates to a method for efficiently decoding a plurality of ciphertexts comprising the steps of: (a) receiving at least one cipher key associated with said ciphertexts; (b) expanding said at least one cipher key for producing its corresponding subkeys; (c) storing said subkeys in a memory; (d) loading said subkeys from said memory; and (e) decoding said ciphertexts using said loaded subkeys. | 11-11-2010 |
20100251213 | METHOD FOR EXECUTING DEBUG COMMANDS - The present invention relates to a method for cycle accurate simulating the processing of a processor comprising the steps of: (a) receiving a source code containing at least one source command and at least one debug command; (b) reading at least one command from said source code and determining if said command is a source command or a debug command; (c) if said command is a source command: (I) interpreting said source command into machine readable command; and (II) storing said source command in an object code file; (d) if said command is a debug command: (I) appending an address to said debug command; and (II) storing said debug command in a debug file; (e) loading said object code file and said debug file into a cycle accurate simulator; and (f) executing at least one said debug command without promoting at least one component which keeps track of the processing cycle accuracy of said simulated processor. | 09-30-2010 |
20100231600 | HIGH BANDWIDTH, EFFICIENT GRAPHICS HARDWARE ARCHITECTURE - The present invention relates to a system according to claim | 09-16-2010 |
20100225734 | STEREOSCOPIC THREE-DIMENSIONAL INTERACTIVE SYSTEM AND METHOD - The present invention relates to a method for providing a stereoscopic interactive object comprising the steps of: (a) providing a display capable of displaying in stereoscope; (b) providing a system capable of motion tracking; (c) providing a stereoscopic image of an object, on said display; (d) tracking user's motion aimed at interacting with said displayed stereoscopic image; (e) analyzing said user's interactive motion; and (f) performing in accordance with said user's interactive motion. | 09-09-2010 |
20100225576 | THREE-DIMENSIONAL INTERACTIVE SYSTEM AND METHOD - The present invention relates to a method for providing an intuitive interactive control object in stereoscope comprising the steps of: (a) providing a display capable of displaying in stereoscope; (b) providing a system capable of motion tracking; (c) tracking a visual signal motion performed by a user; (d) providing a stereoscopic image of a remote control, on said display in response to said signal performed by said user; (e) tracking user's motion aimed at interacting with said displayed stereoscopic image of said remote control; (f) analyzing said user's interactive motion; and (g) performing in accordance with said user's interactive motion. | 09-09-2010 |
20100174970 | EFFICIENT IMPLEMENTATION OF A KEY-EQUATION SOLVER FOR BCH CODES - The present invention relates to a method for solving the key equation and finding the error locator polynomial coefficients of a received word comprising the steps of: (a) providing the syndrome elements of said received word; (b) initializing said coefficients of said error locator polynomial; (c) providing an auxiliary polynomial; (d) initializing said auxiliary polynomial coefficients; (e) processing said syndrome elements and said auxiliary polynomial coefficients for iteratively updating said coefficients of said error locator polynomial; and (f) outputting said updated coefficients of said error locator polynomial. | 07-08-2010 |
20100157145 | ADAPTIVE PANORAMIC INTERPOLATOR - The present invention relates to a method for panoramically interpolating a video from a first aspect ratio to a second aspect ratio comprising the steps of: (a) receiving at least one frame; (b) tracking said frame horizontally or vertically pixel line by pixel line; (c) computing the average luminance value of each of said pixel lines; (d) comparing each said average luminance value to a set threshold for finding the superfluous lines; (e) trimming said frame by deleting said superfluous lines; (f) calculating the required curve for the panoramic scaling of said trimmed frame; and (g) interpolating said trimmed frame into a panoramic display based on said calculations. | 06-24-2010 |
20100127904 | IMPLEMENTATION OF A RAPID ARITHMETIC BINARY DECODING SYSTEM OF A SUFFIX LENGTH - The present invention relates to a system for the parallel processing of a number of binstream bins comprising: (a) inputs for receiving the codIOffset, the codIRange and the bitstream suffix bits; (b) a first circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing an indication of the binstream suffix length magnitude; (c) a second circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing said number of speculative codIOffsets; (d) a third circuit for combining the products of said first circuit and the products of said second circuit for producing a new codIOffset; and (e) a fourth circuit for combining the products of said first circuit with said number of constants for producing a number indicative of the binstream suffix length. | 05-27-2010 |
20100106953 | METHOD FOR PATCHING ROM BOOT CODE - The present invention relates to a method for patching a boot code stored on ROM comprising the steps of (a) storing at least one patching command for said boot code in a PROM; (b) loading said boot code from said ROM to a memory; (c) reading said at least one patching command from said PROM; (d) patching at least one command of said boot code residing in said memory with said at least one patching command from said PROM; and (e) executing the patched boot code. | 04-29-2010 |
20100086280 | METHOD FOR SMOOTHLY PLAYING A VIDEO STREAM IN REVERSE - The present invention relates to a method for displaying a video stream in reverse smoothly comprising the steps of: (a) determining at least one GOP for reverse display; (b) selecting all the frames of said GOP, a subsequent I frame and if present, the B frames positioned between said subsequent I frame and the next I or P frame, in the encoded order, into a selected group; (c) if present, discarding from said selected group the B frames that are positioned between the primary I frame of said GOP and the next I or P frame, in the encoded order; (d) decoding and storing the remaining frames of said selected group; and (e) loading for display at least one of said decoded frames in a reverse display order. | 04-08-2010 |
20100070951 | GENERIC ASSEMBLER - The present invention relates to a method for realizing a generic assembler capable of translating a source code into machine codes for various processor-architectures comprising the steps of: (a) providing an assembler capable of reading a definitions file for translating source code commands into machine code commands; (b) loading said definitions file, which holds definitions related to a processor-architecture, into said assembler; (c) parsing and assessing, by said assembler, said definitions file for finding errors; (d) preparing the internal data structures of said assembler based on said definitions of said definitions file; and (e) translating a source code into a machine code, by said assembler, using said definitions from said definitions file. | 03-18-2010 |
20100040136 | METHOD FOR PERFORMING BINARIZATION USING A LOOKUP TABLE - The present invention also relates to a binarization method for generating a binary sequence, comprising the steps of: (a) receiving a Syntax Element with its binarization parameters; (b) acquiring the corresponding binarization scheme of said Syntax Element using an updateable lookup table; (c) transforming said Syntax Element value into a corresponding binary sequence; (d) acquiring a Context Index, a bypass flag and a terminate flag for each of the bins of said corresponding binary sequence using said lookup table; (e) attaching each of said Context Indexes, said bypass flags, and said terminate flags to its bin of said corresponding binary sequence; and (f) generating said bins of said corresponding binary sequence, their said Context Indexes, said bypass flags, and said terminate flags. | 02-18-2010 |
20100002147 | METHOD FOR IMPROVING THE DERINGING FILTER - The present invention relates to a method for filtering ringing artifacts in a reconstructed pixel edge block comprising the steps of: (a) providing said edge block; (b) determining a threshold as a function of the pixel values in said edge block; (c) mapping each pixel, of said edge block, to a corresponding binary index according to its value and said threshold; (d) scanning using a window, a first binary index of said mapped edge block and its surrounding indices; (e) determining if all entrapped binary indices of said window are uniform; (f) if not all entrapped binary indices of said window are uniform, scanning using a sub window that entraps said first binary index, within said window, for determining if all entrapped binary indices of said sub window are uniform; and (g) if all entrapped binary indices of said sub window are uniform, filtering the pixel that corresponds to said first binary index with the pixel values that correspond to the binary indices entrapped in said sub window. | 01-07-2010 |
20090327381 | TRUE RANDOM NUMBER GENERATOR - The present invention relates to an apparatus for generating a true random number comprising: (a) one or more decoupled oscillator(s), for generating a first set of one or more random bit(s); (b) one or more clock sampler(s), for generating a second set of one or more random bit(s); (c) a logic gate for logically combining said first set of one or more random bit(s) and said second set of one or more random bit(s) into a single true random bit; (d) a synchronizing circuit for synchronizing said single true random bit to the clock domain of said apparatus; (e) an LFSR, synchronized with said clock domain, which receives said synchronized single true random bit, and logically combines at least one of its internal bit(s) with said synchronized single true random bit for generating a true random number represented by the internal bits of said LFSR; and (f) an output bus for communicating said true random number from said LFSR. | 12-31-2009 |
20090248997 | De-Interleaving using minimal memory - A de-interleaver for receiving data blocks including data units in an interleaved order, each data unit having a de-interleaved location within the data block, placing the data units in a memory buffer, and outputting the data units in a de-interleaved order from the memory buffer, the de-interleaver including an output unit configured to output a data unit from a location in the memory buffer of a next data unit in de-interleaved order, thereby to provide the data block in de-interleaved order, and an input unit configured with the output unit to input an incoming data unit, the incoming data unit being in the interleaved order, into the location in the memory buffer vacated by the next, in de-interleaved order, data unit being output. Related apparatus and methods are also described. | 10-01-2009 |
20090210155 | AUTOMOTIVE ENTERTAINMENT, COMMUNICATION, NAVIGATION AND CONTROL CENTER - Apparatus for automotive entertainment, navigation, communication and control, including a plurality of radio, TV, video and audio inputs, a video and audio output, a plurality of wireless communication channels, and a plurality of receivers, transceivers and processing units. | 08-20-2009 |
20090190704 | Synchronization of frame signals having two synchronization words - Apparatus for frame synchronization in a broadcast receiver where received frames comprise first and second synchronization words at predetermined locations in the frame, comprises: a correlator set with expected synchronization words for correlation with incoming symbols of said frame, to find probable locations of the first and second synchronization words within the frame, and a thresholder for thresholding the correlation according to both the first and second thresholds, thereby to allow, the receiver to synchronize with the frame. | 07-30-2009 |
20090141840 | Impulse noise identification method and system - Apparatus for detecting impulse-type noise in a received signal comprises a decoder unit for sampling the signal and decoding to produce symbols, and an analysis unit for analyzing a distribution of the distances between the decoded symbols and the respective samples. The distribution is indicative of noise type, and thus can be analyzed to produce an output when the distribution indicates that the noise is impulse noise. If QAM is the decoding system, then for each decoded symbol there is a distance between the input and the decoded symbol, and the distribution of the distance indicates the type of noise. A random distribution is taken as indicative of the impulse noise. | 06-04-2009 |
20090129514 | Accurate data-aided frequency tracking circuit - A frequency compensation circuit for compensating for a frequency offset in a received signal, the received signal including a periodically repeated pilot sequence for phase locking. The circuit comprises a phase estimator for estimating a phase of the received signal; a phase compensator, associated with the phase estimator, for compensating for the phase; a frequency estimator, comprising a maximum likelihood estimator comprising a first modification for estimating a frequency offset which is small relative to a symbol time, from the pilot sequence, the frequency estimator being connected downstream of the phase compensator; and a frequency compensator for applying a compensation to the signal, thereby to compensate for the frequency offset. The compensator is suitable for the exacting conditions of the DVB-S2 standard. | 05-21-2009 |
20090122928 | Apparatus and method for frequency estimation in the presence of narrowband gaussian noise - A method of compensating for a frequency estimation bias due to sampled filtered noise of a channel filter, comprises: estimating autocorrelation functions for the impulse response of the channel filter over a range of frequencies; selecting one of the frequencies for use; estimating a noise spectral density of the sampled filtered noise; reading the autocorrelation function corresponding to the selected frequency; estimating the frequency bias as a function of the noise spectral density and the autocorrelation function for the selected frequency; and using the estimate to compensate for the frequency offset. The compensated signal is useful in such standard receiver functions as, automatic gain control (AGC), timing recovery, matched filtering/equalization and phase estimation and compensation. | 05-14-2009 |
20090055005 | Audio Processor - Apparatus for processing audio signal streams including a plurality of audio signal inputs, an audio signal output, and a plurality of audio signal processing units, wherein the audio signal input, the audio signal output, and the plurality of audio signal processing units are connected to and controlled by a Micro Controller Unit (MCU), and wherein the audio signal processing units are configured to process more than one audio signal stream at the same time. Related apparatus and methods are also described. | 02-26-2009 |
20090054179 | STRING CLAMPING DEVICE - A string clamping device includes a base with two first sidewalls and a movable unit is located between the two first sidewalls and a guide member is connected to an end of the movable unit. A pair of clamping members are pivotably connected between two second sidewalls of the movable unit so as to clamp a string which is guided by the guide member. Each of the two first sidewalls has a first slot and a second slot defined in an inside thereof. The first slots are close to the guide member and inclined to a horizontal plane. Two bearings are connected to the two second sidewalls and movably received in the first and second slots. The movable unit together with the clamping members is pivoted along the inclined first slots when pulling the string such that the string needs not to be bent. | 02-26-2009 |
20080285652 | Apparatus and methods for optimization of image and motion picture memory access - A cache memory device for location between a main memory and a requesting processor is disclosed. The main memory stores memory blocks, some of which are temporarily located in the cache memory device to improve retrieval performance. The cache memory device is configured to receive requests for respective memory blocks, and the cache memory device comprises an input pooling unit for pooling incoming requests for blocks of memory as well as a request selection mechanism configured for selecting amongst those pooled requests. The request selection mechanism operates according to one or more optimization criteria to optimize the operation of the cache memory device. The device is particularly useful for image and video compression. | 11-20-2008 |
20080263621 | Set top box with transcoding capabilities - A media stream transcoding set top box including an RF input interface, an RF receiver configured to receive from the RF input interface an RF signal including an original digital media stream, and produce an input digital media stream based, at least in part, on the original digital media stream, the input digital media stream including one or more channels, the channels carrying at least one media stream, a decoder configured to receive the input digital media stream and extract therefrom an uncompressed media stream, a processor configured to process the uncompressed media stream, to produce a processed media stream, an encoder configured to compress the processed media stream, to produce a compressed processed digital media stream, and an output interface configured to output the compressed processed digital media stream in a format suitable for a client device. Related apparatus and methods are also described. | 10-23-2008 |
20080263115 | Very long arithmetic logic unit for security processor - An arithmetic and logic unit carries out arithmetic or logic operations on long operands. The unit comprises: an operation unit having a processing location, and configured for carrying out processing on bits at the processing location, the processing comprising any of a plurality of pre-defined arithmetic or logical operations, the processes being defined for a first number of bits determined by the operand word length; a fetch and write unit comprising direct memory access circuitry for fetching a second number of bits of operand data by direct access from an external memory and for writing results to memory, the second number being set by a predetermined memory access width; the second number being smaller than said operand word length, and the direct memory access circuitry being configured to deliver said second number of bits directly to the processing location without aggregation prior to processing. The fetch and write unit is controllable to carry out fetch operations for a further second number of bits of the long operand while a current part of the operand is being processed in said operation unit, thereby to hide memory access latency. | 10-23-2008 |
20080260033 | Hybrid hierarchical motion estimation for video streams - A method for estimating image-to-image motion of a pixel block in a stream of images which includes a current image which includes the pixel block and a reference image, the method including performing a hierarchical search in a search area of the reference image, including producing a decimated reference image and a decimated pixel block, searching for a location in the search area of the decimated reference image which best fits the decimated pixel block, repeating the producing and the searching for more than one level of hierarchy, determining a first candidate location in the reference image which corresponds to the best fitting location, determining a second candidate location in the reference image by a method other than the hierarchical search, performing a search in the reference image for refined locations of the first and the second candidate locations, selecting one final location from the refined candidate locations, and using the final location for estimating the motion. Related apparatus and methods are also described. | 10-23-2008 |
20080240230 | Media processor with an integrated TV receiver - An integrated circuit for processing a media stream, including an RF input interface, an RF receiver unit configured for receiving an RF media stream from the RF input interface and extracting the media stream from the RF media stream, an input interface unit configured for receiving the media stream from a content source, a plurality of processing units, a switch, operatively connected to the RF receiver unit, to the input interface unit, and to each of the processing units, the switch configured to allow more than one of the operatively connected units to simultaneously receive the media stream, thereby allowing simultaneous processing of the media stream by the processing units, and an output interface, operatively connected to the switch, configured for outputting the simultaneously processed media stream. Related apparatus and methods are also described. | 10-02-2008 |
20080240093 | Stream multiplexer/de-multiplexer - Apparatus for performing multiplexing and de-multiplexing of packetized digital data streams, including receivers for receiving data packets from packetized digital data streams, validating the packets, and transmitting only valid packets, PID filters for filtering packets according to a Packet ID included in the packets, the filters receiving valid packets from the receivers, and associating a store-or-drop value with each valid packet, input FIFO buffers for receiving valid packets from the receivers, receiving the store-or-drop value from the PID filters, and storing data based, at least in part, on the store-or-drop value, an input/output unit for transmitting the stored data from the input FIFO buffers to an external memory and reading data from the external memory, output FIFO buffers for receiving data from the input/output unit and storing the data, and transmitters for reading digital data packets from the output FIFO buffers and transmitting the packets as a packetized digital data stream, thereby de-multiplexing the packetized digital data streams and multiplexing the packetized digital data streams. Related apparatus and methods are also described. | 10-02-2008 |