INFINEON TECHNOLOGIES NORTH AMERICA CORP. Patent applications |
Patent application number | Title | Published |
20150334800 | STANDBY POWER FOR LED DRIVERS - Methods, devices, and circuits are disclosed regulating a first parameter of one or more LEDs. The methods, devices, and circuits may further be disclosed switching, in response to an indication of a dimmer interface, from regulating the first parameter of the one or more LEDs to regulating a second parameter below a light generation threshold of the one or more LEDs, and switching from regulating the first parameter to regulating the second parameter causes the one or more LEDs to enter a non-light generation mode. | 11-19-2015 |
20150317473 | DEVICE AND ACCESSORY PAIRING - A device authenticates accessories by detecting that an accessory is attached to the device, determining a unique identification (ID) for the accessory, determining, based on the unique ID, if the accessory has been paired to the device, and in response to determining that the accessory has been paired to the device, enable use of the accessory by the device. In response to determining the accessory has not been paired to the device, the devices performs a secondary authentication process on the accessory. | 11-05-2015 |
20150280696 | CIRCUIT FOR COMMON MODE REMOVAL FOR DC-COUPLED FRONT-END CIRCUITS - In one example, a method includes receiving a first differential signal including a first voltage signal and a second voltage signal, wherein the first differential signal includes a first common mode voltage; receiving a second common mode voltage. The method further includes determining, by a circuit, a second differential signal including a third voltage signal and a fourth voltage signal, wherein a difference between the third voltage signal and the fourth voltage signal is based on a difference between the first voltage signal and the second voltage signal, wherein the second differential signal includes the second common mode voltage. The method further includes outputting, substantially continuously, the second differential signal. | 10-01-2015 |
20140191736 | Active Transient Response for DC-DC Converters - A first power transistor of a DC-DC converter is connected between a voltage supply node and a common node, a second power transistor is connected between a reference node and the common node, and an inductor is connected between the common node and the output node of the DC-DC converter. A controller switches the first transistor off and the second transistor off during a step-down event at the load if current in the inductor exceeds a positive threshold value. | 07-10-2014 |
20140167634 | Method and Circuit for LED Driver Dimming - An LED driver includes a transformer, current control loop and current adjustment circuit. The primary side of the transformer transfers energy to the secondary side of the transformer responsive to an input signal. The secondary side delivers output current to one or more LEDs at a magnitude corresponding to the amount of energy transferred to the secondary side. The current control loop controls current in the primary side so that the output current equals a reference current signal. The current adjustment circuit injects a current adjustment signal into the current control loop responsive to a phase-cut signal which removes a portion of the input signal. The current control loop also decreases the current in the primary side responsive to the current adjustment signal so that a brightness of each LED connected to the secondary side is decreased by an amount corresponding to the magnitude of the current adjustment signal. | 06-19-2014 |
20140153295 | Buck-Flyback Converter - A two-transistor flyback converter includes a transformer having a primary side and a secondary side, a first transistor connected between an input voltage source and a first terminal of the primary side, a second transistor connected between ground and a second terminal of the primary side, and a diode directly connected between the first terminal of the primary side and ground. The first and second transistors are operable to switch on and off simultaneously and with no current return from the primary side to the input voltage source when the input voltage source is less than a reflected voltage from the secondary side. | 06-05-2014 |
20140125306 | Switching Regulator Control with Nonlinear Feed-Forward Correction - A switching regulator includes a power stage and a controller. The power stage is operable to produce an output voltage. The controller is operable to set a duty cycle for the power stage based on feed-forward control so that the power stage produces the output voltage as a function of an input voltage and a reference voltage provided to the switching regulator. The controller is further operable to adjust the feed-forward control to counteract the effect of one or more nonlinearities of the switching regulator on the output voltage. | 05-08-2014 |
20140118070 | Doherty Amplifier Circuit with Phase-Controlled Load Modulation - A symmetric Doherty amplifier includes a main amplifier and a peaking amplifier of the same size as the main amplifier. The symmetric Doherty amplifier is configured to operate at peak output power when the main amplifier and the peaking amplifier are each in saturation, and at output-back-off (OBO) when the main amplifier is in saturation and the peaking amplifier is not in saturation. Phase shift circuitry is configured to shift the phase at an output of the peaking amplifier at OBO so that a load impedance seen by the main amplifier and efficiency of the symmetric Doherty amplifier both increase at OBO as a function of the phase shift at the peaking amplifier output. | 05-01-2014 |
20140002037 | Switching Regulator Cycle-by-Cycle Current Estimation | 01-02-2014 |
20130256858 | PCB Based RF-Power Package Window Frame - A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate. | 10-03-2013 |
20130241639 | IMPEDANCE SPREADING WIDEBAND DOHERTY AMPLIFIER CIRCUIT WITH PEAKING IMPEDANCE ABSORPTION - A wideband Doherty amplifier circuit includes a main amplifier configured to operate in a linear mode, a peaking amplifier configured to operate in a non-linear mode and a Doherty combiner directly connected to an output of each amplifier so that no output match devices are in the path between the amplifier outputs and the Doherty combiner. The Doherty combiner is configured to present the same load impedance to each amplifier when both amplifiers are conducting and present a modulated load impedance to the main amplifier when the peaking amplifier is non-conducting so that a variation in the VSWR seen by the main amplifier is less than 5% over a plurality of frequency bands and/or so that the peaking amplifier has an off-state impedance spreading of 20 degrees or less over the plurality of frequency bands. | 09-19-2013 |
20130194027 | Cascode Switch with Robust Turn On and Turn Off - A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current. | 08-01-2013 |
20130194026 | Half Bridge Flyback and Forward - A circuit includes a high-side switch, a low-side switch, a diode, a transformer having a primary winding and a secondary windowing, and an input connected to a first terminal of the primary winding. The high-side switch has a source, a gate connected to a drive source and a drain connected to a second terminal of the primary winding. The low-side switch has a source connected to ground, a gate connected to a drive source and a drain connected to the source of the high-side switch. The diode is connected between the gate of the high-side switch and the first terminal of the primary winding. The diode forms a current loop with the primary winding and the high-side switch to circulate current when low side switch is off until the high side switch turns off. | 08-01-2013 |
20120319780 | WIDEBAND DOHERTY AMPLIFIER CIRCUIT HAVING A CONSTANT IMPEDANCE COMBINER - A three way wideband Doherty amplifier circuit includes a first peaking amplifier operable to turn on at a first power level, a second peaking amplifier operable to turn on at a second power level below the first power level and a main power amplifier operable to turn on at all power levels. The main power amplifier has a high impedance load modulated state when the first and second peaking amplifiers are turned off. The three way wideband Doherty amplifier circuit further includes a constant impedance combiner connected to an output of each amplifier. The constant impedance combiner has a characteristic impedance which matches the impedance of the main amplifier in the high impedance load modulated state with or without an output matching device connecting the main amplifier output to the constant impedance combiner, as viewed from the output of the main amplifier. | 12-20-2012 |
20120179282 | System and Method for Semiconductor Device Fabrication Using Modeling - In one embodiment, a method of manufacturing a semiconductor device includes using a processor to generate a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure. The method further includes using a processor to generate a second 3-D resist profile for a second process condition using the layout mask. The first process condition includes a plurality of process variables, and the second process condition includes different values of the plurality of process variables than the first process condition. The method includes generating a 3-D process variable (PV) band profile by combining the first 3-D resist profile with the second 3-D resist profile and displaying a 3-D image of the 3-D PV band profile on a display. | 07-12-2012 |
20120168957 | METHOD TO REDUCE DEPTH DELTA BETWEEN DENSE AND WIDE FEATURES IN DUAL DAMASCENE STRUCTURES - A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region. | 07-05-2012 |
20120156881 | METHOD FOR DEFINING A SEPARATING STRUCTURE WITHIN A SEMICONDUCTOR DEVICE - A method includes depositing a material layer over a semiconductor substrate and using a first mask in a first exposure/patterning process to pattern the material layer thereby forming a plurality of first and second features. The first features include patterns for the semiconductor device and the second features include printing assist features. The method includes using a second mask in a second exposure/patterning process to effectively remove the second features from the material layer and to define at least one separating structure between two first features. | 06-21-2012 |
20120068691 | di/dt Current Sensing - A circuit includes a power circuit and a current sensing circuit. The power circuit has a main current loop. The current sensing circuit is spaced apart from and electrically decoupled from the power circuit. The current sensing circuit is operable to generate a voltage proportional to an electromagnetic field generated responsive to a current change in the main current loop of the power circuit and generate a current information signal based on the voltage. The current information signal describes the current in the main current loop. | 03-22-2012 |
20120068681 | Integrated Circuit Package With Reduced Parasitic Loop Inductance - A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop. | 03-22-2012 |
20110298451 | Through Bias Pole for IGMR Speed Sensing - One embodiment relates to a sensing system that includes a magnetic encoder wheel having alternating pole magnetic domains along a circumference thereof. The magnetic encoder wheel is configured to rotate about a first axis. The sensing system further includes a magnetic field sensing element in spatial relationship with the magnetic encoder wheel that is oriented to sense magnetic field components extending generally in a direction parallel to a second axis that is perpendicular to the first axis. The sensing system also includes a magnetic flux influencing element configured to influence magnetic field components associated with the alternating pole magnetic domains of the magnetic encoder to reduce magnetic field components associated with the first axis. | 12-08-2011 |
20110169096 | BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS - An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor. | 07-14-2011 |
20110147921 | Flange for Semiconductor Die - A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema. | 06-23-2011 |
20110121824 | ANGLE MEASUREMENT SYSTEM - Some aspects of the present disclosure relate to techniques for measuring an angular position of a rotating shaft. As will be described in greater detail below, some angle measurement systems of the present disclosure include at least two magnets that cooperatively rotate at different rates according to a predetermined relationship (e.g., a predetermined gear ratio). Two or more magnetic field sensing elements, which are often stationary, measure the directionality of the resultant magnetic field at different positions for a particular angular shaft position. Based on the directionality measured by the magnetic field sensing elements, the techniques can determine an absolute angular position of the rotating shaft, which can be greater than three-hundred and sixty degrees. | 05-26-2011 |
20110089529 | Open Cavity Leadless Surface Mountable Package for High Power RF Applications - An RF semiconductor package includes a substrate having generally planar top and bottom surfaces. The substrate includes a metallic base region and one or more metallic signal terminal regions extending from the top surface to the bottom surface, and an insulative material separating the metallic regions from one another. The bottom surface of an RF semiconductor die is surface-mounted to the base region at the top substrate surface. The RF semiconductor die has a terminal pad disposed at a top surface of the RF semiconductor die. The terminal pad is electrically connected to one of the signal terminal regions at the top substrate surface. A lid is attached to the top substrate surface so that the RF semiconductor die is enclosed by the lid to form an open-cavity around the RF semiconductor die. The base and signal terminal regions are configured for surface-mounting at the bottom substrate surface. | 04-21-2011 |
20110069538 | MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE - A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse. | 03-24-2011 |
20110031563 | Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers - Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein. | 02-10-2011 |
20110012254 | Air Cavity Package with Copper Heat Sink and Ceramic Window Frame - An air cavity package is manufactured by attaching a die to a surface of a copper heat sink, dispensing a bead of epoxy around a periphery of the heat sink surface after the die is attached to the copper heat sink so that the bead of epoxy generally surrounds the die and placing a ceramic window frame on the bead of epoxy. The epoxy is cured to attach a bottom surface of the ceramic window frame to the copper heat sink. | 01-20-2011 |
20100321656 | TRANSMISSION MASK WITH DIFFERENTIAL ATTENUATION TO IMPROVE ISO-DENSE PROXIMITY - A system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive openings in correspondence to the predetermined patterns. The exposure mask has areas densely populated with the light-transmissive openings and areas sparsely populated with the light-transmissive openings. Light is attenuated through the densely populated light-transmissive openings by a different amount than through the sparsely populated light-transmissive openings. | 12-23-2010 |
20100289088 | THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER - An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above. | 11-18-2010 |
20100283134 | High Power Ceramic on Copper Package - According to an embodiment of a high power package, the package includes a copper heat sink, a ceramic lead frame and a semiconductor chip. The copper heat sink has a thermal conductivity of at least 350 W/m K. The ceramic lead frame is attached to the copper heat sink with an epoxy. The semiconductor chip is attached to the copper heat sink on the same side as the lead frame with an electrically conductive material having a melting point of about 280° C. or greater. | 11-11-2010 |
20100272967 | METHOD OF FORMING A PATTERN OF AN ARRAY OF SHAPES INCLUDING A BLOCKED REGION - A second photoresist having a second photosensitivity is formed on a substrate. A first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on the second photoresist. Preferably, the first photoresist is a gray resist that becomes transparent upon exposure. At least one portion of the first photoresist is lithographically exposed employing a first reticle having a first pattern to form at least one transparent lithographically exposed resist portion, while the second photoresist remains intact. The second photoresist is lithographically exposed employing a second reticle including a second pattern to form a plurality of lithographically exposed shapes in the second photoresist. The plurality of lithographically exposed shapes have a composite pattern which is the derived from the second pattern by limiting the second pattern only within the area of the at least one transparent lithographically exposed resist pattern. | 10-28-2010 |
20100246414 | NETWORK RETRANSMISSION PROTOCOLS USING A PROXY NODE - One embodiment relates to a method for communicating over a transmission medium shared between a plurality of nodes including a source node, a proxy node, and other nodes. In the method, a transmission data unit is transmitted from the source node to the proxy node and to the other nodes. A confirmation is selectively transmitted from the proxy node to the other nodes based on whether a reception data unit corresponding to the transmission data unit is correctly received at the proxy node. Based on whether the confirmation is received at one of the other nodes, a negative acknowledgement is selectively transmitted from the one of the other nodes to the source node. Other methods and devices are also disclosed. | 09-30-2010 |
20100208789 | VOLTAGE LEVEL CONVERTER WITH MIXED SIGNAL CONTROLLER - According to an embodiment, a mixed signal controller includes a fine controller, a coarse controller and a digital controller. The fine controller is operable to output an analog modulation signal responsive to an analog control signal and a voltage signal input to the fine controller. The coarse controller is operable to output a digital pulse width modulation (PWM) signal responsive to the analog modulation signal and an analog PWM reference signal input to the coarse controller. The digital controller is operable to program the analog control signal and the analog PWM reference signal responsive to the digital PWM signal so that the fine and coarse controllers together regulate the voltage signal at a predetermined voltage level. | 08-19-2010 |
20100200979 | Power Transistor Package with Integrated Bus Bar - According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections. | 08-12-2010 |
20100175041 | ADJUSTMENT OF MASK SHAPES FOR IMPROVING PRINTABILITY OF DENSE INTEGRATED CIRCUIT LAYOUT - Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided. | 07-08-2010 |
20100175040 | METHODOLOGY OF PLACING PRINTING ASSIST FEATURE FOR RANDOM MASK LAYOUT - Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated with one or more printing assist features (PrAFs); adding the one or more PrAFs of the set of parameters to the design layout to produce a modified design layout; performing simulation of the one or more PrAFs and the one or more designed features on the modified design layout; verifying whether the one or more PrAFs are removable based on results of the simulation; and creating a set of PrAF placement rules based on the set of parameters, if the one or more PrAFs are verified as removable. The set of PrAF placement rules may be used in creating a final set of PrAF features to be used for creating the mask layout. | 07-08-2010 |
20100148326 | Thermally Enhanced Electronic Package - According to one embodiment, an electronic package includes a semiconductor die, a heat sink and a metallization layer interposed between the semiconductor die and the heat sink. The metallization layer attaches the semiconductor die to the heat sink. The metallization layer has a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater. | 06-17-2010 |
20100102393 | METAL GATE TRANSISTORS - An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor. | 04-29-2010 |
20100099250 | Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers - Methods of forming a contact pad include forming a copper pattern on a semiconductor substrate and forming a passivation layer on the copper pattern. The passivation layer is defined to have an opening therein that exposes at least a portion of an upper surface of the copper pattern. A diffusion barrier layer is formed in the opening by electroless plating the diffusion barrier layer onto the exposed portion of the upper surface of the copper pattern. This diffusion barrier layer operates as a barrier to copper out-diffusion from the copper pattern. These methods further include conformally depositing an underbump metallization layer onto at least a sidewall of the opening in the passivation layer and onto an upper surface of the diffusion barrier layer. A step is then performed to plate a contact bump (e.g., solder bump) onto a portion of the underbump metallization layer extending opposite the diffusion barrier layer. | 04-22-2010 |
20100097155 | Stripline Balun - According to one embodiment, a balun includes one or more transformers configured to block DC power between a line and a device at microwave frequencies. The one or more transformers block DC power between the line and the device by electromagnetically coupling the device to the line. | 04-22-2010 |
20100087042 | Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein - Methods of forming a three-dimensional capacitor network may include forming a first horizontal MIM capacitor on a semiconductor substrate and forming a first interlayer insulating layer on the first horizontal MIM capacitor. A first vertical capacitor electrode is then formed in the first interlayer insulating layer and a second horizontal MIM capacitor is formed on the first interlayer insulating layer. This second horizontal MIM capacitor may be formed by forming an upper capacitor electrode and a lower capacitor electrode. The upper capacitor electrode may be electrically connected by the first vertical capacitor electrode to an upper capacitor electrode of the underlying first MIM capacitor. The lower capacitor electrode, which may be formed in the first interlayer insulating layer, may extend opposite the upper electrodes of the first and second MIM capacitors. | 04-08-2010 |
20100083384 | Secure Operation of Programmable Devices - According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory, a plurality of connection control elements and a logic unit. The logic blocks are grouped into one or more programmed partitions. The memory stores authentication information and partition information. The connection control elements controllably interconnect different ones of the logic blocks. The logic unit controls external access to the one or more partitions based on the authentication information, controls reprogramming of the one or more partitions based on at least some of the partition information and configures the connection control elements based on at least some of the partition information. | 04-01-2010 |
20100083367 | Secure Partitioning of Programmable Devices - According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores authentication and partition information uploaded to the programmable logic device prior to partition programming. The logic unit authenticates programming access to the one or more partitions based on the authentication information and controls programming of the one or more partitions based on the partition information. | 04-01-2010 |
20100082928 | Secure Manufacturing of Programmable Devices - According to an embodiment, a programmable logic device includes a plurality of logic blocks and a logic unit. The logic blocks are grouped into one or more partitions. The logic unit controls external access to the one or more partitions, controls programming of the one or more partitions and controls interconnection and operation of the one or more partitions during operation of the programmable logic device. | 04-01-2010 |
20100081272 | Methods of Forming Electrical Interconnects Using Electroless Plating Techniques that Inhibit Void Formation - Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer. | 04-01-2010 |
20100031026 | METHOD AND SYSTEM FOR TRANSFERRING INFORMATION TO A DEVICE - A system and method for transferring information to a device include sending a first challenge from an information provider to programming equipment, and responding to the first challenge by the programming equipment. A second challenge is sent from the programming equipment to the information provider, which responds to the second challenge. Information is encrypted by the information provider and sent from the information provider to the programming equipment. | 02-04-2010 |
20100013104 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit processing system is provided including a substrate having an integrated circuit; an interconnect layer over the integrated circuit; a low-K dielectric layer over the interconnect layer; a hard mask layer over the low-K dielectric layer; a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; and an interconnect metal in the via opening. | 01-21-2010 |
20100006944 | MIXED VOLTAGE TOLERANT INPUT/OUTPUT ELECTROSTATIC DISCHARGE DEVICES - An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground. The device also includes a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being coupled to the I/O pad. | 01-14-2010 |
20100005440 | CALIBRATION AND VERIFICATAION STRUCTURES FOR USE IN OPTICAL PROXIMITY CORRECTION - A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered. | 01-07-2010 |
20090296924 | KEY MANAGEMENT FOR COMMUNICATION NETWORKS - One embodiment of the present invention relates to a method for key management in a communications network. In this method, a public key authentication scheme is carried out between a security controller and a plurality of nodes to establish a plurality of node-to-security-controller (NSC) keys. The NSC keys are respectively associated with the plurality of nodes and are used for secure communication between the security controller and the respective nodes. Other methods and devices are also disclosed. | 12-03-2009 |
20090295382 | METHODS AND SYSTEMS FOR MAGNETIC FIELD SENSING - One embodiment relates to a sensor. The sensor includes a first magnet having a first surface and a second magnet having a second surface. A differential sensing element extends alongside the first and second surfaces. The differential sensing element includes a first sensing element and a second sensing element. In addition, a layer of ferromagnetic or paramagnetic material runs between the first and second magnets and spaces the first and second magnets from one another. Other apparatuses and methods are also set forth. | 12-03-2009 |
20090294882 | METHODS AND SYSTEMS FOR MAGNETIC SENSING - One embodiment relates to a method of manufacturing a magnetic sensor. In the method, an engagement surface is provided. A magnet body is formed over the engagement surface by gradually building thickness of a magnetic material. The magnet body has a magnetic flux guiding surface that substantially corresponds to the engagement surface. Other apparatuses and methods are also set forth. | 12-03-2009 |
20090261820 | WAFER FOR ELECTRICALLY CHARACTERIZING TUNNEL JUNCTION FILM STACKS WITH LITTLE OR NO PROCESSING - Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting. | 10-22-2009 |
20090239344 | Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance - Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions. | 09-24-2009 |
20090184756 | Semiconductor Power Device with Bias Circuit - An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit. | 07-23-2009 |
20090172401 | METHOD AND SYSTEM FOR CONTROLLING A DEVICE - A system and method for controlling a device. Data that was encrypted using a first encryption scheme is decrypted, then re-encrypted using a second encryption scheme. The re-encrypted data is then decrypted. | 07-02-2009 |
20090172392 | METHOD AND SYSTEM FOR TRANSFERRING INFORMATION TO A DEVICE - A system and method for transferring information include generating a public/private key pair for programming equipment and sending the programming equipment public key to a certificate authority. A programming equipment certificate is generated using the programming equipment public key and a private key of the certificate authority. The programming equipment certificate and a certificate authority certificate are sent to the programming equipment. Information is transferred to or from the programming equipment in response to an authentication using the programming equipment certificate and the certificate authority certificate. | 07-02-2009 |
20090154927 | MULTI-CARRIER COMMUNICATION VIA SUB-CARRIER GROUPS - One embodiment of the present invention relates to a method for communicating over a multi-carrier communication channel. In the method, sub-carrier frequencies that are reserved for communication between a pair of nework nodes are associated with different sub-carrier groups, where the sub-carriers of each sub-carrier group are assigned a common transmission characteristic that is independent of the transmission characteric for the other sub-carrier groups. Other methods and devices are also disclosed. | 06-18-2009 |
20090116650 | METHOD AND SYSTEM FOR TRANSFERRING INFORMATION TO A DEVICE - Methods and systems for transferring information to a device include assigning a unique identifier to a device and generating a unique key for the device. The device is located at a first site, and the unique identifier is sent from the device to a second site. The unique key is obtained at the second site, and it is used for encrypting information at the second site. The encrypted information is sent from the second site to the device, where it can then be decrypted. | 05-07-2009 |
20090087992 | METHOD OF MINIMIZING VIA SIDEWALL DAMAGES DURING DUAL DAMASCENE TRENCH REACTIVE ION ETCHING IN A VIA FIRST SCHEME - A method of minimizing undercut of a hard mask in an integrated circuit (IC) structure including steps of providing an IC structure having a substrate, a interlayer dielectric layer, and a hard mask, forming a via in said IC structure, and depositing an organic planarizing layer (OPL) over the IC structure such that it fills the vias formed therein. The method also includes steps of forming a masking structure layer over the OPL, forming an opening in the masking structure that has a critical dimension (CD) smaller than an opening design dimension, anisotropic etching the OPL such that sidewall of the via remains covered with the OPL while forming a trench, and removing any remaining OPL on the sidewalls and trench, wherein the undercut of the sidewalls with respect to the hard mask is minimized by the covering of OPL during the anisotropic etching process. | 04-02-2009 |
20090008361 | OXIDANT AND PASSIVANT COMPOSITION AND METHOD FOR USE IN TREATING A MICROELECTRONIC STRUCTURE - A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure. | 01-08-2009 |
20080305621 | CHANNEL STRAIN ENGINEERING IN FIELD-EFFECT-TRANSISTOR - There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material. | 12-11-2008 |
20080266990 | Flexible redundancy replacement scheme for semiconductor device - A redundancy replacement scheme for repairing a faulty memory cell including memory cells arranged in memory blocks containing word lines and column select lines. The redundancy replacement scheme including replacing the faulty memory cell in a second memory block with a spare memory cell in the second memory block based on a decoded address of a first memory block. | 10-30-2008 |
20080265409 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer. | 10-30-2008 |
20080253388 | HOME NETWORKING SYSTEM - One embodiment relates to a network. The network includes a first splitter having an input port and N output ports. A first network node is associated with a first of the N output ports. A second network node is associated with a second of the N output ports and is adapted to receive signals communicated from the first network node through the first splitter. Other apparatuses and methods are also set forth. | 10-16-2008 |
20080233709 | METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR - A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a film of the reactant on a surface of the material, controlling the composition and residence time of the film on the surface of the material to etch at least a portion of the material, and removing any unwanted reactant and reaction product from the chamber or the surface of the material. | 09-25-2008 |
20080199784 | Small Feature Integrated Circuit Fabrication - A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the integrated circuit, selectively exposing portions of the photoresist through at least one photolithography mask having a pattern including means for alleviating line end shortening of the first and second lines adjacent the gap, and developing the photoresist after the selective exposing step. | 08-21-2008 |