Northrop Grumman Space & Mission Systems Corp. Patent applications |
Patent application number | Title | Published |
20110032604 | PASSIVE ALL-FIBER INTEGRATED HIGH POWER COHERENT BEAM COMBINATION - A fiber laser amplifier system including a beam splitter that splits a feedback beam into a plurality of fiber beams where a separate fiber beam is sent to a fiber amplifier for amplifying the fiber beam. A tapered fiber bundle couples all of the output ends of all of the fiber amplifiers into a combined fiber providing a combined output beam. An end cap is optically coupled to an output end of the tapered fiber bundle to expand the output beam. A beam sampler samples a portion of the output beam from the end cap and provides a sample beam. A single mode fiber receives the sample beam from the beam sampler and provides the feedback beam. | 02-10-2011 |
20110032602 | ALL-FIBER INTEGRATED HIGH POWER COHERENT BEAM COMBINATION - A fiber laser amplifier system including a master oscillator that generates a signal beam. A splitter splits the signal beam into a plurality of fiber beams where a separate fiber beam is sent to a fiber amplifier for amplifying the fiber beam. A tapered fiber bundle couples all of the output ends of all of the fiber amplifiers into a combined fiber providing a combined output beam. An end cap is optically coupled to an output end of the tapered fiber bundle to expand the output beam. | 02-10-2011 |
20100328760 | WAVEGUIDE PARAMETRIC DEVICE AND METHOD - A waveguide parametric device including a multi-mode waveguide having orientation layers formed in a propagation direction of a signal beam and a pump beam propagating down the waveguide. The orientation layers are oppositely oriented to provide non-linear coupling between the pump beam and the signal beam and have a periodicity that provides quasi-phase matching for a fundamental propagation mode, where the waveguide has a size to accommodate multi-mode wave propagation. | 12-30-2010 |
20100127240 | Carbon nanotube fabrication from crystallography oriented catalyst - A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer. | 05-27-2010 |
20100074285 | Microchannel Cooler For High Efficiency Laser Diode Heat Extraction - A laser diode package includes a laser diode, a cooler, and a metallization layer. The laser diode is used for converting electrical energy to optical energy. The cooler receives and routes a coolant from a cooling source via internal channels. The cooler includes a plurality of ceramic sheets and a highly thermally-conductive sheet. The ceramic sheets are fused together and the thermally-conductive sheet is attached to a top ceramic sheet of the plurality of ceramic sheets. The metallization layer has at least a portion on the thermally-conductive sheet. The portion is electrically coupled to the laser diode for conducting the electrical energy to the laser diode. | 03-25-2010 |
20090206369 | HIGH ELECTRON MOBILITY TRANSISTOR SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - In a method of forming a semiconductor device on a semiconductor substrate ( | 08-20-2009 |
20090148985 | Method for Fabricating a Nitride FET Including Passivation Layers - A method for fabricating a nitride-based FET device that provides reduced electron trapping and gate current leakage. The fabrication method provides a device that includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. Semiconductor device layers are deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage. | 06-11-2009 |
20090146224 | Composite Passivation Process for Nitride FET - A nitride-based FET device that provides reduced electron trapping and gate current leakage. The device includes a relatively thick passivation layer to reduce traps caused by device processing and a thin passivation layer below the gate terminal to reduce gate current leakage. The device includes semiconductor device layers deposited on a substrate. A plurality of passivation layers are deposited on the semiconductor device layers, where at least two of the layers are made of a different dielectric material to provide an etch stop. One or more of the passivation layers can be removed using the interfaces between the layers as an etch stop so that the distance between the gate terminal and the semiconductor device layers can be tightly controlled, where the distance can be made very thin to increase device performance and reduce gate current leakage. | 06-11-2009 |
20090078888 | Method and Apparatus For Detecting and Adjusting Substrate Height - A method and apparatus | 03-26-2009 |
20090045437 | METHOD AND APPARATUS FOR FORMING A SEMI-INSULATING TRANSITION INTERFACE - The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a first level to a second level; (b) annealing at least the first graded InAlAs layer; (c) depositing the second graded InAlAs layer on the first graded InAlAs layer at the first constant temperature, the second graded InAlAs layer having an In/Al composition ratio which increases across the buffer layer from the second level to a third level; and (d) annealing at least the second graded InAlAs layer; the buffer layer being formed under Groups III/V overpressure. | 02-19-2009 |
20090029554 | Method of Batch Integration of Low Dielectric Substrates with MMICs - A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling. | 01-29-2009 |
20090029526 | Method of Exposing Circuit Lateral Interconnect Contacts by Wafer Saw - A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages. | 01-29-2009 |
20090026627 | Support Structures for On-Wafer Testing of Wafer-Level Packages and Multiple Wafer Stacked Structures - A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged. | 01-29-2009 |
20090026619 | Method for Backside Metallization for Semiconductor Substrate - A wafer circuit, such as a wafer-level package, that includes a semiconductor substrate on which is fabricated one or more integrated circuits. A backside metal layer is deposited on the semiconductor substrate, and is electrically coupled to the integrated circuit by metallized vias extending through the substrate wafer. The backside metal layer is cut to provide electrically isolated backside metal layers for RF, DC and/or ground signals. An adhesion layer is deposited on the backside of the substrate before the metal layer is deposited so that the metal layer is firmly secured to the substrate, and resists peeling. The adhesion layer can be sputtered silicon, sputtered silicon nitride, silicon nitride deposited by chemical vapor deposition, nickel deposited by evaporation and nickel chromium deposited by evaporation. | 01-29-2009 |
20090026598 | Wafer Level Packaging Integrated Hydrogen Getter - A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer. | 01-29-2009 |
20080230803 | Integrated Contact Interface Layer - A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 Å. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a thickness less than 5000 Å, and a concentration of indium of about 86% at a top of the combined layer. | 09-25-2008 |