ICERA INC. Patent applications |
Patent application number | Title | Published |
20150180530 | WI-FI TRANSCEIVER HAVING DUAL-BAND VIRTUAL CONCURRENT CONNECTION MODE AND METHOD OF OPERATION THEREOF - A transceiver, a method of providing multiple-band virtual concurrent wireless communication and a wireless device incorporating the transceiver or the method. In one embodiment, the transceiver includes: (1) first transmit and receive intermediate frequency (IF) strips, (2) second transmit and receive IF strips, (3) first and second local oscillators (LOs) and (4) switches operable to multiplex clock signals from the first and second local oscillators to cause the transceiver to operate in a selectable one of: (4a) a unified, multiple-input, multiple-output (MIMO) mode in which the first and second transmit and receive IF strips are driven to transmit and receive in a first band and (4b) a concurrent multiple-band connection mode in which the first transmit and receive IF strips are driven in the first band and the second transmit and receive IF strips are concurrently driven in a second band. | 06-25-2015 |
20140146858 | PROCESSING SIGNALS IN A WIRELESS COMMUNICATIONS ENVIRONMENT - One aspect provides a method of processing a signal transmitted over a channel in a wireless communication system. In one embodiment, the method comprises receiving at a receiver the signal transmitted over the channel, estimating at intervals at least one parameter of a time varying communication environment of the system, monitoring at least one processor-related criterion of a processor at the receiver, and selecting a signal processing function from a plurality of signal processing functions implementable by the processor. The selecting of the signal processing function is based on both the at least one parameter and the at least one processor-related criterion. Each signal processing function comprises a plurality of code blocks which process the received signal. Each code block of the plurality of code blocks comprises a sequence of instructions for execution by on a processor platform of the processor. | 05-29-2014 |
20130243053 | METHOD AND CIRCUIT FOR FRACTIONAL RATE PULSE SHAPING - A fractional rate converting filter in a wireless transceiver comprising a delay line, multiplier circuit, adder circuit, and selector. The delay line receives a digital input signal at a first sample rate and has delay blocks each providing an output and receiving samples gated at a plurality of clock cycles of an integer sub-multiple frequency of a clock. The outputs are multiplied by corresponding filter tap coefficients. Each filter tap coefficient is spaced by a first integer Y. The adder circuit receives and sums the tap outputs to provide an output signal. The selector iteratively shifts the coefficients by a second integer Z. The output of each delay block is multiplied by corresponding shifted filter tap coefficients. The delay blocks are inhibited from receiving another input sample during the plurality of clock cycles. The output signal has a second sample rate at the integer sub-multiple frequency of the clock. | 09-19-2013 |
20120300830 | EQUALISER FOR WIRELESS RECEIVERS WITH NORMALISED COEFFICIENTS - A method, receiver and program for equalising a radio signal comprising a sequence of data samples multiplexed with a sequence of pilot samples. The method comprises; calculating equaliser coefficients by computing cross-correlations of the received signal and known pilot samples available at the receiver and auto-correlations of the received signal; and equalising the received signal using the calculated coefficients. | 11-29-2012 |
20120300765 | CELLULAR COMMUNICATIONS SYSTEM - A method, receiver and program for processing a signal received using a wireless communication channel by a receiver in a wireless cellular network. The method comprises: receiving signal samples of a signal to be processed from a serving cell; identifying a set of dominant interfering cells generating an interfering signal above a level; using the number of cells in the set to select an interference scenario; and using the selected interference scenario and at least one parameter related to the serving cell and the interfering cells to select a processing function for processing the signal. | 11-29-2012 |
20120294350 | SIGNAL PROCESSING IN WIRELESS COMMUNICATION RECEIVERS - A method, receiver and program for equalising digital samples of a radio signal received over a wireless communications channel. The method comprises: receiving digital samples of the radio signal; calculating equaliser coefficients in the frequency domain; transforming the equaliser coefficients from the frequency domain to the time domain; and equalising the digital samples in the time domain using the transformed time domain equaliser coefficients. | 11-22-2012 |
20120269307 | PROCESSING A RADIO FREQUENCY SIGNAL - Circuitry and a method for use in a radio frequency receiver for processing a radio frequency signal are provided. The circuitry comprises a mixer arranged to receive the radio frequency signal and down-convert the received radio frequency signal to a lower frequency. The received radio frequency signal has an interference component and the interference component in the down-converted signal is within an interference frequency range. The circuitry also comprises an LC based notch filter arranged to receive the down-converted signal from the mixer, filter the down-converted signal, and output the filtered signal for processing by a baseband processing block. The LC based notch filter has a notch centered within said interference frequency range, such that the LC based notch filter is arranged to attenuate the interference component in the down-converted signal. | 10-25-2012 |
20120268190 | LOCAL OSCILLATOR CLOCK SIGNALS - An apparatus and method for generating complementary periodic signals for a mixer circuit is provided. The apparatus comprises first and second generation circuits each for generating a periodic signal with a transition time on each rising edge different than a transition time on each falling edge. Each of the first and second generation circuits has an output for supplying its periodic signal to a mixer such that each rising edge of a periodic signal from one of the circuits crosses each falling edge of a periodic signal from the other of the circuits at a crossing point below a turn on voltage of the mixer. | 10-25-2012 |
20120256676 | MIXER CIRCUIT - A driver circuit for supplying a drive signal to a mixer circuit comprising a first and second circuit branch and an operational amplifier. The first circuit branch receives an input signal and a bias signal. The second circuit branch receives the input signal. The operational amplifier has a first input connected to a junction node of the first circuit branch and a second input connected to a junction node of the second circuit branch. The operational amplifier is arranged to provide an operational amplifier output signal a second component of the second circuit branch so that a voltage at the junction node of the second circuit branch is equal to a voltage at the junction node of the first circuit branch. The voltage is dependent on the input signal and providing the drive signal. | 10-11-2012 |
20120256669 | DUTY CYCLE CORRECTION - Method and circuitry for controlling duty cycle of an input signal towards a desired value comprising a sequence of at least two inverters arranged in series and feedback circuitry. A first inverter is arranged to receive the input signal and a last inverter is arranged to output a signal having the same frequency as the input signal. The output signal is an adjusted version of the input signal. The feedback circuitry is arranged to receive the output signal and comprises a comparing and supplying means. The comparing means compares the output signal with a reference signal indicative of a desired value and generates a feedback signal based on the comparison of the output and reference signal. The supplying means supplies the feedback signal to adjust operating conditions of at least one of the inverters, such that the duty cycle of the output signal is controlled towards the desired value. | 10-11-2012 |
20120256613 | LOW SUPPLY REGULATOR HAVING A HIGH POWER SUPPLY REJECTION RATIO - A power supply noise rejection circuit for functional circuits, such as a voltage controlled oscillator (VCO). The power supply noise rejection circuit includes an isolation transistor connected to a voltage supply for providing an output current and voltage substantially free of noise across the full frequency range. A current source, a diode connected reference transistor with resistance means connected between its gate and drain terminals, and a dummy circuit serially connected between the voltage supply and ground generate a bias voltage that is applied to the gate of the isolation transistor. The dummy circuit mimics the DC characteristics of the functional circuit such that the output current tracks with process and temperature variations. The isolation transistor and the reference transistor can have negative threshold voltages, and the circuit can include bleed means for drawing current from the gate of the reference transistor and isolation transistor. | 10-11-2012 |
20120230301 | CANCELLING INTERFERENCE IN A WIRELESS CELLULAR NETWORK - A method, program and user equipment for wireless communication in a cellular communication system comprising a plurality of base stations. The method comprises: synchronizing to one of said the base stations using a synchronization channel transmitted from that base station; receiving a pilot channel from said base station; after synchronizing to said base station, receiving a signal from that base station; and using the pilot channel from said base station to cancel interference on said signal caused by the synchronization channel. | 09-13-2012 |
20120221834 | PROCESSOR ARCHITECTURE - A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction. | 08-30-2012 |
20120192028 | ITERATIVE DECODING OF SIGNALS RECEIVED OVER A NOISY CHANNEL USING FORWARD AND BACKWARD RECURSIONS WITH WARM-UP INITIALIZATION - A method, apparatus and program. The method comprises: receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states; for each symbol in the sequence, determining a set of state metrics each representing a probability that the respective symbol corresponds to each of the plurality of states; and decoding the signal by processing runs of recursions, using runs of forward recursions and runs of reverse recursions. The decoding comprises performing a plurality of repeated iterations over the sequence, and for each iteration: dividing the sequence into a plurality of smaller windows, processing the windows using separate runs of recursions, and performing an associated warm-up run of recursions for each window. The decoding further comprises, for each repeated recursion: alternating the direction of the warm-up runs between forward and reverse with each successive iteration over the sequence, storing one of the sets of state metrics from each window, and initialising the warm-up run of each window using a corresponding stored set of state metrics from a previous iteration. | 07-26-2012 |
20120144127 | DATA TRANSMISSION - A method of transmitting data from a first module to addressable storage devices in a second module. The method comprises: transmitting from the first module to a second module in a first transmission cycle an address identifying a storage device in the second module for a data item; at the second module, determining the status of a storage location in the device identified by the address for holding a data item and dispatching in a second transmission cycle a pre-emptive acknowledgement signal, the state of which depends on the status of that storage location; transmitting in the second transmission cycle the data item from the first module to the second module; transmitting the address in a later transmission cycle from the first module to the second module; and selectively transmitting one of the data item and a next data item depending on the state of the pre-emptive acknowledgement signal. | 06-07-2012 |
20120122407 | ADAPTIVE TRANSMISSION FEEDBACK - A method, program and apparatus for transmitting from a transmitter to a receiver over a channel using a transmit diversity scheme. The method comprises: receiving power-related information fed back from the receiver to the transmitter; and at the transmitter, using the power-related information to generate channel state information. The method further comprises using the generated channel state information to control for subsequent transmission to the receiver from the multiple transmit antennas of the transmitter. | 05-17-2012 |
20120121033 | METHOD AND DEVICE FOR DECODING OF SIGNALS TRANSMITTED OVER FADING CHANNELS WITH MULTIPLICATIVE NOISE - A method of generating a reliability indicator for decoding an encoded signal transmitted from a transmitter to a receiver via a wireless channel subject to fading. The method comprises: receiving symbols of the encoded signal; generating a reliability indicator for decoding at least some of the symbols selectively based on one or both of a statistical model representing additive white Gaussian noise (AWGN) in the encoded signal and a statistical model representing fading of the encoded signal; and selecting the statistical model based on signal characteristics of the wireless channel. | 05-17-2012 |
20120093207 | Manufacturing Process - The invention provides a method of manufacturing a user equipment comprising a wireless modem, a method of activating a user equipment as a wireless modem, and a corresponding server and user equipment. A processor is produced for executing wireless modem code to operate the processor as a wireless modem, the processor having a writeable, non-volatile memory for storing the wireless modem code but being produced with at least a substantive portion of said wireless modem code not installed on said memory or otherwise, thus rendering the processor inoperative as a wireless modem. The processor is assembled into a user equipment and supplied to an end-user still without the substantive portion of wireless modem code installed. In response to an indication from the end-user requesting activation of the user equipment as a wireless modem, at least said substantive portion of wireless modem code is then distributed to the end-user for installation on the memory the user equipment's processor. | 04-19-2012 |
20120076189 | ESTIMATION OF SIGNAL AND INTERFERENCE POWER - Wireless receiver and method of operating a wireless receiver in a wireless communication network for: receiving a signal, the received signal comprising data containing at least one symbol from a symbol alphabet, the symbol alphabet consisting of complex values that define a direction in the complex plane, the received signal further comprising interference; measuring the variance of a first component of the received signal that is perpendicular to the defined direction in the complex plane; estimating the interference power of the received signal using the measured variance of the first component of the received signal; estimating a total power of the received signal; estimating the power of the at least one symbol of the received signal by subtracting the estimated interference power from the estimated total power of the received signal; and based on the estimated interference power and the estimated power of the at least one symbol of the received signal, performing at least one of the steps of: processing the received signal, and generating control information related to the transmission of a further signal from the wireless receiver. | 03-29-2012 |
20120057650 | TRANSMITTING A SIGNAL FROM A POWER AMPLIFIER - A method for limiting peak-to-average power of a signal transmitted from a power amplifier. The method comprises: applying a pulse-shape filter to a first signal, thereby generating a second signal being a filtered version of the first signal; and outputting the second signal for transmission from a power amplifier. The method further comprises: applying each of a plurality of predictor filters to a respective instance of the first signal, each predictor filter approximating the application of the pulse-shape filter to the first signal based on a different respective set of filter coefficients, and each thereby generating a respective third signal. The method also further comprises determining an indicator of amplitude of each of the third signals, selecting the indicator corresponding to the largest of those amplitudes, generating a modifier based on the selected indicator, and using the modifier to limit the first signal prior to applying the pulse-shape filter. | 03-08-2012 |
20120033750 | TRANSPORT BLOCK SIZE - Disclosed herein is a method, device, network and computer program product for transmitting data in transport blocks from the device on an uplink channel of the network. Information indicative of a current condition on the uplink channel is determined. Based on the determined information, a transport block size for use in transmitting data on the uplink channel is adapted and data is transmitted from the device on the uplink channel in transport blocks having the adapted transport block size. | 02-09-2012 |
20120023352 | ACTIVE POWER MANAGEMENT - A method of controlling the clock frequency of a processor executing software in a plurality of active periods, the method comprising, for each period: supplying to a power management application at least one parameter defining an execution profile for the period having high frequency and low frequency operating intervals; the power management application determining, based on said profile, granted clock frequencies for the high and low frequency operating intervals; the processor supplying to the power management application at the commencement of a period an operating cycle requirement for the period; the power management application determining, for each period, based on the operating cycle requirement, the length of the low frequency interval; and controlling the clock frequency in each interval based on the granted clock frequencies determined by the power management application. | 01-26-2012 |
20120005471 | BOOTING AN INTEGRATED CIRCUIT - An integrated circuit is disclosed herein. In one embodiment, the integrated circuit includes: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties. | 01-05-2012 |
20120001270 | MEMORY CELLS - A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC. | 01-05-2012 |
20110305262 | MIMO RECEIVER HAVING IMPROVED SIR ESTIMATION AND CORRESPONDING METHOD - A method and corresponding receiver product, the method comprising: receiving a plurality of data streams over a wireless multiple-input-multiple-output data channel, whereby each data stream is received at all of a plurality of receive antennas from all of a plurality of transmit antennas with a respective weighting having been applied to each stream as transmitted from each different transmit antenna; receiving a common pilot signal over a common pilot channel; receiving an indication of the weightings; extracting the individual data streams from the plurality received at the receive antennas; and using the weightings and the common pilot signal together with information regarding the extracted data streams to calculate, for each of the streams, an estimate of signal power relative to interference from the one or more others of said data streams. | 12-15-2011 |
20110283136 | MEMORY ERRORS - The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information. | 11-17-2011 |
20110249770 | PASSIVE TRANSMITTER ARCHITECTURE WITH SWITCHABLE OUTPUTS FOR WIRELESS APPLICATIONS - A transmitter architecture having a single signal path or hardware to cover WCDMA/EDGE/GSM applications, and requires no SAW at the transmitter outputs. The transmitter architecture allows for a transmit convergence feature. A passive mixer with unique driver and furthermore using native devices available from the CMOS process for the mixer cores enables low voltage and low power design, low output noise and high linearity. A digital variable gain amplifier has the capability to cover wide output dynamic range operated from low supply voltage and interfaced digitally with the baseband circuit without DAC. A single transformer is used to combine the outputs from the WCDMA/EDGE and GSM drivers and subsequently convert the differential signal paths into a single-ended signal. RF switches are used to divert the output from the transformer to different bands and applications. | 10-13-2011 |
20110182197 | ESTIMATING SIGNAL CHARACTERISTICS - A method, program and apparatus for transmitting an RF signal over a wireless communication network. The method comprises: determining a respective weighting factor for each of a plurality of digital signals each corresponding to a respective channel, the weighting factors being for weighting the digital signals for combination to produce a composite signal intended for transmission as an RF signal via a power amplifier. The method further comprises: executing instructions on a processor to dynamically calculate, in the processor, a metric related to the non-linearity of the power amplifier's transfer characteristics for the composite signal using the determined weighting factors; supplying to the power amplifier a signal for transmission as an RF signal; amplifying the signal for transmission at the power amplifier to transmit an RF signal over the wireless communication network via at least one antenna; and controlling the transmission based on the metric related to the amplifier non-linearity. | 07-28-2011 |
20110164663 | A METHOD AND CIRCUIT FOR FRACTIONAL RATE PULSE SHAPING - A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasing resulting from the upconversion process, and then downsampling the intermediate signal by a second integer factor to provide a final signal having a second sample rate. The first factor and the second factor are selected to obtain a desired output sample rate that is a fraction of the sample rate of the input signal. | 07-07-2011 |
20110163815 | METHOD AND SYSTEM FOR CALIBRATING A FREQUENCY SYNTHESIZER - A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain. | 07-07-2011 |
20110138347 | SYSTEM AND METHOD FOR DESIGNING INTEGRATED CIRCUITS THAT EMPLOY ADAPTIVE VOLTAGE SCALING OPTIMIZATION - A design process optimization system and method for designing a circuit, which may be an integrated circuit (IC) employing adaptive voltage and scaling optimization (AVSO). In one embodiment, the system includes: (1) a process-voltage-temperature (PVT) libraries database configured to contain PVT libraries of PVT characterizations of devices of cells from which the circuit is to be constructed and (2) a PVT library selector coupled to the PVT libraries database and configured to receive a selection indicating a supplemental objective and respond to the selection by selecting one of the PVT libraries from the PVT libraries database, a timing signoff tool later employing at most two corners from the one of the PVT libraries to perform a timing signoff with respect to the circuit. | 06-09-2011 |
20110105171 | REPORTING CHANNEL QUALITY INFORMATION - The present invention relates to a method of transmitting channel quality data for channels in a wireless communication system, and to a corresponding receiver and transmitter. The method comprises determining a plurality of channel quality indicators for a corresponding plurality of frequency intervals, and transmitting information about channel quality indicators in the form of differentially encoded slope data. | 05-05-2011 |
20110078416 | APPARATUS AND METHOD FOR CONTROL PROCESSING IN DUAL PATH PROCESSOR - A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions. The processing channel comprises a plurality of functional units and operable to perform control processing operations. The decode unit is operable to receive and decode instruction packets of a bit length of 64 bits and to detect if the instruction packet defines three control instructions each having a length of 21 bits. The decode unit detects that the instruction packet comprises the three control instructions. The control instructions are supplied to the processing channel for execution in the order in which they appear in the instruction packet. The detection uses an identification bit in the instruction packet. | 03-31-2011 |
20110075773 | METHOD AND SYSTEM FOR PROCESSING A SIGNAL - Method and receiver for processing a signal in a wireless communication system in which the signal comprises a sequence of chips. The signal is receive data at least one rake finger and sampled. There is a time spacing t | 03-31-2011 |
20110058597 | EQUALISATION PROCESSING - A method and apparatus for processing a signal in a wireless communication system. The method comprises: receiving a signal at a receiver over a wireless channel; sampling the signal to produce a plurality of signal samples; and supplying the samples to an equaliser implemented in software running on a processor of the receiver, the equaliser being configured to process the samples using at least one equaliser time period having a nominal length. The method further comprises dynamically determining one or more characteristics of the channel; in dependence on the determined channel characteristics, dynamically selecting between a first operational state of the equaliser in which the nominal length is used and a second operational state of the equaliser in which an alternative length is used in place of the nominal length; and processing the samples in the equaliser using the determined equaliser time period length. | 03-10-2011 |
20110045783 | SYSTEM AND METHOD OF WIRELESS COMMUNICATION - A method, program and system for transmitting from a transmitter to a receiver over a wireless multipie-input-multiple-output channel. In one aspect, the method may comprise encoding precoding information fed back from the receiver to the transmitter according to a differential encoding scheme, and resetting the differential encoding scheme upon detecting a condition. In another aspect, the method may comprises encoding precoding matrices fed back from the receiver to the transmitter relative to a most-probable subset of precoding matrices. In another aspect, the method may comprise transmitting an indication of and/or the size of a preferred subset of precoding matrices for use in the encoding. | 02-24-2011 |
20110032837 | SYNCHRONOUS CDMA COMMUNICATION SYSTEM - In one aspect, there is provided a method of processing a signal received using a wireless communication channel by a receiver in a wireless cellular network. In one embodiment, the method comprises receiving signal samples of a signal to be processed from a serving cell, identifying a second of dominant interfering cells generating an interfering signal, using a number of cells in the set to select an interference scenario, and using the selected interference scenario and at least one parameter related to the serving cell and the interfering cells to select a processing function for processing the signal. | 02-10-2011 |
20110019780 | PROCESSING DIGITAL SAMPLES IN A WIRELESS RECEIVER - A system and method for processing digital samples from a signal received via a wireless transmission channel in a wireless communications system. The method comprises: comparing a target signal quality value with an estimated received signal quality value; detecting if the estimated received signal quality value exceeds the target signal quality value for a period; and selecting one of a plurality of processing routines of differing sensitivities for processing the digital samples. | 01-27-2011 |
20110019754 | POWER CONTROL IN A WIRELESS COMMUNICATION SYSTEM - A method of power control in a wireless communication system wherein blocks are transmitted from a transmitter to a receiver on multiple wireless transport channels. The method comprises comparing a target signal quality value with a received signal quality value and providing the results of the comparing step to the transmitter to adjust transmit power, and a mechanism for controlling the target signal quality for transport channels that have been inactive for a predefined period. A corresponding receiver is also provided. | 01-27-2011 |
20110007644 | FREQUENCY OFFSET ESTIMATION IN A CDMA SYSTEM - The present invention provides a method of estimating a frequency offset. The method comprises receiving a wireless signal timed according to a first frequency; generating a local signal timed according to a second frequency; and performing a plurality of synchronization searches, each search comprising obtaining a set of correlation results indicative of a correlation between the wireless signal and the local signal at different timing offsets of the wireless signal relative to the local signal. The method the no comprises finding a series of results, with a result from each of a plurality of the synchronization searches, for which the difference in; timing offset between results from adjacent searches in the series is within a maximum specified value. A frequency off set between the first and second frequencies can be determined from the series. | 01-13-2011 |
20100322191 | PHYSICAL CHANNEL ESTABLISHMENT - There is disclosed a method of controlling physical channel establishment in a wireless communication system, which method comprises: a.) determining if decoding of a system frame number is required as part of an initialization of a physical channel establishment procedure; b.) if decoding of the system frame number is not required, initializing a decoding of a system frame number for the channel to be established; and c.) if the decoding of the system frame number fails, terminating the channel establishment procedure. | 12-23-2010 |
20100322094 | CARRIER DETECTION - There is disclosed a method of determining one or more candidate frequencies for a carrier signal in a received signal, which method comprises: generating a narrowband spectrum of the received signal; detecting one or more peaks in the narrowband spectrum; generating a candidate frequency list, each frequency at which a peak occurs being included in the candidate frequency list. The method further comprises: removing the detected one or more peaks from the narrowband spectrum to generate a modified narrowband spectrum; detecting one or more further peaks in the modified narrowband spectrum; and modifying the candidate frequency list in dependence on the one or more further peaks. | 12-23-2010 |
20100309850 | POWER CONTROL IN A WIRELESS COMMUNICATION SYSTEM - A method of power control in a wireless communications system wherein blocks are transmitted from a transmitter to a receiver via a wireless transmission channel. The method comprises comparing a target signal quality value with a received signal quality value and providing the results of the comparing step to the transmitter to adjust transmit power based on the comparing step. The target signal quality value is set by the following steps: determining an initial target value; determining if received blocks have been successfully decoded; identifying the received blocks as pass or fail blocks; when pass blocks are received, comparing the target signal quality value with the received signal quality value and decreasing the target value only if the target value is greater than the received signal quality value less a margin. | 12-09-2010 |
20100304779 | POWER CONTROL IN A WIRELESS COMMUNICATION SYSTEM - A method of power control in a wireless communication system, wherein blocks are transmitted from a transmitter to a receiver via a wireless transport channel. The method comprises comparing a target signal quality value with a received signal quality value and providing the results of the comparing step to the transmitter to adjust transmit power based on the comparing step. The target signal quality value is set by the following steps: determining an initial target value; detecting if a data block has been received; detecting if received blocks have been successfully decoded; and decreasing the target value when pass blocks are received and increasing the target value when failed blocks are received subject to monitoring a period of inactivity on the transport channel in which no blocks are received. | 12-02-2010 |
20100304769 | POWER CONTROL IN A WIRELESS COMMUNICATION SYSTEM - An inter-radio-access-technology device comprising: an interface for communicating over a wireless cellular network, and a processor arranged to execute code for performing operations handling communications via the interface according to a plurality of different radio access technologies. The processor is operable to execute code using any selected one of a plurality of different instruction sets, each set being configured for performing operations according to a respective one of the radio access technologies. The device is operable to dynamically switch between the radio access technologies, by selecting corresponding code for execution by the processor and selecting the corresponding instruction set for use in execution of the selected code. | 12-02-2010 |
20100296553 | PROCESSING DIGITAL SAMPLES IN A WIRELESS RECEIVER - A method of processing digital samples of a signal received at a receiver of a wireless communication system includes monitoring channel conditions and generating a channel indicator including at least one channel parameter by performing at least one of: estimating a channel mobility parameter and comparing it with a threshold; estimating a channel parameter of the energy of the channel outside a predefined temporal window and comparing it with a threshold; estimating a channel temporal duration parameter and establishing if it meets predetermined criteria; estimating a channel-zero location parameter and establishing if it meets predetermined criteria; estimating a received-signal signal-to-disturbance power ratio and comparing it to a threshold; estimating an estimated-channel-response signal-to-disturbance power ratio; estimating the degree of non-stationarity of the disturbance at the receiver input; and selecting one of a plurality of processing routines for processing the digital samples based on said channel indicator. Related receivers are also described. | 11-25-2010 |
20100290547 | GENERATING CHANNEL ESTIMATES IN A RADIO RECEIVER - A method and system for generating channel estimates for processing signals received through first and second transmission channels in a wireless communications network, each channel corresponding to a separate transmit antenna, and each signal comprising a plurality of samples derived from symbols transmitted in the signal by: generating first variable z1 (k) and second variable z2 (k); and providing a set of filter coefficients (I) and generating first and second channel estimates using first and second variables and a set of filter coefficients. | 11-18-2010 |
20100284500 | ESTIMATING SIGNAL TO INTERFERENCE RATIO IN A WIRELESS COMMUNICATIONS RECEIVER - A method and corresponding system for generating an estimate of at least one of a signal power, a noise power and a signal to interference ratio for signal samples received via first and second wireless channels, the signal samples corresponding to pilot symbols transmitted in respective different structures via the first and second wireless channels. The method comprises: calculating first and second variables, each variable being a sequence of values computed from the received signal samples and the pilot symbols for each respective first and second wireless channel; generating first and second channel estimates from the first and second variables; combining the first and second channel estimates to generate a combined channel estimate; and generating at least one of the signal power, noise power and SIR using the combined channel estimate. | 11-11-2010 |
20100267418 | SMART CARD MODULE SUPPORTING AUTHENTICATION AND SOFTWARE-DEFINED RADIO FUNCTION FOR A WIRELESS DEVICE - The disclosure provides a module for use in a wireless electronic device and being removable therefrom. In one embodiment, the module includes an antenna connector for connecting the antenna of the wireless terminal to the module, and transferring radio frequency signals over a wireless interface. The module also includes a first storage means storing user authentication information for use in authenticating a user of the wireless terminal to a wireless cellular network, and a second storage means storing communications code for processing information to be transferred over the wireless interface. The module further includes a processor arranged to execute the communications code in order to process information for communicating between the wireless terminal and the cellular network via the antenna connector. | 10-21-2010 |
20100254469 | REPORTING CHANNEL QUALITY INFORMATION - A method and corresponding receiver for transmitting channel quality data for a channel in a wireless communication system are provided. The method comprises determining channel quality metrics for frequency intervals within the channel, selecting groups of frequency intervals based on the determined metrics, and transmitting one or more channel quality indicators for the groups. The invention also provides a method of transmitting over a channel based on such channel quality indicators feedback from a receiver, and a corresponding transmitter. | 10-07-2010 |
20100254445 | PROCESSING TRANSMISSIONS IN A WIRELESS COMMUNICATION SYSTEM - Disclosed herein are methods of processing transmissions in a wireless communication system to detect whether a transmission unit contains transmitted data, systems for processing transmissions in a digital communications system to detect the same, receivers for processing transmissions in a wireless communications system and computer readable media implementing a method for processing the same. In one embodiment, a method of processing transmissions in a wireless communication system to detect whether a transmission unit contains transmitted data includes: generating an averaged function of bit reliability indicators from a plurality of received samples and applying a test to compare an average of ln cos h(ยท) (natural logarithm of the hyperbolic cosine) values for the reliability indicators, with a factor proportional to an average signal-to-disturbance ratio of the plurality of samples to determine if the transmission unit contains transmitted data. | 10-07-2010 |
20100225351 | Resolving Mestastability - A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of the latch. Each of the differential amplifiers includes a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier. If the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, the differential amplifiers drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and drive down the logical output of the latch if the input signal transitions from the second to the first logical level. | 09-09-2010 |
20100202421 | TRANSMITTING SIGNALS - A method, program and apparatus for transmitting a signal in a time slot of a channel comprising a plurality of time slots. Using a transmitter having a processor and a power amplifier, the method comprises: retrieving a reference ramp pattern from a memory; determining an output power level for the slot from a plurality of possible output power levels, each requiring a respective corresponding ramp pattern; executing software on the processor to apply a scaling function to the reference ramp pattern in dependence on the determined output power level, thus generating a scaled ramp pattern corresponding to the pattern required for that determined level; supplying the scaled ramp pattern to a control input of the power amplifier, to control the gain of the power amplifier during the time slot; and using the power amplifier, controlled according to the scaled ramp pattern, to transmit the signal in the time slot. | 08-12-2010 |
20100185789 | DMA Engine - Disclosed herein is a method of accessing a slave device from a circuit including a central processing unit, a data transfer engine, and an interface to the slave device. In one embodiment, the method includes: executing code on the central processing unit to set up the data transfer engine to access the slave device; and based on the set-up, operating the data transfer engine to supply a read request word to a transmit buffer of the interface for transmission to the slave device, and, after return of a corresponding response word to a first-in-first-out receive buffer of the interface, to disable the first-in-first-out receive buffer from receiving any further data such that the last word therein is assured to be the response word. The method further includes using an underflow mechanism of the first-in-first-out receive buffer to determine the last word therein and hence determine the response word. | 07-22-2010 |
20100095106 | BOOT ALGORITHM - A method, chip and computer program product for booting from a secondary boot source. In one embodiment, the method includes: (1) retrieving primary boot code from an on-chip primary boot source on the same chip as a processor, the primary boot code comprising at least a boot discovery algorithm for determining the location of an external secondary boot source external to said chip, (2) executing the primary boot code on the processor, including the boot discovery algorithm, thus operating the processor to check each of a plurality of locations to determine the location of the external secondary boot source, (3) retrieving the secondary boot code from the determined location and (4) continuing the booting of the processor by executing the secondary boot code on the processor. | 04-15-2010 |
20100088688 | INSTRUCTION CACHE - Disclosed herein is a method of optimising an executable program to improve instruction cache hit rate when executed on a processor. A method of predicting instruction cache behaviour of an executable program is also disclosed. According to further aspects of the present invention, there is provided a software development tool product comprising code which when executed on a computer will perform the method of optimising an executable program. A linker product and a computer program are also disclosed. | 04-08-2010 |
20090172459 | MEMORY INTERFACE - A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium. | 07-02-2009 |
20090172383 | BOOTING AN INTEGRATED CIRCUIT - An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties. | 07-02-2009 |
20090172380 | BOOTING AN INTEGRATED CIRCUIT - An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties. | 07-02-2009 |
20090153194 | CLOCK CIRCUITRY - A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data between the first and second circuit portions. The clock circuitry generates a first control signal at a predetermined time in each cycle of the first clock signal prior to a predetermined edge, and a second control signal at a predetermined time in each cycle of the second clock signal prior to a predetermined edge. A change in the relative frequency is conditional on a coincidence of the first and second control signals. The synchronisation generates the pulses such that there is at least one cycle of the first clock signal between those pulses, and such that there is only one of those pulses per cycle of the second clock signal. | 06-18-2009 |
20080310564 | Processing data in a digital communications system - A method of processing a signal in a wireless digital communications system, wherein a source of disturbance affects differently at least first and second portions of a received signal carrying user data and/or control data, the method comprising: identifying the second portion of the received signal, most affected by the source of disturbance; generating a first estimate of the disturbance (P | 12-18-2008 |