TEXAS INSTRUMENTS INCORPORATED Patent applications |
Patent application number | Title | Published |
20160141363 | METHOD OF IMPROVING LATERAL BJT CHARACTERISTICS IN BCD TECHNOLOGY - In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BV | 05-19-2016 |
20160139187 | CURRENT SENSE CIRCUIT THAT OPERATES OVER A WIDE RANGE OF CURRENTS - The magnitude of an output current that flows into a load is determined by placing a sense bipolar transistor and a sense resistor in series with the load, utilizing the non-linear current characteristics of the base-emitter junction of the sense bipolar transistor to compress and sense an emitter current logarithmically, and then performing an inverse log function to determine the emitter current, which is substantially identical to the output current that flows into the load. | 05-19-2016 |
20160133689 | RELIABILITY IMPROVEMENT OF POLYMER-BASED CAPACITORS BY MOISTURE BARRIER - It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process. | 05-12-2016 |
20160119714 | AUDIO POWER LIMITING BASED ON THERMAL MODELING - Systems and methods for audio power limiting based on thermal modeling are described. In some embodiments, a method includes monitoring a first temperature of a power die within an audio system; monitoring a second temperature of a digital die within the audio system; and using the first and second temperatures to limit an amplitude of an audio signal provided to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) of an amplifier within the audio system to keep an operating temperature of the MOSFET under a thermal protection threshold without stopping the audio signal from being output by the audio system. | 04-28-2016 |
20160119575 | IMAGE DATA PROCESSING FOR DIGITAL OVERLAP WIDE DYNAMIC RANGE SENSORS - Methods and integrated circuits to process image data from single or multiple digital overlap (DOL) wide dynamic range (WDR) sensors, in which first received pixel data associated with a first exposure of a sensor image is stored in a DDR memory circuit, second received pixel data associated with a second exposure of the image is stored in the first buffer, third received pixel data associated with a third exposure of the image is stored in a second buffer, and fourth received pixel data associated with a fourth exposure of the image is provided to a merge circuit, and merged pixel data is stored in a dynamically partitioned line buffer for processing by an image pipeline circuit to facilitate interfacing multiple DOL WDR sensors in an interleaved fashion. | 04-28-2016 |
20160119094 | PSEUDORANDOM SEQUENCE GENERATION FOR OFDM CELLULAR SYSTEMS - In one embodiment, a transmitter includes a binary sequence generator unit configured to provide a sequence of reference signal bits, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to the transmitter and one or more time indices of the sequence. The transmitter also include a mapping unit that transforms the sequence of reference signal bits into a complex reference signal, and a transmit unit configured to transmit the complex reference signal. In another embodiment, a receiver includes a receive unit configured to receive a complex reference signal and a reference signal decoder unit configured to detect a sequence of reference signal bits from the complex reference signal, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to a transmitter and one or more time indices of the sequence. | 04-28-2016 |
20160118977 | DC-DC CONVERTER WITH TEMPERATURE, PROCESS AND VOLTAGE COMPENSATED DEAD TIME DELAY - Temperature, process and supply compensated delay circuits, DC to DC converters and integrated circuits are presented in which switch driver dead time delays are provided using a plurality of cascaded CMOS inverter circuits with a first inverter coupled through a diode-connected MOS transistor to a regulated voltage or circuit ground and a MOS capacitor is provided between the first inverter output and the regulated voltage or circuit ground to provide a controlled delay time. A second cascaded CMOS inverter is powered by a compensated voltage which decreases with temperature to operate as a comparator, and certain embodiments include one or more intermediate CMOS inverters to form a level shifting circuit between the second inverter and the final output inverter, with the level shift inverters powered by successively higher compensated voltages that decrease with increasing temperature. | 04-28-2016 |
20160117557 | APPARATUS FOR DETECTING FAULTS IN VIDEO FRAMES OF VIDEO SEQUENCE - A fault detection circuit for detecting faults in a video sequence includes a multiple input signature register (MISR) with a linear feedback shift register (LFSR) that receives pixel data for pixels in a frame region for video frames of a video sequence and receives a read signal to read the pixel data and shift the MISR; a multiple signature storage buffer (MSSB) that stores frame signatures; and a signature comparator that compares current and reference frame signatures to determine if a fault condition exists in the video sequence. The MISR holds a frame signature for the frame region of the video frame while receiving a frame end signal. The MSSB stores a current frame signature held by the MISR after receiving the frame end signal. The MSSB also stores a reference frame signature. A display processing circuit includes the fault detection circuit. An integrated circuit includes the display processing circuit. | 04-28-2016 |
20160117274 | USB PORT CONTROLLER WITH AUTOMATIC TRANSMIT RETRIES AND RECEIVE ACKNOWLEDGEMENTS - Described examples include USB controllers and methods of interfacing a host processor with one or more USB ports with the host processor implementing an upper protocol layer and a policy engine for negotiating USB power delivery parameters, in which the USB controller includes a logic circuit implementing a lower protocol layer to provide automatic outgoing data transmission retries independent of the upper protocol layer of the host processor. The controller logic circuit further implements automatic incoming data packet validity verification and acknowledgment independent of the upper protocol layer of the host processor. | 04-28-2016 |
20160117261 | RESPONSE VALIDATION MECHANISM FOR TRIGGERING NON-INVASIVE RE-TEST ACCESS OF INTEGRATED CIRCUITS - In an embodiment of the invention, response validation offers increased integrated circuit security by using a unique password or re-test key for every integrated circuit manufactured. Non-invasive re-test of an IC can be performed using an encryption input. | 04-28-2016 |
20160116573 | METHOD AND APPARATUS FOR GENERATING ALIGNMENT MATRIX FOR CAMERA-RADAR SYSTEM - A method of generating an alignment matrix for a camera-radar system includes: receiving radar data originated by a radar subsystem and representative of an area of interest within a field of view for the radar subsystem; receiving image data originated by a camera subsystem and representative of the area of interest within a field of view for the camera subsystem; processing the radar data to detect features within the area of interest and to determine a reflected radar point with three dimensions relating to a camera-radar system; processing the image data to detect features within the area of interest and to determine a centroid with two dimensions relating to the camera-radar system; and computing an alignment matrix for radar and image data from the camera-radar system based on a functional relationship between the three dimensions for the reflected radar point and the two dimensions for the centroid. | 04-28-2016 |
20160113085 | Combined Hybrid and Local Dimming Control of Light Emitting Diodes - An LED backlight controller combines global/hybrid and local brightness/dimming control for an LED backlight illuminator with local regions illuminated by associated LED strings. Global/hybrid brightness/dimming control performs hybrid digital modulation control for a predefined lower range of brightness levels, with string current maintained at a substantially constant level associated with a predefined maximum brightness for the lower range (controlling brightness by adjusting digital modulation, such as PWM duty cycle, up to a maximum), and performs hybrid string current control for a predefined higher range of brightness levels (controlling brightness by adjusting string current). Local dimming control is performed by introducing a local digital modulation signal into a hybrid digital modulation control path for the associated string, so that digital modulation for the associated string is a combination of local digital modulation and global/hybrid digital modulation. | 04-21-2016 |
20160112055 | PHASE FREQUENCY DETECTOR (PFD) CIRCUIT WITH IMPROVED LOCK TIME - Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit. | 04-21-2016 |
20160112006 | DIGITAL CONTROLLED OSCILLATOR AND SWITCHABLE VARACTOR FOR HIGH FREQUENCY LOW NOISE OPERATION - Low noise switchable varactors and digital controlled oscillator (DCO) circuitry are presented for creating alternating signals at controlled frequencies, including a first transistor for selectively coupling two capacitors between varactor output nodes when a control signal is in a first state, second and third transistors for selectively coupling first and second internal nodes between the respective capacitors and the first transistor with a third internal node when the control signal is in the first state, and an inverter disconnected from the first and second internal nodes to mitigate phase noise and operable to control the voltage of the third internal node according to the control signal. | 04-21-2016 |
20160110894 | METHOD AND APPARATUS TO RENDER LINES ON A DISPLAY SCREEN - Disclosed examples include drawing apparatus and methods of rendering lines on a display screen, in which a first angle is determined that corresponds to a hand drawn line created by a user on the display screen, and a new line is rendered on the display screen to represent the hand drawn line created by the user. The new line is selectively rendered parallel or perpendicular to an existing line on the display screen at least partially according to the first angle using the processor. | 04-21-2016 |
20160109327 | METHOD AND OTDR APPARATUS FOR OPTICAL CABLE DEFECT LOCATION WITH REDUCED MEMORY REQUIREMENT - Optical time domain reflectometer (OTDR) systems, methods and integrated circuits are presented for locating defects in an optical cable or other optical cable, in which a first optical signal is transmitted to the cable and reflections are sampled over a first time range at a first sample rate to identify one or more suspected defect locations, and a second optical signal is transmitted and corresponding reflections are sampled over a second smaller time range at a higher second sample rate to identify at least one defect location of the optical cable for relaxed memory requirements in the OTDR system. | 04-21-2016 |
20160099643 | Configurable Power Supply Circuit with External Resistance Detection - A power supply circuit, suitable for use in an integrated circuit, the circuit configured to detect whether an output voltage has been specified using an external resistance network. The power supply circuit is configured to determine the appropriate output voltage to be generated based on a voltage measured at a single input pin of the power supply circuit, where the single input pin provides a feedback voltage used in the control loop of the power supply circuit. Based on the feedback voltage at the input pin, the power supply circuit is configured to detect the presence of a resistance network external to the single input pin. If an external resistance network is detected, the power supply is configured to generate the output voltage specified at the input pin. If no external resistance network is detected, the power supply is configured to generate a default output voltage. | 04-07-2016 |
20160097638 | METHOD AND APPARATUS FOR TILT SENSING USING ECCENTRIC MOTOR - Systems, apparatus and methods are presented for sensing or estimating a tilt angle, in which a current flowing in an eccentric mass motor is sensed, and a detector circuit assesses the amplitude of a synchronous component of the motor current and provides an output signal or value indicating a tilt angle relative to a gravitational axis at least partially according to the amplitude of the synchronous component of the motor current. | 04-07-2016 |
20160094205 | DIGITAL OPEN LOOP DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction (DCC) circuit includes a master delay line that receives an input clock and determines a period of the input clock. A calibration module is coupled to the master delay line and generates a calibration code based on a desired duty cycle and the period of the input clock. A slave delay line generates a delayed input clock based on the input clock and the calibration code. A clock generation module generates an output clock, having the desired duty cycle, in response to the input clock and the delayed input clock. | 03-31-2016 |
20160094204 | FLIP-FLOPS WITH LOW CLOCK POWER - The disclosure provides a flip-flop that utilizes low power as a result of reduced transistor count. The flip-flop includes a tri-state inverter that receives a flip-flop input and a clock input. A master latch is coupled to an output of the tri-state inverter and provides a control signal to the tri-state inverter. The control signal activates the tri-state inverter. A slave latch receives an output of the master latch and the control signal. An output inverter is coupled to an output of the slave latch and generates a flip-flop output. | 03-31-2016 |
20160093552 | INTEGRATION OF BACKSIDE HEAT SPREADER FOR THERMAL MANAGEMENT - A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters. | 03-31-2016 |
20160093551 | INTEGRATION OF HEAT SPREADER FOR BEOL THERMAL MANAGEMENT - A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters. | 03-31-2016 |
20160092624 | FILLER INSERTION IN CIRCUIT LAYOUT - A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requirement. Then, a filler insertion pattern based on a required ratio is identified such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes. | 03-31-2016 |
20160091342 | Multi-level Rotational Resolvers Using Inductive Sensors - A rotational resolver system and method includes a rotational shaft to which at least one eccentric conductive coarse resolution disc is fixed and to which at least one conductive fine resolution disc is also fixed. The fine resolution disc defines a plurality of generally semicircular protruding edge segments. At least one conductive coarse-disc sensing coil is disposed adjacent an edge of the coarse resolution disc, and at least one conductive fine-disc sensing coil is disposed adjacent the edge of the fine resolution disc. These coils may be oriented for axial sensing of the respective disc | 03-31-2016 |
20160088214 | COMPENSATING ANGULAR MISALIGNMENT IN OPTICAL IMAGE STABILIZATION (OIS) SYSTEMS - Systems and methods for compensating angular misalignment in Optical Image Stabilization (OIS) systems are described. In some embodiments, a method may include measuring an angle representing a misalignment between an actuator and an electronic component within a camera; and compensating for the misalignment using a rotation matrix, wherein the rotation matrix is calculated based upon the angle. In other embodiments, a camera may include an image sensor coupled to a Printed Circuit Board (PCB); an OIS actuator coupled to the PCB and optically coupled to the image sensor, where the OIS actuator is physically misaligned with respect to the image sensor; and a controller coupled to the PCB, the controller configured to: measure an angle representing the misalignment; and compensate for the misalignment using a rotation matrix at the time of an image capture, where the rotation matrix is calculated based upon the angle. | 03-24-2016 |
20160087518 | CIRCUIT FOR DRIVER CONTROL OF SWITCHING CIRCUIT - Several circuits and methods for driver control of a switching circuit are disclosed. In an embodiment, a circuit for driver control of a switching circuit includes a driver circuit and a control circuit. The driver circuit is capable of being coupled to the switching circuit. The switching circuit includes a first switch and a second switch. The driver circuit is configured to control a conductive state of the switching circuit by facilitating an alternate state change of the first switch and the second switch. The control circuit is coupled to the driver circuit and is configured to detect a noise signal during a state change of the first switch. The control circuit is further configured to control the driver circuit to thereby slow down the state change of the first switch. | 03-24-2016 |
20160079959 | PROGRAMMABLE STEP ATTENUATOR WITH CROSS CONNECTION - Disclosed examples include a programmable attenuator circuit providing selective cross coupling of impedance components between circuit input nodes and output nodes according to control signals to set or adjust an attenuation value of the attenuator circuit. The attenuator circuit includes a plurality of attenuator impedance components, and a switching circuit to selectively connect at least a first attenuator impedance component between the first input node and the second output node, to selectively connect at least a second attenuator impedance component between the second input node and the first output node, to selectively connect a third attenuator impedance component between the first input node and the first output node, and to selectively connect a fourth attenuator impedance component between the second input node and the second output node. | 03-17-2016 |
20160072735 | LOW VOLTAGE FEEDFORWARD CURRENT ASSIST ETHERNET LINE DRIVER - Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels. | 03-10-2016 |
20160072518 | PIPELINE ADC AND REFERENCE LOAD BALANCING CIRCUIT AND METHOD TO BALANCE REFERENCE CIRCUIT LOAD - Disclosed examples include pipeline ADC, balancing circuits and methods to balance a load of a reference circuit to reduce non-linearity and settling effects for a reference voltage signal, in which balancing capacitors are connected to a voltage source in a pipeline stage ADC sample time period to precharge the balancing capacitors using a voltage above the reference voltage, and a selected set of the precharged balancing capacitors is connected to provide charge to the output of the reference circuit during the second time period. | 03-10-2016 |
20160071725 | METHOD OF FORMING A THIN FILM THAT ELIMINATES AIR BUBBLES - A method, which forms an air-bubble-free thin film with a high-viscosity fluid resin, initially dispenses the fluid resin on an outer region of a semiconductor wafer while the semiconductor wafer is spinning, and then dispenses the fluid resin onto the center of the semiconductor wafer after the semiconductor wafer has stopped spinning. | 03-10-2016 |
20160071577 | STATIC RANDOM ACCESS MEMORY WITH REDUCED WRITE POWER - A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes. | 03-10-2016 |
20160070017 | MATERIAL-DISCERNING SENSING BY MEASUREMENT OF DIFFERENT POINTS OF IMPEDANCE - A material-discerning proximity sensor is arranged to include an antenna that is arranged to radiate a radio-frequency signal. A capacitive sensor is arranged to detect a change in capacitance of the capacitive sensor and to receive the radio-frequency signal. An electrical quantity sensor is arranged to detect a change of the received radio-frequency signal and a change of a radio-frequency signal at an output of the at least one band pass filter. | 03-10-2016 |
20160069662 | INDUCTIVE POSITION DETECTION - A position detecting system detects and responds to the movement of a target through a sensing domain area of a plane. The movement causes the amount of the target that lies within a first sensing domain area of a first sensor to change. A second sensor detects a height from the plane to a sensor for enhancing accuracy of measurements from the first sensor. | 03-10-2016 |
20160066263 | Systems and Methods of Power Efficient Wi-Fi - In example embodiments disclosed herein, a primary wireless device infrequently sends a ping to a secondary device to determine if there are any communications from an access point intended for the primary wireless device. The secondary device, ideally connected to wall power, is wirelessly connected to the access point, acting as a connected proxy so that the primary wireless device, typically battery powered, does not always have to be connected. In a situation in which an incoming communication is intended for the primary device, the secondary device receives the notification and buffers whatever is sent from the access point intended for the primary wireless device and acknowledges the receipt. Then, when the primary wireless device pings the secondary device, the secondary device sends the buffered communication to the primary wireless device. As far as the access point is concerned, it thinks it is communicating directly with primary wireless device. | 03-03-2016 |
20160065188 | LOW LEAKAGE SHADOW LATCH-BASED MULTI-THRESHOLD CMOS SEQUENTIAL CIRCUIT - Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit. | 03-03-2016 |
20160043586 | METHODS, ELECTRONIC DEVICES, AND CHARGER APPARATUS FOR QUICK USB CHARGING - USB charger apparatus and chargeable electronic devices are presented in which the device and charger use USB cable data lines to establish a bidirectional communications connection, and the charger provides charger capability information to a master controller of the electronic device via the communications connection. The device controller preferentially selects a fastest charging match between the charger capability information and device charging capability information, and sends configuration information through the communications connection to set the power supply level of the charger. The charger communicates power supply status information to the electronic device, and the device can reconfigure the charger power supply level accordingly. | 02-11-2016 |
20160043539 | SHORT-CIRCUIT PROTECTION FOR VOLTAGE REGULATORS - Circuits and methods for providing short-circuit protection in a voltage regulator are disclosed. A voltage regulator includes a pass switch, a voltage error amplifier, a driver circuit, and a short-circuit protection circuit. The pass element is coupled to a power supply and a load, and generates an output voltage in response to a drive signal. The voltage error amplifier generates an error voltage based on a difference of a reference voltage and the output voltage and the driver circuit generates the drive signal in response to the error voltage. The short-circuit protection circuit senses the drive signal and provides a high-resistance path to the driver circuit in a short-circuit event. In a short-circuit event, the high-resistance path clamps current in the driver circuit thereby clamping a voltage difference between the first and third terminals and thereby limiting a load current in the short-circuit event. | 02-11-2016 |
20160034396 | Programmable Address-Based Write-Through Cache Control - This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit. | 02-04-2016 |
20160027365 | POWER AND BRIGHTNESS MANAGEMENT OF SOLID-STATE DISPLAYS - System, method, and device for maximizing brightness of solid-state illuminators while minimizing power usage based on individual scene contents. An embodiment varies power to each of the solid-state illuminators (red, green, & blue) based on the scene content that is being displayed optimizing the non-linear brightness response of solid-state illuminators. | 01-28-2016 |
20160019945 | POWER GATE FOR LATCH-UP PREVENTION - In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate. | 01-21-2016 |
20160006403 | MULTISTAGE AMPLIFIER CIRCUIT WITH IMPROVED SETTLING TIME - Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions. | 01-07-2016 |
20160006336 | DC TO DC CONVERTER AND PWM CONTROLLER WITH ADAPTIVE COMPENSATION CIRCUIT - DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude. | 01-07-2016 |
20150380637 | PIEZOELETRIC WET ETCH PROCESS WITH REDUCED RESIST LIFTING AND CONTROLLED UNDERCUT - A microelectronic device containing a piezoelectric thin film element is formed by oxidizing a top surface of a piezoelectric layer with an oxygen plasma, and subsequently forming an etch mask containing photoresist on the oxidized top surface. The etch mask is conditioned with an oven bake followed by a UV bake. The piezoelectric layer is etched using a three step process: a first step includes a wet etch of an aqueous solution of about 5% NH | 12-31-2015 |
20150380635 | METHODS TO IMPROVE THE CRYSTALLINITY OF PbZrTiO3 AND Pt FILMS FOR MEMS APPLICATIONS - A microelectronic device containing a piezoelectric component is formed sputtering an adhesion layer of titanium on a substrate by an ionized metal plasma (IMP) process. The adhesion layer is oxidized so that at least a portion of the titanium is converted to a layer of substantially stoichiometric titanium dioxide (TiO | 12-31-2015 |
20150371985 | POSITIVE STRIKE SCR, NEGATIVE STRIKE SCR, AND A BIDIRECTIONAL ESD STRUCTURE THAT UTILIZES THE POSITIVE STRIKE SCR AND THE NEGATIVE STRIKE SCR - A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection. | 12-24-2015 |
20150371638 | Context Aware Sound Signature Detection - A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. Sparse sound parameter information is extracted from the analog signal. The extracted sound parameter information is sampled in a periodic manner and a context value is updated to indicate a current environmental condition. The sparse sound parameter information is compared to both the context value and a signature sound parameter database stored locally with the sound recognition sensor to identify sounds or speech contained in the analog signal, such that identification of sound or speech is adaptive to the current environmental condition. | 12-24-2015 |
20150370031 | LENS DRIVER CIRCUIT WITH RINGING COMPENSATION - A lens driver circuit determines the resonant frequency at a number of positions that a lens can move to so that the lens can move from an old position to a new position in two steps where the second step occurs a delay time after the first step. The delay time can be one-half of the period of the resonant frequency at the new position. | 12-24-2015 |
20150365696 | OPTICAL FLOW DETERMINATION USING PYRAMIDAL BLOCK MATCHING - An image processing system includes a processor and optical flow determination logic. The optical flow determination logic is to quantify relative motion of a feature present in a first frame of video and a second frame of video with respect to the two frames of video. The optical flow determination logic configures the processor to convert each of the frames of video into a hierarchical image pyramid. The image pyramid comprises a plurality of image levels. Image resolution is reduced at each higher one of the image levels. For each image level and for each pixel in the first frame, the processor is configured to establish an initial estimate of a location of the pixel in the second frame and to apply a plurality of sequential searches, starting from the initial estimate, that establish refined estimates of the location of the pixel in the second frame. | 12-17-2015 |
20150364600 | METHOD TO ENABLE HIGHER CARBON CO-IMPLANTS TO IMPROVE DEVICE MISMATCH WITHOUT DEGRADING LEAKAGE - An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least one of the angled carbon co-implant is greater than the implant energy of the boron halo implant. A total carbon dose of the angled carbon co-implants is at least 5 times a total boron dose of the boron halo implants. The NMOS transistor has a carbon concentration in the halo regions which is at least 5 times greater than the boron concentration in the halo regions. The co-implanted carbon extends under the gate of the NMOS transistor. | 12-17-2015 |
20150358827 | METHOD AND APPARATUS FOR TRANSMITTING LTE WAVEFORMS IN SHARED SPECTRUM BY CARRIER SENSING - A method of operating a long term evolution (LTE) communication system on a shared frequency spectrum is disclosed. A user equipment (UE) is initialized on an LTE frequency band. A base station (eNB) monitors the shared frequency spectrum to determine if it is BUSY. The eNB transmits to the UE on the shared frequency spectrum if it is not BUSY. The eNB waits for a first time if it is BUSY and directs the UE to vacate the shared frequency spectrum after the first time. | 12-10-2015 |
20150358050 | ADAPTIVE MODULATION SYSTEM AND METHOD TO MINIMIZE ENERGY CONSUMPTION - A communication device includes a modulating component, a transmitting component and a controlling component. The modulating component generates a first modulated packet and a second modulated packet. The first modulated packet is based on a first modulation scheme and the second modulated packet is based on a second modulation scheme. The first modulation scheme has a first amount of energy associated therewith, and the second modulation scheme has a second amount of energy associated therewith. The first amount of energy is less than the second amount of energy. The transmitting component generates a transmit packet based on one of the first modulated packet and the second modulated packet. The controlling component generates a control signal to instruct the modulating component to generate the first modulated packet When the transmit packet will be less than a predetermined threshold. The threshold is based on the first amount of energy. | 12-10-2015 |
20150349734 | DIFFERENTIAL AMPLIFIER WITH HIGH-SPEED COMMON MODE FEEDBACK - The differential signals at the outputs of a differential amplifier quickly change in response to common mode changes in the output differential signals. The amplified input signals amplified by the differential amplifier quickly change in response to common mode changes in the differential signals input into the differential amplifier. A bias voltage input to the differential amplifier is isolated to remove low-frequency components from the bias voltage. | 12-03-2015 |
20150349112 | TRENCH MOSFET HAVING REDUCED GATE CHARGE - A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together. | 12-03-2015 |
20150349110 | MOSFET HAVING DUAL-GATE CELLS WITH AN INTEGRATED CHANNEL DIODE - A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion. | 12-03-2015 |
20150348881 | Solder Coated Clip And Integrated Circuit Packaging Method - A method of making a QFD package including providing a clip and coating at least a first end portion of the clip with solder paste. | 12-03-2015 |
20150340952 | CIRCUITS AND METHODS TO LINEARIZE CONVERSION GAIN IN A DC-DC CONVERTER - Described examples include DC-DC power conversion systems, apparatus and methods for linearizing a DC-DC circuit conversion gain, including a gain circuit providing an output signal according to a gain value and the difference between a first compensation signal and a threshold signal, and a switching circuit selectively operative when the first compensation signal exceeds the threshold signal to linearize the conversion gain by providing a second compensation signal for pulse width modulation of at least one DC-DC converter switch according to the threshold signal and the gain circuit output signal. | 11-26-2015 |
20150340496 | TRANSISTOR HAVING DOUBLE ISOLATION WITH ONE FLOATING ISOLATION - A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats. | 11-26-2015 |
20150340324 | Integrated Circuit Die And Package - A semiconductor package assembly includes a substrate having an upper surface with a die attachment region thereon. A layer of die attachment material is positioned on top of the die attachment region. The semiconductor package assembly also includes an integrated circuit (“IC”) die. The die has a top portion including a laterally extending top wall surface and a plurality of generally vertically extending wall surfaces extending downwardly from the top wall surface. The die has a metallized bottom portion. The bottom portion has at least two metallized laterally extending wall surfaces and a plurality of metallized generally vertically extending connecting surfaces that connect the metallized laterally extending surfaces of the bottom portion. The layer of die attachment material interfaces with one or both of the metallized laterally extending surfaces and the plurality of metallized generally vertically extending connecting wall surfaces. | 11-26-2015 |
20150338866 | DC-DC CONVERTER CONTROLLER APPARATUS WITH DUAL-COUNTER DIGITAL INTEGRATOR - DC-DC converter PWM controllers and dual counter digital integrators are presented for integrating an error between a reference voltage signal and a feedback voltage signal, in which a comparator, dual counters, and a DAC are used to provide a compensated reference to a modulator loop comparator which generates a PWM switching signal for controlling a power converter output voltage, with the second counter being selectively incremented or decremented when the first counter output indicates a predetermined value after the first counter output transitions in one direction through a predetermined count range to enhance loop stability, and a startup mode control allows fast integrator operation during initialization, with the ability to freeze integrator operation during overcurrent conditions. | 11-26-2015 |
20150334353 | SENSOR SYNCHRONIZED NETWORKS USING OVERLAPPING SENSOR FIELDS - A method of synchronizing includes providing a sensor network including sensor nodes having object recognition sensors (ORS's) and building automation network nodes. The ORS's have partially overlapping fields of view in a sensed overlap area in the building. Movement of an individual through the sensed overlap area triggers dynamic synchronizing with the first sensor node waking up and sending a first RF request to join a subnet and for a schedule of wakeup times, the first sensor node receiving a response from any sensor node that receives the first request including synchronization information having times the first sensor node should wake up. The second sensor node is activated by the individual's movement and sends a second RF message to join the subnet and for a schedule of wakeup times. The first sensor node receives the second RF message and in response sends the synchronization information to the second sensor node. | 11-19-2015 |
20150333010 | BOND PAD HAVING RUTHENIUM DIRECTLY ON PASSIVATION SIDEWALL - A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads. | 11-19-2015 |
20150326236 | FRACTIONAL-N SYNTHESIZER WITH PRE-MULTIPLICATION - A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value. | 11-12-2015 |
20150326231 | TUNABLE FREQUENCY-TO-VOLTAGE CONTROLLED OSCILLATION - A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal. | 11-12-2015 |
20150326226 | LOAD SWITCH FOR CONTROLLING ELECTRICAL COUPLING BETWEEN POWER SUPPLY AND LOAD - Circuits and methods for controlling electrical coupling by a load switch are disclosed. In an embodiment, the load switch includes a pass element, level-shift circuit and low-resistance active path. The pass element is configured to be coupled to a power supply and a load, and is configured to electrically couple the power supply with the load during ON-state and electrically decouple the power supply from the load during OFF-state. The level-shift circuit includes a first transistor and pull-up resistor and is configured to generate a level-shifted signal in response to an enable signal, and enable the ON-state and the OFF-state of the pass element based on first and second voltages of the level-shifted signal. The low-resistance active path is coupled in parallel with the pull-up resistor for shunting the pull-up resistor in the OFF-state by providing a path for a leakage current of the first transistor in the OFF-state. | 11-12-2015 |
20150325501 | Cantilevered Leadframe Support Structure for Magnetic Wireless Transfer Between Integrated Circuit Dies - A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers. | 11-12-2015 |
20150325308 | METHOD AND APPARATUS FOR CONCURRENT TEST OF FLASH MEMORY CORES - An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access. | 11-12-2015 |
20150324208 | FAST STARTUP BEHAVIOR CONTROL OF A CPU - In an embodiment of the invention, a storage element which provides a user program is extended by logic which can detect special conditions and inject special start addresses on demand. During the read (fetch) of a start address of the user program, which is always at a fixed address for a given CPU, the conditions are used to respond to this read address either by different hardcoded addresses or by the original content of the memory. | 11-12-2015 |
20150323596 | METHOD AND APPARATUS FOR TEST TIME REDUCTION USING FRACTIONAL DATA PACKING - An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency. | 11-12-2015 |
20150318831 | CURRENT-LIMITING IN AN AMPLIFIER SYSTEM - One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude. | 11-05-2015 |
20150317087 | FILLER BANK CONTROL CIRCUIT FOR SYNCHRONOUS FIFO QUEUES AND OTHER MEMORY DEVICES - An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value. | 11-05-2015 |
20150311281 | HIGH BREAKDOWN N-TYPE BURIED LAYER - A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer. | 10-29-2015 |
20150309525 | Voltage Reference - A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor. The output voltage of the voltage reference circuit is compensated as a function of the measured ratio. | 10-29-2015 |
20150309111 | Multiple Rate Signature Test to Verify Integrated Circuit Identity - Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example. | 10-29-2015 |
20150303961 | MULTI-BRANCH OUTPHASING SYSTEM AND METHOD - A multi-level, multi-branch outphasing amplifier ( | 10-22-2015 |
20150300990 | SURFACE SENSING METHOD FOR CORROSION SENSING VIA MAGNETIC MODULATION - A method includes pulsating a magnetic field at a first location associated with an external surface of a wall containing magnetic material. The method also includes measuring at least one characteristic of the pulsating magnetic field at a second location associated with the external surface of the wall. The at least one characteristic changes based on corrosion on an internal surface the wall between the first and second locations. The magnetic field could be pulsated by applying an AC signal to a conductive coil or by vibrating a magnet. The method could also include analyzing the at least one measured characteristic to identify an amount of the corrosion and/or a change in the amount of the corrosion. Use of the internal surface the wall could be modified based on the amount or change of the corrosion. Multiple magnetic fields can be generated at multiple first locations, and the at least one characteristic can be measured at multiple second locations. | 10-22-2015 |
20150300962 | Assembly For Inspecting Machine Parts Used In The Production Of Semiconductor Components - An assembly for inspecting machine parts used in the production of semiconductor devices, such as integrated circuit (IC) dies. The assembly includes a laser scanning apparatus adapted to precisely measure predetermined parameters of the machine parts. | 10-22-2015 |
20150294983 | ISOLATED SEMICONDUCTOR LAYER OVER BURIED ISOLATION LAYER - An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate. | 10-15-2015 |
20150294902 | ISOLATED SEMICONDUCTOR LAYER IN BULK WAFER BY LOCALIZED SILICON EPITAXIAL SEED FORMATION - An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer. | 10-15-2015 |
20150294895 | LOCALIZED REGION OF ISOLATED SILICON OVER DIELECTRIC MESA - An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa. | 10-15-2015 |
20150291369 | TRAY LOADING SYSTEM FOR ELECTRONIC COMPONENTS - A tray loading system for tested electronic components including a tray loading bin adapted to prevent trays of a first configuration from being operably received in a first bin operating mode and to operably receive trays of the first configuration in a second bin operating mode. The system also includes an operating mode switching assembly adapted to automatically change from the second operating mode to the first operating mode in response to an operation associated with removal of loaded trays of the first configuration from the tray loading bin. | 10-15-2015 |
20150280699 | LINEARIZATION CIRCUIT FOR HIGH FREQUENCY SIGNAL PHASE ADJUSTMENT - A circuit includes a phase adjustment capacitor (PAC) coupled to a signal path and configured to adjust a phase of a signal on the signal path. A transistor switch device is coupled in series with the PAC to provide a circuit branch parallel with the signal path. The transistor switch device is configured to selectively open or close the circuit branch of the signal path to enable or disable, respectively, the adjustment of the phase of the signal on the signal path via the PAC. A nonlinear capacitance is coupled to a node interconnecting the PAC and the transistor switch device. The nonlinear capacitance is configured to vary inversely proportional with a capacitance of the transistor switch device with respect to the signal on the signal path and to linearize a total capacitance provided by the circuit branch when the circuit branch is open. | 10-01-2015 |
20150279487 | Memory Repair Categorization Tracking - An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category. | 10-01-2015 |
20150278008 | CRC-BASED FORWARD ERROR CORRECTION CIRCUITRY AND METHOD - A communication system includes digital transmitter circuitry ( | 10-01-2015 |
20150271913 | ELECTRONIC DEVICE PACKAGE WITH VERTICALLY INTEGRATED CAPACITORS - A system-in-a-package (SIP) has a semiconductor chip embedded in a dielectric substrate. An inductor is on a top surface of a substrate and is connected to the semiconductor chip. A thin film capacitor may be placed between the inductor and the dielectric substrate. A second thin film capacitor may be placed on the top surface of the semiconductor chip, or be embedded in the dielectric substrate with a thermal pad on a bottom surface of the substrate which is connected to the second thin film capacitor to facilitate heat dissipation. | 09-24-2015 |
20150270708 | ESD PROTECTION CIRCUIT WITH PLURAL AVALANCHE DIODES - An electrostatic discharge (ESD) protection circuit (FIG. | 09-24-2015 |
20150270257 | SERIES CONNECTED ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit (FIG. | 09-24-2015 |
20150270256 | SEGMENTED NPN VERTICAL BIPOLAR TRANSISTOR - A segmented bipolar transistor includes a p-base in a semiconductor surface including at least one p-base finger having a base metal/silicide stack including a base metal line that contacts a silicide layer on the semiconductor surface of the p-base finger. An n+ buried layer is under the p-base. A collector includes an n+ sinker extending from the semiconductor surface to the n+ buried layer including a collector finger having a collector metal/silicide stack including a collector metal line that contacts a silicide layer on the semiconductor surface of the collector finger. An n+ emitter has at least one emitter finger including an emitter metal/silicide stack that contacts the silicide layer on the semiconductor surface of the emitter finger. The emitter metal/silicide stack and/or collector metal/silicide stack include segmentation with a gap which cuts a metal line and/or the silicide layer of the stack. | 09-24-2015 |
20150270253 | PROGRAMMABLE ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit (FIG. | 09-24-2015 |
20150264455 | Drivers And Methods Of Driving Tranducers - A transducer has an input and produces a mechanical output, wherein the magnitude of the mechanical output of the transducer is dependent on the frequency and magnitude of current at the input. A driver for the transducer includes a device having a transfer function associated with the device, the device having a device input and a device output, the device output being connectable to the input of the transducer and the device input being connectable to a power source. The device attenuates the current output at a frequency that causes a peak in the magnitude of the mechanical output of the transducer. | 09-17-2015 |
20150263759 | ANALOG-TO-DIGITAL CONVERTER - A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter. | 09-17-2015 |
20150263744 | DUAL COMPARATOR-BASED ERROR CORRECTION SCHEME FOR ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC. | 09-17-2015 |
20150262920 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces. | 09-17-2015 |
20150262852 | Carrier Tape Packaging Method And Apparatus - An apparatus for detecting misplaced units in a moving carrier tape having a plurality of pockets with units positioned therein. The apparatus includes a displaceable assembly having a head portion positioned above the carrier tape that is adapted to deflect in response to engagement with a misplaced unit in one of the plurality of pockets. | 09-17-2015 |
20150262569 | PROCESSOR CHIP WITH ULTRASOUND TRANSDUCER FOR ULTRASOUND CHIP DEBUGGING - A transceiver device combination includes a first ultrasound transducer and a processor chip including a central processing unit (CPU). A memory is coupled to the CPU including stored ultrasound communications software for rendering the processor chip a target device for an ultrasound probe driven via a host computing device having a second ultrasound transducer for together performing ultrasonic debugging of the processor chip. The transceiver device combination includes (i) a transmit path including an ultrasound driver having an input driven by an output of the CPU, where an output of the ultrasound driver is coupled to drive an input of the first ultrasound transducer to transmit ultrasound signals and (ii) a receive path including analog signal processing circuitry that couples an output of the first ultrasound transducer responsive to received ultrasound signals from the ultrasound probe to an input of the CPU. | 09-17-2015 |
20150256216 | METHOD AND APPARATUS FOR DIGITAL PREDISTORTION FOR A SWITCHED MODE POWER AMPLIFIER - A method includes receiving an input signal and predistorting a baseband representation of the input signal at a carrier frequency and at one or more harmonic frequencies. The method also includes generating an output signal based on the predistorted baseband representation of the input signal, and transmitting the output signal to a power amplifier. Predistorting the baseband representation of the input signal at the carrier frequency could occur in parallel with predistorting the baseband representation of the input signal at the one or more harmonic frequencies. | 09-10-2015 |
20150255596 | LDMOS TRANSISTOR AND METHOD OF FORMING THE LDMOS TRANSISTOR WITH IMPROVED RDS*CGD - The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region. | 09-10-2015 |
20150249907 | METHOD AND SYSTEM FOR LOCATION ESTIMATION - Several systems and methods for location estimation in a multi-floor environment are disclosed. In an embodiment, the method includes performing wireless scanning so as to receive wireless signals from one or more access points from among a plurality of access points positioned at plurality of locations, respectively at one or more floors from among a plurality of floors within the multi-floor environment. A first set of RSSI measurements is computed corresponding to the wireless signals. Absolute floor location information is determined based on the first set of RSSI measurements and a pre-defined objective function. The pre-defined objective function is configured to maximize a probability of a user being located at a floor so as to receive the wireless signals. A user floor location is determined based on the absolute floor location information. The user location is estimated at least in part based on the user floor location. | 09-03-2015 |
20150249881 | POWER CONTROL FOR MULTICHANNEL SIGNAL PROCESSING CIRCUIT - A circuit includes an input channel array that includes a plurality of channels to receive a plurality of input signals and generate a plurality of channel output signals. A processor to processes the plurality of channel output signals from the input channel array. The processor and the input channel array are configured to operate in a sleep mode when all of the analog input signals are inactive or an active mode when at least one of the analog input signals is active. A secondary channel samples the plurality of input signals and generates a secondary output signal indicative of activity for at least one of the input signals. A secondary channel detector determines a level of signal activity for any of the input signals during the sleep mode based on the secondary output signal. | 09-03-2015 |
20150249458 | ON-CHIP ANALOG-TO-DIGITAL CONVERTER (ADC) LINEARITY TEXT FOR EMBEDDED DEVICES - A method for testing linearity of an ADC, comprising receiving a trigger signal indicating an ADC input voltage step adjustment, reading an ADC output sample upon receiving the trigger signal, wherein the ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes, computing a histogram of code occurrences for M consecutive ADC output codes, wherein the histogram comprises M number of bins corresponding to the M consecutive ADC output codes, and wherein M is less than N, updating a DNL value and an INL value according to the histogram at an interval of K number of ADC output sample readings, and shifting the histogram by one ADC output code after updating the DNL and the INL values. | 09-03-2015 |
20150247928 | COOPERATIVE LOCATION SENSOR APPARATUS AND SYSTEM FOR LOW COMPLEXITY GEOLOCATION - A location or position sensor apparatus and sensor systems are presented, in which individual location sensors store and wirelessly exchange orbital information, soft demodulation information, position and time of day information, and the sensors share decoding and computation tasks related to acquiring and tracking navigation satellites to conserve power and to facilitate determination of sensor positions. | 09-03-2015 |
20150244386 | BACKGROUND DAC CALIBRATION FOR PIPELINE ADC - A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current. | 08-27-2015 |
20150244355 | LOW-POWER OFFSET-STORED LATCH - A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase. | 08-27-2015 |
20150243648 | QUANTUM WELL-MODULATED BIPOLAR JUNCTION TRANSISTOR - A semiconductor device includes a quantum well-modulated bipolar junction transistor (QW-modulated BJT) having a base with an area for a modulatable quantum well in the base. The QW-modulated BJT includes a quantum well (QW) control node which is capable of modulating a quantity and level of energy levels of the quantum well. A recombination site abuts the area for the quantum well with a contact area of at least 25 square nanometers. The semiconductor device may be operated by providing a reference node such as ground to the emitter and a power source to the collector. A bias voltage is provided to the gate to form the quantum well and a signal voltage is provided to the gate, so that the collector current includes a component which varies with the signal. | 08-27-2015 |
20150243639 | INTEGRATED PASSIVE FLIP CHIP PACKAGE - A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die. | 08-27-2015 |
20150243494 | MECHANICALLY ROBUST SILICON SUBSTRATE HAVING GROUP IIIA-N EPITAXIAL LAYER THEREON - A method of forming an epitaxial article includes growing a crystal of elemental silicon having a minimum boron doping level of 3.2×10 | 08-27-2015 |
20150236730 | subtracting linear impairments for non-linear impairment digital pre-distortion error signal - Example embodiment of the systems and methods of linear impairment modeling to improve digital pre-distortion adaptation performance includes a DPD module that is modified during each sample by a DPD adaptation engine. A linear impairment modeling module separates the linear and non-linear errors introduced in the power amplifier. The linear impairment model is adjusted during each sample using inputs from the input signal and from a FB post processing module. The linear impairment modeling module removes the linear errors such that the DPD adaptation engine only adapts the DPD module based on the non-linear errors. This increases system stability and allows for the correction of IQ imbalance inside the linear impairment modeling, simplifying the feedback post-processing. | 08-20-2015 |
20150236670 | OUTPUT RANGE FOR INTERPOLATION ARCHITECTURES EMPLOYING A CASCADED INTEGRATOR-COMB (CIC) FILTER WITH A MULTIPLIER - A cascaded integrator-comb filter (CIC) that includes a differentiator, a rate changer, an integrator, and a multiplier. The differentiator is configured to differentiate an input signal to produce a differentiated input signal. The rate changer is coupled to the differentiator and is configured to interpolate the differentiated input signal based on an interpolation rate to produce an upsample signal. The integrator is coupled to the rate changer and is configured to integrate the upsample signal to produce an output signal. The multiplier is coupled to the differentiator, rate changer, and integrator and is configured to increase the output signal amplitude based on the interpolation rate. | 08-20-2015 |
20150234519 | TOUCHSCREEN CONTROLLER AND METHOD FOR CHARGER NOISE REDUCTION THROUGH NOISE SHAPING - Touch screen controllers and methods are presented for removing charger noise and other high frequency noise from touch screens in the presence of aliasing in which a digital low pass filter rejects the high frequency noise, a noise tracker determines whether noise is being aliased into the low pass filter pass band, and a noise shaper artificially induces or modifies aliasing in the system by adjusting an analog-to-digital converter sampling frequency and/or a panel scan frequency to try to move the aliased noise outside the low pass filter pass band. | 08-20-2015 |
20150234404 | LOW DROPOUT VOLTAGE REGULATOR CIRCUITS - In an embodiment, a voltage regulator is disclosed. The voltage regulator circuit includes a switch, a first feedback circuit and a second feedback circuit. The switch is configured to receive an input signal at a first terminal and an error signal at a second terminal and configured to generate an output signal at a third terminal. The first feedback circuit includes a first transistor and a second transistor configured to control the error signal at the second terminal of the switch in response to a difference between the output signal and a reference signal. The second feedback circuit is configured to sense the error signal and generate a tail current at the second node and the fourth node to maintain substantially equal currents in the first transistor and the second transistor, respectively, thereby causing a voltage of the output signal as substantially equal to a voltage of the reference signal. | 08-20-2015 |
20150234000 | Real Time Semiconductor Process Excursion Monitor - Semiconductor process excursions may be monitored by fabricating functional circuitry on a plurality of semiconductor devices and then testing the functional circuitry of the plurality of semiconductor devices using a sequence of test patterns. A cumulative failure curve may be determined that has points of discontinuity based on results of testing with the sequence of test patterns. A point of discontinuity magnitude at a selected location in the cumulative failure curve may be compared to an expected discontinuity magnitude. Process excursion analysis may be indicated when a point of discontinuity magnitude exceeds an expected magnitude threshold. | 08-20-2015 |
20150229199 | Constant On-Time Control for Power Converter - An electronic device includes a power stage, a switch and a controller. Power is transferred from an input through the power stage to an output. The switch turns on and off a current provided to the power stage for transferring the power. The controller turns on and off the switch. During a low-load mode, the controller causes the switch to operate with a constant on-time control. | 08-13-2015 |
20150224615 | TURNTABLE - An apparatus for rotating a load about a predetermined rotation axis of the apparatus. The apparatus includes a rotatable shaft having a central longitudinal axis; a turntable fixedly mounted on the rotatable shaft; an annular centering surface; and a stud member positioned opposite the annular centering surface. Either the annular centering surface or the stud member is affixed to the turntable. The annular centering surface and the stud member are adapted to co-act to maintain the central longitudinal axis of the rotatable shaft in alignment with the predetermined rotation axis of the apparatus. | 08-13-2015 |
20150222903 | METHOD AND APPARATUS FOR SUB-PICTURE BASED RASTER SCANNING CODING ORDER - A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning order within sub-pictures, wherein from core to core, coding of the sub-picture is independent around sub-picture boundaries, and wherein within a core, coding of a sub-picture is at least one of dependent or independent around sub-picture boundaries. | 08-06-2015 |
20150222463 | TRANSMITTER AND METHOD OF TRANSMITTING - At least one tone is generated. An output signal is generated in response to an input signal and the at least one tone. The output signal is modulated. The input signal and the at least one tone are represented in the modulated output signal. The at least one tone is outside a bandwidth of the input signal as represented in the modulated output signal. The modulated output signal is amplified. The at least one tone in the amplified signal is attenuated after the amplifying. | 08-06-2015 |
20150222217 | TRAVELLING WAVE MOTOR PRE-DRIVER USING HIGH RESOLUTION PWM GENERATORS - A motor driver combination for controlling a travelling wave motor includes a pre-driver including a microcontroller unit (MCU) chip including a plurality of high-resolution pulse width modulation (HRPWM) generators providing a frequency resolution better than ten Hz. A digital bus is for transferring digital words received from a controller in a servo and velocity control block to the HRPWM generators, where the digital words provide travelling wave motor operating performance information from the motor during its operation. A clock oscillator providing an accuracy of at least eighty (80) parts per million (ppm) is coupled to or provided by the MCU chip for each of the high-resolution PWM generators. A motor driver includes a plurality of power drivers for providing phased outputs for driving the travelling wave motor including a plurality of inputs coupled to outputs of the plurality of HRPWM generators. The travelling wave motor can be an ultrasonic motor. | 08-06-2015 |
20150221524 | SLOPED PHOTORESIST EDGES FOR DEFECT REDUCTION FOR METAL DRY ETCH PROCESSES - A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer. | 08-06-2015 |
20150220065 | CIRCUIT FOR DETECTING AND CORRECTING TIMING ERRORS - A circuit for detecting and correcting timing errors. A timing circuit includes an interpolator. The interpolator includes a fine counter, a coarse counter, and stop correction logic. The coarse counter is incremented by a rollover output of the fine counter to generate a coarse count value. The stop correction logic is coupled to the fine counter and the coarse counter. The stop correction logic divides each cycle of the rollover output into first, second, and third time intervals, and selects a coarse counter output value to represent a time interval measured by the coarse counter based on a one of the first, second, and third intervals in which a time measurement stop signal is detected. | 08-06-2015 |
20150215968 | RANDOM ACCESS CHANNEL FALSE ALARM CONTROL - A wireless device includes a preamble detector configured to identify preambles transmitted via a random access channel of a wireless network. The preamble detector includes preamble false alarm logic. The preamble false alarm logic is configured to set a preamble false alarm detection window, and compare, to one another, preambles identified in the false alarm detection window. The preamble false alarm logic is configured to identify, based on the comparison, a largest of the preambles in the false alarm detection window, and reject all but the identified largest of the preambles as false alarm detections. | 07-30-2015 |
20150214934 | RELAXATION OSCILLATOR WITH LOW DRIFT AND NATIVE OFFSET CANCELLATION - Relaxation oscillator circuitry is presented with low drift and native offset cancellation, including an amplifier amplifying a first current signal to provide a pulse amplifier output waveform, an integrator integrating a second current signal to provide a ramp output waveform, and a comparator comparing the integrator output waveform with a threshold set by the amplifier output waveform to generate an alternating oscillator output used to switch the polarities of the first and second current signals. | 07-30-2015 |
20150214907 | SYSTEM, METHOD AND DEVICE FOR POWER AMPLIFICATION OF A SIGNAL IN AN INTEGRATED CIRCUIT - According to an aspect of present disclosure, a set of power amplifiers are used to amplify power of a signal for transmission. The signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding. A current path on the primary side is provided for flow of a current that is induced on at least one primary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing in to the power amplifier that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency. In one embodiment, the current path is provided using a resistor network. | 07-30-2015 |
20150214136 | SEMICONDUCTOR DEVICE HAVING LEADFRAME WITH PRESSURE-ABSORBING PAD STRAPS - A leadframe ( | 07-30-2015 |
20150212152 | TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION - Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously. | 07-30-2015 |
20150212150 | DFT APPROACH TO ENABLE FASTER SCAN CHAIN DIAGNOSIS - A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input. | 07-30-2015 |
20150212143 | KILL DIE SUBROUTINE AT PROBE FOR REDUCING PARAMETRIC FAILING DEVICES AT PACKAGE TEST - A method of testing semiconductor devices includes contacting bond pads coupled to integrated circuitry on a first die of a plurality of interconnected die on a substrate using a probe system having probes and probe tests including parametric tests, continuity tests, and a kill die subroutine. Probe tests using the probe program are performed. Die are binned into a first bin (Bin 1 die) for being a good die for all probe tests, or a second bin (Bin 2 die) for failing at least one of continuity tests and parametric tests. The Bin 2 die are divided into a first sub-group that failed the continuity tests and a second sub-group that do not fail the continuity tests. A kill die subroutine is triggered including applying power sufficient to selectively cause damage to the second sub-group of Bin 2 die to generate a continuity failure and thus generate kill die. | 07-30-2015 |
20150208451 | Access Point Discoverability in Multi-Role Multi-Channel Devices - Systems and methods for improved access point discoverability in multi-role multi-channel devices are described. When the multi-role multi-channel device leaves an AP role and then later returns to the AP role, such as when operating in another role, the multi-role multi-channel device sends a unicast probe response to the stations in a predetermined list. The unicast probe response is transmitted even without receiving a corresponding probe request. If one of the stations on the list is in the area and would like to connect to the AP role, it can complete the connection process using information in the response message. | 07-23-2015 |
20150207405 | INPUT OFFSET CONTROL - Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a second input circuit. The first input circuit is configured to operate within first common mode voltage range, configured to provide first input current, and configured to vary the first input current upon or subsequent to a variation of a voltage level in the first common mode voltage range. The second input circuit is coupled to the first input circuit and is configured to operate within second common mode voltage range, configured to provide a second input current, and configured to vary the second input current based on variation of the voltage level in the second common mode voltage range. Upon or subsequent to increasing the common mode voltage, the first input current is reduced and the second input current is increased. | 07-23-2015 |
20150207400 | CONTROL APPARATUS AND METHOD FOR THERMAL BALANCING IN MULTIPHASE DC-DC CONVERTERS - Integrated circuit apparatus and processes are presented for controlling a plurality of parallel-connected DC-DC converter phases forming a multiphase DC-DC conversion system in which individual converter phases are successively activated or deactivated for increasing and decreasing load conditions, respectively, according to an ordered phase sequence, and the phase sequence is selectively modified to promote thermal balancing of the DC-DC converter phases. | 07-23-2015 |
20150198664 | INTEGRATED CIRCUIT - Integrated circuits and methods for testing integrated circuits are disclosed herein. An embodiment of an integrated circuit includes a microprocessor and memory that is accessible by the microprocessor. The integrated circuit also includes reconfigurable logic, wherein a first test program for testing at least one of the microprocessor and memory is loadable onto the reconfigurable logic. At least one other program is loadable into the reconfigurable logic after the first test program runs. | 07-16-2015 |
20150188561 | NOVEL TECHNIQUE TO COMBINE A COARSE ADC AND A SAR ADC - A successive approximation register analog to digital converter (SAR ADC) is disclosed. The SAR ADC receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode. | 07-02-2015 |
20150188533 | Bootstrapped Sampling Switch Circuits and Systems - A bootstrap circuit for a sampling transistor. A circuit includes a MOS transistor having a source terminal coupled to an input for receiving an input voltage; an output at a drain terminal of the MOS transistor coupled to one plate of a sampling capacitor; a first switch coupling the input voltage to a gate terminal of the MOS transistor responsive to an initial phase control signal; a bootstrap capacitor having a top plate coupled to the gate terminal of the MOS transistor and coupled to the first switch; a second switch coupling a bottom plate of the bootstrap capacitor to a first low voltage supply responsive to the initial phase control signal; a third switch coupling the bottom plate of the bootstrap capacitor to a positive voltage supply greater than the first low voltage supply responsive to a first phase periodic control signal. Additional circuits and systems are disclosed. | 07-02-2015 |
20150188413 | MULTIPLE OUTPUT INTEGRATED POWER FACTOR CORRECTION - A multiple-output integrated power factor correction system includes, for example, a processor that is formed in a substrate and is arranged to monitor each voltage output of two or more output stages of a power supply and in response to generate an individual voltage error signal for each monitored output stage. A combined output voltage error signal is generated in response to each of the individual voltage error signals. The voltage input to the power supply and the total inductor current of the power supply are monitored and used to generate a combined output voltage control signal in response to the monitored input voltage total inductor current as well as the combined output voltage error control signal. Each individual output voltage control signal for each monitored output stage is generated in response to each of the respective generated individual voltage error signals. | 07-02-2015 |
20150180692 | CIRCUITS AND METHODS FOR TRANSMITTING SIGNALS - For generating quantized signals, a quantized phase domain related to quantized phases of an input signal is generated. Vectors that the input signal may occupy are calculated based on the quantized phase domain. A first quantized phase of a first component of the input signal is generated per the quantized phase domain, and a second quantized phase of a second component of the input signal is generated per the quantized phase domain. | 06-25-2015 |
20150180594 | SELF-CALIBRATING SHARED-COMPONENT DUAL SYNTHESIZER - A self-calibrating shared-component dual synthesizer includes, for example, two frequency synthesizers that are adapted to operate (respectively) in transmit (TX) and receive (RX) modes. Each synthesizer can be selectively arranged to vary and optimize the phase noise in accordance with the TX and RX requirements associated with each mode as well as independently optimized for flexible low area floorplan to achieve low power, spectral fidelity and reduced test time, low cost built in self-calibration. The two frequency synthesizers are also adapted to provide a built-in self-test signals used for intermodulation testing and calibration. | 06-25-2015 |
20150177326 | Waveform Calibration Using Built In Self Test Mechanism - A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components. | 06-25-2015 |
20150162830 | POWER CONVERTER SOFT START CIRCUIT - PWM control circuits and soft start circuitry thereof are presented in which a source follower circuit provides an input to a pulse generator error amplifier during startup according to a lower one of an internal soft start circuit ramp signal and a voltage across and externally connected capacitor, with a current source connected to the source follower to limit the charging current supplied to the externally connected capacitor. | 06-11-2015 |
20150149331 | Taking Device Inventory using Dynamically Generated Symbols - A method for inventorying one or more devices may be initiated by receiving an input command to request a device identification (ID) for one of the devices. A unique ID image that is indicative of the ID of one device may then be dynamically created. The unique ID image may be displayed on a display screen coupled to the one device, whereby the unique ID image is available to be observed by an inventory input device. The unique ID image may be a quick response (QR) bar code. The display screen may be part of a hand-held calculator, and the one device may be a network module coupled to the hand-held calculator. | 05-28-2015 |
20150146174 | PROJECTOR WITH OPTICAL CONVERSION MEDIA PUMPED BY LOW ETENDUE SOURCE - A projector system with a single imaging array has a low-etendue light source. The projector system includes a first optical path from the low-etendue light source to a plurality of optical conversion media having a plurality of emission wavelengths to provide display light with wavelengths longer than blue light. The projector system includes a second optical path from the optical conversion media to the imaging array. The projector system has a means of moving an excitation location on the optical conversion media in the first optical path. The projector system may include a blue LED, a diffuser region, or an optical conversion medium with a blue emission wavelength to provide blue display light. Light from the low-etendue light source is prevented from directly impinging on the imaging array. | 05-28-2015 |
20150145497 | LOW-LOSS STEP-UP AND STEP-DOWN VOLTAGE CONVERTER - A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided. | 05-28-2015 |
20150138995 | METHOD, SYSTEM AND APPARATUS FOR PHASE NOISE CANCELLATION - According to an aspect of the present disclosure, a baseband signal and a pilot signal are combined for a transmission. The combined signal is then translated to higher frequency band by mixing a local oscillator signal and the combined signal. On the receiver, the pilot signal is used to remove the phase noise in the baseband signal, as both baseband signal and the pilot signal are affected/modified by substantially the same phase noise. In one embodiment, the pilot signal may be selected either centered outside the bandwidth of the base band signal or centered inside the bandwidth of the base band signal with enough guard band around it so that it can be filtered out using filters. The pilot signal is used in a similar fashion to eliminate the effect of the phase noise introduced by the local oscillator present in the tester in testing the receiver device. | 05-21-2015 |
20150138446 | Compact Optical Projection Apparatus - A compact optical projection apparatus. An apparatus for light projection includes at least one illumination device; a cover prism including a curved surface positioned to receive illumination light rays and a total internal reflection surface positioned to internally reflect the light rays towards an asymmetric reflector surface positioned opposite the total internal reflection surface, the asymmetric reflector surface configured to reflect the received light rays out of the cover prism at an emitter side of the cover prism; a spatial light modulating the illumination light rays with image data to form image light rays; a reverse total internal reflection (RTIR) prism positioned between the spatial light modulator and the emitter side of the cover prism and further comprising a total internal reflection surface configured to totally internally reflect the image light rays out of the RTIR prism into a light projection device. Additional apparatus are disclosed. | 05-21-2015 |
20150137700 | Systems and Methods of Driving Multiple Outputs - Systems and methods of driving multiple outputs are provided in which a single inductor may be used to drive multiple output such as independent strings of LEDs or white LEDs (WLEDs). In an example embodiment, a boost DC to DC converter may be used with a single inductor to drive multiple outputs. In an example embodiment, the error voltage of each of the multiple outputs is sampled during each cycle of the DC to DC converter and the largest error voltage is determined for that cycle. Power from the DC to DC converter is then supplied to that output during that cycle. | 05-21-2015 |
20150135152 | Clock Tree Design - A clock tree design tool is described which receives input from a user via a graphical user interface (GUI) through a first window, the input including an indication of an output clock frequency. The tool also detects selection by the user of a soft control and, as a result of detecting selection of the soft control, generates a plurality of clock tree solutions. The tool further causes a graphical form of a highlighted one of the clock tree solutions to be displayed in a second window of the GUI. An algorithm for generating the various clock tree solutions is also disclosed. | 05-14-2015 |
20150134711 | FILE ACCESS METHOD AND SYSTEM THEREOF - Several systems and methods for accessing files stored in a storage device are disclosed. In an embodiment, the method includes accessing a file allocation table (FAT) in a computer file system associated with the storage device. The FAT includes a plurality of cluster addresses corresponding to a plurality of clusters allocated to a file stored in the storage device. A cluster address is read to identify a location of a next cluster. One or more bits in the cluster address are read to determine a presence of a signature value indicating allocation of a set of contiguous clusters from among the plurality of clusters. A number of contiguous clusters is computed based on a pre-determined number of consecutive cluster addresses succeeding the cluster address if the signature value is present. The set of contiguous clusters are read from the storage device based on the computed number of contiguous clusters. | 05-14-2015 |
20150130755 | Integrated Receiver and ADC for Capacitive Touch Sensing Apparatus and Methods - An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed. | 05-14-2015 |
20150130527 | LOW POWER SCHEME TO PROTECT THE LOW VOLTAGE CAPACITORS IN HIGH VOLTAGE IO CIRCUITS - An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode. | 05-14-2015 |
20150127992 | USING AN IN-SYSTEM COMPONENT AS AN EMBEDDED TRACE RECEIVER - A system having a plurality of application computer circuits is disclosed. A first application computer circuit is arranged to process a first application. A trace collection circuit collects trace information from the first application computer circuit. A second application computer circuit is arranged to receive and store the collected trace information in a first mode and to process a second application in a second mode. | 05-07-2015 |
20150127695 | PROCESSOR TRIGONOMETRIC COMPUTATION - A method for a processor computing a first trigonometric function to use an alternative trigonometric function for certain ranges of the operand. A modulo function may be used to provide an operand with a reduced range, and the modulo function may subtract in multiple steps in a manner that preserves low-order bits. | 05-07-2015 |
20150124663 | METHOD AND APPARATUS FOR CONFIGURATON, MEASUREMENT AND REPORTING OF CHANNEL STATE INFORMATION FOR LTE TDD WITH DYNAMIC UL/DL CONFIGURATION - A method of operating a time division duplex (TDD) wireless communication system is disclosed. The method includes establishing communications with a remote transceiver. A subframe configuration including static and flexible subframes is determined and transmitted to the remote transceiver. A channel state information (CSI) report is received from the remote transceiver in response to the subframe configuration. | 05-07-2015 |
20150123711 | OPTIMIZED PEAK DETECTOR for the AGC LOOP IN A DIGITAL RADIO RECEIVER - A method of peak detection applicable to complex in-phase and quadrature phase signals in a digital radio receiver where the incoming signal is divided into a plurality of frames. Each frame is then further divided into a plurality of smaller blocks, and the signal peak is determined in each block individually followed by selecting the peak signal value from the said blocks. | 05-07-2015 |
20150123710 | CROSS-CONDUCTION DETECTOR FOR SWITCHING REGULATOR - An integrated circuit includes a detector configured to monitor a high-drive signal and a low-drive signal that drives a high-side switch and a low-side switch respectively of an integrated circuit switching regulator. The detector monitors both the rising edge and the trailing edge of each of the high-drive and the low-drive signals respectively to determine a timing overlap between the signals and generates a detection signal indicating a dead-time value proportional to the presence or absence of the timing overlap between the signals. An output circuit can be configured to process the detection signal from the detector to enable a correction of the timing overlap between the signals if timing overlap is detected. | 05-07-2015 |
20150123627 | POWER CONVERTERS AND COMPENSATION CIRCUITS THEREOF - In an embodiment, a circuit includes a Direct Current (DC)-DC buck-boost converter and a controller. The controller includes an error amplifier configured to receive a feedback signal responsive to an output signal of the buck-boost converter. The error amplifier is configured to compare the feedback signal and a reference signal to generate an error signal. The controller includes a modulator circuit that is configured to receive the error signal and compare the error signal with a periodic ramp signal to generate a modulated signal. The controller further includes a digital logic block to generate switching signals in response to the modulated signal that is fed to the buck-boost converter to control the output signal of the buck-boost converter. The controller includes a capacitance multiplier circuit coupled to the output of the error amplifier to configure a dominant pole so as to compensate the buck-boost converter. | 05-07-2015 |
20150121043 | COMPUTER AND METHODS FOR SOLVING MATH FUNCTIONS - Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy. | 04-30-2015 |
20150120726 | Using Audio Cues to Improve Object Retrieval in Video - A method of object retrieval from visual data is provided that includes annotating at least one portion of the visual data with a context keyword corresponding to an object, wherein the annotating is performed responsive to recognition of the context keyword in audio data corresponding to the at least one portion of the visual data, receiving a query to retrieve the object, wherein the query includes a query keyword associated with both the object and the context keyword, identifying the at least one portion of the visual data based on the context keyword, and searching for the object in the at least one portion of the visual data using an appearance model corresponding to the query keyword. | 04-30-2015 |
20150120026 | ANALOG-TO-DIGITAL CONVERTER - A system includes an analog-to-digital converter receiving a plurality of input signals. One particular input signal has a particular analog value and the analog-to-digital converter uses a fixed reference to convert the particular analog value to a particular digital value. The analog-to-digital converter uses the particular analog value as a reference for converting the analog values of the remaining input signals. | 04-30-2015 |
20150117575 | METHOD, SYSTEM AND APPARATUS FOR CARRIER FREQUENCY OFFSET CORRECTION AND CHANNEL ESTIMATION - A receiver is configured to use a first part of a received signal and a second part of the received signal to determine, respectively, a first estimate and a second estimate of the channel. The first and second parts carry information for decoding the received signal in a first protocol and in a second protocol, respectively. A final estimate of the channel is performed from the first and the second estimates. The final estimate is then used for decoding the data in the received signal according to one of the protocols. A carrier frequency offset from a set of symbols occurring prior to preamble symbols is determined and is corrected for decoding the preamble symbols. The corrected preamble symbols are then used for estimating the channel. In one embodiment, the carrier frequency offset is determined for the multiple antenna packet format used in the 802.11n standard. | 04-30-2015 |
20150116027 | UNIFIED BANDGAP VOLTAGE CURVATURE CORRECTION CIRCUIT - A unified bandgap voltage waveform compensation amplifier is arranged having shared input transistor pairs, a shared load resistor, and shared current sources. For example, a first amplifier structure is arranged to produce a negative-going bias correction signal when a bandgap voltage reference increases as operating temperatures rise and a second amplifier structure is arranged to produce a positive-going bias correction signal when the bandgap voltage reference increases as operating temperatures rise. The unified amplifier is arranged to combine the positive- and negative-going signals to generate a combined compensation current that is used to compensate for temperature instability of the bandage voltage reference. | 04-30-2015 |
20150115929 | METHOD AND APPARATUS FOR GENERATING PIECE-WISE LINEAR REGULATED SUPPLY - The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that receives a reference voltage and an analog supply voltage. A second clamp circuit receives the reference voltage. A voltage divider circuit is coupled to the first clamp circuit and the second clamp circuit. The voltage divider circuit receives a peripheral supply voltage and generates a regulated supply voltage. | 04-30-2015 |
20150113030 | NOVEL APPROACH FOR SIGNIFICANT IMPROVEMENT OF FFT PERFORMANCE IN MICROCONTROLLERS - A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log | 04-23-2015 |
20150103908 | METHOD AND APPARATUS FOR A LOW COMPLEXITY TRANSFORM UNIT PARTITIONING STRUCTURE FOR HEVC - A method and apparatus for a low complexity transform unit partitioning structure for High Efficiency Video Coding (HEVC). The method includes determining prediction unit size of a coding unit, and setting the size of transform unit size of Y, U and V according to the prediction unit size of the coding unit. | 04-16-2015 |
20150103566 | Systems and Methods of CCM Primary-Side Regulation - Example embodiments of the systems and methods of CCM primary-side regulation disclosed herein subtract an estimate of the secondary IR drop from each output voltage sample. This allows a fixed sample instant to be set (with regard to the beginning of the off or flyback interval), and removes the need to hunt for or adjust to an optimum sample instant, or one with minimum IR drop error. The estimate of the IR drop may be adjusted on a cycle-by-cycle basis, based on the commanded primary peak current, knowing that the peak secondary current will be directly proportional by the turns ratio of the transformer. For improved accuracy, an adjustment may be made for the decay of secondary current during the delay to the sample instant, if the inductance value is known. | 04-16-2015 |
20150103563 | AUTOMATIC TIMING ADJUSTMENT FOR SYNCHRONOUS RECTIFIER CIRCUIT - A circuit includes a conduction detector configured to monitor conduction of a body diode of a synchronous rectifier switch relative to a predetermined threshold and to generate a detector output that indicates conduction or non-conduction of the body diode. A window analyzer is configured to generate a timing signal to indicate if the synchronous rectifier switch is turned off prematurely or turned off late relative to an on-time turn off based on the detector output from the conduction detector. A controller is configured to adjust the timing of the synchronous rectifier switch based on whether the timing signal indicates that the synchronous rectifier switch is turned off prematurely or turned off late relative to the on-time turn off. | 04-16-2015 |
20150100856 | PACKET HEADER PROTECTION FOR UTILITY NETWORKS - A packet header protection system includes, for example, a header checksum (CS) that is arranged to provide error detection capability to FSK (frequency shift keyed) packet headers. Accordingly, receivers in the network can more quickly terminate processing of an errored packet upon detection of error(s) in the header. Quickly detecting packet header errors helps to avoid a sequence of compounding errors such as the repeated transmissions of a packet having an undetected erroneous header. Accordingly, the packet header protection system reduces false alarm rate in the network and increases network throughput. | 04-09-2015 |
20150100812 | SERIAL BUS VOLTAGE COMPENSATION - A serial bus network includes a voltage regulator, a plurality of power switches, and a voltage monitor. The voltage regulator provides power to a plurality of serial buses. Each of the serial buses provides power from the voltage regulator to a device coupled to the serial bus. Each of the power switches switches power from the voltage regulator to one of the serial buses, and includes an input terminal coupled to a voltage regulator output, and an output terminal coupled to one of the serial buses. The voltage monitor is coupled to the voltage regulator and to the output terminal of each of the power switches. The voltage monitor compares bus voltages at the output terminals of the power switches, identifies a lowest of the bus voltages, and adjusts the voltage regulator output voltage such that the identified lowest of the bus voltages is within a predetermined operational voltage range. | 04-09-2015 |
20150100608 | RECONFIGURING AN ASIC AT RUNTIME - Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling. | 04-09-2015 |
20150098569 | Power Line Communication (PLC) Network Nodes Using Cipher Then Segment Security - Embodiments of the invention provide systems and methods for a cipher then segment approach in a Power Line Communication (PLC). A node or device generates frames to be transmitted to a destination node in the PLC network. A processor in the node is configured to generate a data payload comprising data to be sent to the destination node. The processor divides the data payload into two or more payload segments and encrypts the payload segments. The processor creates a frame for each of the encrypted payload segments, wherein each frame comprises a message integrity code. The processor creates a segment identifier for each frame using the message integrity code and an authentication key that is shared with the destination PLC node. The segment identifier is added to each frame. | 04-09-2015 |
20150097608 | SYSTEM AND METHOD FOR CONTROLLING CIRCUIT INPUT-OUTPUT TIMING - An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory. | 04-09-2015 |
20150097577 | CAPACITANCE DETECTION CIRCUIT THAT DETECTS MINUTE CHANGES IN CAPACITANCE - A capacitance detection circuit detects changes in the capacitance of a variable capacitor by using the change in capacitance to change the resonant frequency of a variable capacitor oscillator. The resonant frequency of the variable capacitor oscillator is converted from the time domain to the frequency domain, and then selected frequencies values are compared to known frequency domain values to detect the magnitude of the change in capacitance. | 04-09-2015 |
20150097231 | VERTICAL TRENCH MOSFET DEVICE IN INTEGRATED POWER TECHNOLOGIES - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners. | 04-09-2015 |
20150097230 | TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET - A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions. | 04-09-2015 |
20150097225 | TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET - A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region. | 04-09-2015 |
20150092475 | PSEUDO RETENTION TILL ACCESS MODE ENABLED MEMORY - A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access. | 04-02-2015 |
20150092308 | SCHEME TO REDUCE STRESS OF INPUT/ OUTPUT (IO) DRIVER - An input/output (IO) circuit is provided that reduces stress on a driver without using an additional reference voltage. The IO circuit receives an overshoot voltage and an undershoot voltage in a receive mode. The IO circuit includes a driver circuit. The driver circuit includes an NMOS transistor coupled to a PMOS transistor. A pad is coupled to the driver circuit. A PMOS protect circuit is coupled to the driver circuit and the pad. An NMOS protect circuit is coupled to the driver circuit and the pad. The NMOS protect circuit is configured to be activated only for a duration of the overshoot voltage received at the pad during the receive mode and the PMOS protect circuit is configured to be activated only for a duration of the undershoot voltage received at the pad during the receive mode. | 04-02-2015 |
20150091647 | REDUCING A SETTLING TIME AFTER A SLEW CONDITION IN AN AMPLIFIER - In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A third stage receives the third and fourth line voltages and outputs an output voltage in response thereto. A slew boost circuit detects a slew condition, in which a threshold difference arises between the first and second input voltages, and outputs a slew current in response thereto for maintaining a slew rate of the output voltage during the slew condition. The first stage includes circuits for reducing a variable difference between the first and second line voltages. | 04-02-2015 |
20150091642 | METHOD AND CIRCUITRY FOR MULTI-STAGE AMPLIFICATION - In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A transformer includes first and second coils. A first terminal of the first coil is coupled through a first resistor to the first line. A second terminal of the first coil is coupled through a second resistor to the second line. A first terminal of the second coil is coupled through a third resistor to the third line. A second terminal of the second coil is coupled through a fourth resistor to the fourth line. | 04-02-2015 |
20150091616 | TECHNIQUE TO REALIZE HIGH VOLTAGE IO DRIVER IN A LOW VOLTAGE BICMOS PROCESS - An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit. | 04-02-2015 |
20150091538 | METHOD AND SYSTEM FOR CONVERTING A DC VOLTAGE - An output voltage is compared to a reference voltage, comparison signals are generated, and control signals and mode signals are generated in response thereto. The output voltage is generated in response to the control signals. A speed of the comparing is increased in response to the mode signals indicating that the output voltage is being increased. The speed is reduced in response to the mode signals indicating that the output voltage is being reduced. For increasing the speed, a path is enabled to conduct current. While the path is enabled, at least one switched voltage is connected to vary an amount of the current conducted through the path. The switched voltage is at least one of the reference voltage and the output voltage. For reducing the speed, the path is disabled against conducting current. While the path is disabled, the switched voltage is disconnected from varying the amount. | 04-02-2015 |
20150091502 | SHARED ANTENNA SOLUTION FOR WIRELESS CHARGING AND NEAR FIELD COMMUNICATION - A method of coupling a first port of a single antenna to a first coupling circuit and a second port of the single antenna to a second coupling circuit. The method includes coupling a wireless charging unit to the first coupling unit and coupling an NFC transceiver block to the second coupling circuit. The method further includes isolating the single antenna from the wireless charging unit during a time interval when the NFC transceiver block is operational and isolating the single antenna from the NFC transceiver block during a time interval when the wireless charging unit is operational. | 04-02-2015 |
20150091385 | POWER HARVEST ARCHITECTURE FOR NEAR FIELD COMMUNICATION DEVICES - A method of charging a power harvested supply in an electronic communication device, which can be an NFC (near field communication) device. The power harvested supply in the electronic communication device is charged without causing dV/V violation and avoids false wake up. An RF (radio frequency) field is received at the antenna of the electronic communication device. A differential voltage is generated from the RF field at a first tag pin and a second tag pin of the electronic communication device. A bandgap reference voltage and a reference current are generated in response to the differential voltage. A shunt current is generated in response to the differential voltage and the bandgap reference voltage. A bank of switching devices is activated if the shunt current is more than the reference current. | 04-02-2015 |
20150089289 | PROGRAMMABLE INTERFACE-BASED VALIDATION AND DEBUG - A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human. | 03-26-2015 |
20150088419 | METHOD, SYSTEM AND APPARATUS FOR VEHICULAR NAVIGATION USING INERTIAL SENSORS - According to an aspect of the present disclosure, the relative attitude between an inertial measurement unit (IMU), present on a mobile device, and the frame of reference of the vehicle carrying mobile device is estimated. The estimated relative attitude is used to translate the IMU measurement to the vehicle frame of reference to determine the velocity and position of the vehicle. As a result, the vehicle position and velocity are determined accurately in the event of undocking and re-docking of the mobile device from a docking system in the vehicle. The relative attitude is estimated in terms of pitch, roll, and yaw angles. | 03-26-2015 |
20150087135 | METHOD OF FORMING A TRENCH ISOLATION STRUCTURE USING A SION LAYER - A moat, which is a region of a semiconductor wafer that is laterally surrounded by a trench isolation structure, is protected from damage due to dishing or low spots that result from chemical-mechanical polishing by forming a patterned hard mask structure with an upper silicon oxynitride layer, and performing the polishing with a slurry that includes ceria. | 03-26-2015 |
20150086125 | Adaptive Weighted-Local-Difference Order Statistics Filters - A novel modification to the order statistics filters called the Adaptive Weighted-Local-Difference Order Statistics is shown that will act as a generic framework for the design of adaptive filters suitable for specific signal processing applications. To demonstrate the design of filters using this framework two implementations were defined and evaluated: Edge Orientation Adaptive Weighted-Local-Difference Median Filter (EOAWLDMF) and Luminance-Similarity Adaptive Weighted-Local-Difference Median Filter (LSAWLDMF) for restoration of noisy images. | 03-26-2015 |
20150085901 | CIRCUITS, DEVICES, AND PROCESSES FOR IMPROVED POSITIONING SATELLITE RECEPTION AND OTHER SPREAD SPECTRUM RECEPTION - An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit ( | 03-26-2015 |
20150085725 | POWER EFFICIENT METHOD FOR WI-FI HOME AUTOMATION - A method for automation and control of a wireless device in a WiFi environment. The method includes a wireless mobile device configured with a soft access point (softAP) transmitting probe requests to home automation devices and traditional stationary access points. The wireless mobile device periodically wakes up to scan for other services, sends a probe request, authenticates the received probe response from the another device and receives control information via the received probe response. | 03-26-2015 |
20150084797 | LOW POWER EXCESS LOOP DELAY COMPENSATION TECHNIQUE FOR DELTA-SIGMA MODULATORS - A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier. | 03-26-2015 |
20150079886 | PERMEATED GROOVING IN CMP POLISHING PADS - A polishing pad for polishing a semiconductor wafer or other materials, having grooves in the polishing pad to enhance the usable lifetime of the polishing pad. | 03-19-2015 |
20150079698 | Thermal Treatment for Reducing Transistor Performance Variation in Ferroelectric Memories - Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed. | 03-19-2015 |
20150078198 | SIMPLE MESH NETWORK FOR WIRELESS TRANSCEIVERS - A method of operating a mesh network is disclosed (FIG. | 03-19-2015 |
20150077582 | METHOD AND SYSTEM FOR ADAPTING A DEVICE FOR ENHANCEMENT OF IMAGES - A device stores a list of geographic regions and respective sets of device parameters for achieving target visual characteristics thereof. One of the geographic regions is selected. In response to the selected geographic region's respective set of device parameters, the device automatically adapts for achieving the selected geographic region's target visual characteristics in the device's enhancement of images. At least one of the images is enhanced with the adapted device. | 03-19-2015 |
20150071380 | METHOD AND CIRCUITRY FOR TRANSMITTING DATA - Data transfer devices and methods for transferring data between first and second circuits are disclosed. A data transfer device includes a first circuit having a plurality of data channels, wherein at least one of the data channels is an active data channel. A serializer has a plurality of inputs and an output, wherein the inputs are coupled to the plurality of data channels. The serializer is for coupling only one active channel at a time to the output. An isolation barrier is coupled to the output of the serializer, the isolation attenuates transients and passes the fundamental frequency. A second circuit includes a deserializer having an input and at least one output, the input is coupled to the isolation barrier, the at least one output is at least one active data channel. | 03-12-2015 |
20150070088 | Circuits And Methods For Cancelling Nonlinear Distortions In Pulse Width Modulated Sequences - A method of canceling nonlinear distortions in pulse width modulated signals includes receiving an input signal. A first signal that is the modulated input signal is generated. The first signal has quantized levels representing the input signal. A pulse width modulated (PWM) sequence that is representative of the first signal is generated. A second signal that is the PWM sequence mixed with a carrier signal is generated. An error signal is generated in response to the first signal and modeled from the second signal. The error signal is added to the input signal. | 03-12-2015 |
20150070063 | LOW POWER CLOCK GATED FLIP-FLOPS - A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output. | 03-12-2015 |
20150070061 | DUAL-PORT NEGATIVE LEVEL SENSITIVE RESET PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 03-12-2015 |
20150069942 | Tri-Stating Brushless DC Motor Phase for Direct Detection of Back EMF Zero Cross - A back electromotive force (BEMF) zero cross may be detected in a brushless direct current (BLDC) motor that is controlled by pulse width modulation (PWM). A phase input of the BLDC motor is tri-stated during PWM periods in which the phase input conducts motor drive current, and the tri-stating of the phase input is used to determine whether a BEMF zero cross has occurred in the BLDC motor. | 03-12-2015 |
20150069600 | Embedded Silver Nanomaterials into Die Backside to Enhance Package Performance and Reliability - A method and apparatus for enhancing the electrical and thermal performance of semiconductor packages effectively, especially for laminated packages, where sinterable materials cannot be used. The concept of this invention is to embed silver or silver-coated nanomaterials, which can be nanoparticles, nanoflakes, nanowires etc., into die backside to improve the interface between die and die attach materials, thus enhancing electrical and thermal performance through sintering and enhancing reliability by improving adhesion. | 03-12-2015 |
20150069572 | Multilayer High Voltage Isolation Barrier in an Integrated Circuit - A semiconductor package is provided that has a transformer formed within a multilayer dielectric laminate substrate. The transformer has a first inductor coil formed in one or more dielectric laminate layers of the substrate, a second inductor coil formed in one or more dielectric laminate layers of the substrate, and an isolation barrier comprising two or more dielectric laminate layers of the multilayer substrate positioned between the first inductor coil and the second inductor coil. The transformer may be mounted on a lead frame along with one or more integrated circuits and molded into a packaged isolation device. | 03-12-2015 |
20150069516 | INNER L-SPACER FOR REPLACEMENT GATE FLOW - An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity. | 03-12-2015 |
20150068013 | CURRENT, TEMPERATURE OR ELECTROMAGNETIC FIELD ACTUATED FASTENERS - A method of bonding or debonding objects includes providing a first object including a first substrate with moveable features thereon which provide an actuated and a non-actuated state having different protrusion from the first substrate or a different curvature. A second object has an array of loops thereon. The moveable features while in one of the actuated state and non-actuated state are positioned, sized and shaped to fit within the loops. The moveable features include or are mechanically coupled to a material which responds to application of an actuating condition including electrical current, temperature, or an electromagnetic field by changing between the actuated state and the non-actuated state. Electrical current, temperature, or an electromagnetic field is automatically applied or changed to trigger a state change between the actuated state and non-actuated state that results in a bonding event or a debonding event between the first object and the second object. | 03-12-2015 |
20150067119 | Dynamic Programming and Control of Networked Sensors and Microcontrollers - A network of sensor and controller nodes having the ability to be dynamically programmed and receive updated software from one another, and from a host system. Each network node includes multiple state machines, at least some of which are operable relative to physical pins at the network node; the physical pins correspond to inputs from sensor functions or outputs to control functions. The network nodes include microcontrollers that are operable in an operating mode to execute a state machine and respond to commands from other nodes or the host, and in a read mode to receive and store program instructions transmitted from other nodes or the host. A learn mode is also provided, by way of which a network node can store program code corresponding to instructions and actions at the node when under user control. | 03-05-2015 |
20150066498 | Analog to Information Sound Signature Detection - A low power sound recognition sensor is configured to receive an analog signal that may contain a signature sound. The received analog signal is evaluated using a detection portion of the analog section to determine when background noise on the analog signal is exceeded. A feature extraction portion of the analog section is triggered to extract sparse sound parameter information from the analog signal when the background noise is exceeded. An initial truncated portion of the sound parameter information is compared to a truncated sound parameter database stored locally with the sound recognition sensor to detect when there is a likelihood that the expected sound is being received in the analog signal. A trigger signal is generated to trigger classification logic when the likelihood that the expected sound is being received exceeds a threshold value. | 03-05-2015 |