Altera Corporation Patent applications |
Patent application number | Title | Published |
20160116536 | METHODS AND APPARATUS FOR AUTOMATIC FAULT DETECTION - Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself. | 04-28-2016 |
20160043724 | ROUTING AND PROGRAMMING FOR RESISTIVE SWITCH ARRAYS - Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein. | 02-11-2016 |
20150295579 | System Reset Controller Replacing Individual Asynchronous Resets - An integrated circuit device comprises a system reset controller. The system reset controller includes a clock signal input, a reset signal input, a clock signal output, and a reset signal output. The system reset controller is arranged to receive distributed clock and reset signal inputs and output modified clock and reset signal outputs such that asynchronous reset inputs in downstream system components can be replaced by logic elements not requiring asynchronous reset inputs with no change in externally-visible behavior except the length of reset sequences as measured by clock pulses. | 10-15-2015 |
20150288511 | MULTI-RATE TRANSCEIVER CIRCUITRY - Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit. | 10-08-2015 |
20150281031 | APPARATUS AND METHODS FOR DETERMINING LATENCY OF A NETWORK PORT - One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed. | 10-01-2015 |
20150280558 | INTEGRATED CURRENT REPLICATOR AND METHOD OF OPERATING THE SAME - An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power converter during a complementary portion of the duty cycle and a second transconductance amplifier configured produce a second voltage at the common circuit node proportional to the second input current during the complementary portion of the duty cycle. The integrated current replicator includes an amplifier configured to produce a voltage replicating the first input current and the second input current from the first voltage and the second voltage. | 10-01-2015 |
20150235921 | SILICON-GLASS HYBRID INTERPOSER CIRCUITRY - An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer. The interposer may be used for forming an integrated circuit package. The integrated circuit package includes multiple integrated circuits that are mounted on the interposer. | 08-20-2015 |
20150228506 | METHODS FOR PACKAGING INTEGRATED CIRCUITS - Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package. | 08-13-2015 |
20150214229 | CONFIGURATION BIT ARCHITECTURE FOR PROGRAMMABLE INTEGRATED CIRCUIT DEVICE - An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells. | 07-30-2015 |
20150206965 | HIGH PERFORMANCE FINFET - A FinFET is described having first, second, and third pluralities of fins with gate structures and source and drain regions formed on the fins so that PMOS transistors are formed on the first plurality of fins, NMOS transistors are formed on the second plurality and PMOS transistors are formed on the third plurality. In one embodiment, the first and second pluralities of fins are made of strained silicon; and the third plurality of fins is made of a material such as germanium or silicon germanium that has a higher hole mobility than strained silicon. In a second embodiment, the first plurality of fins is made of silicon, the second plurality of strained silicon, germanium or a III-V compound; and the third plurality is made of germanium or silicon germanium. | 07-23-2015 |
20150205579 | DETERMINISTIC FIFO BUFFER - One embodiment relates to a method for determining a latency of a FIFO buffer. A highest-order bit is provided from FIFO write and read counters to input-comparison logic that distinguishes between the highest-order write and read bits having a same logic level and the highest-order write and read bits having different logic levels. The occupancy level, and hence the latency, of the FIFO buffer is determined based on the output of the input-comparison logic. Another embodiment relates to a FIFO buffer having write and read counters that each have a length in bits that is one bit longer than is needed to address the FIFO buffer. Another embodiment relates to a method of tuning a latency of a FIFO buffer. Other embodiments and features are also disclosed. | 07-23-2015 |
20150200156 | MODULE HAVING MIRROR-SYMMETRIC TERMINALS AND METHODS OF FORMING THE SAME - A module having substantially mirror-symmetric terminals and methods of forming the same. In one embodiment, the module has first and second module terminals and includes a first semiconductor device with first and second terminals in a substantially mirror-symmetric arrangement on the first semiconductor device and coupled to a first common node of the first semiconductor device. The module also includes a second semiconductor device including third and fourth terminals in a substantially mirror-symmetric arrangement on the second semiconductor device and coupled to a second common node of the second semiconductor device. At least one of the first and second terminals is coupled to the first module terminal, and at least one of the third and fourth terminals are coupled to the second module terminal. The first and second module terminals are in a substantially mirror-symmetric arrangement on the module. | 07-16-2015 |
20150200155 | SEMICONDUCTOR DEVICE HAVING MIRROR-SYMMETRIC TERMINALS AND METHODS OF FORMING THE SAME - A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a control element having first and second input nodes and an output node, the first and second input nodes being coupled to first and second input terminals, respectively, of the semiconductor device and the output node being coupled to the control node of the semiconductor switch, the first and second input terminals being substantially center-positioned on the semiconductor device. | 07-16-2015 |
20150154338 | Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 06-04-2015 |
20150149843 | INTEGRATED CIRCUIT WITH A HIGH-SPEED DEBUG ACCESS PORT - An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. The interface circuitry includes a function circuit block that is used to receive a data packet from external circuitry coupled to the integrated circuit. The dedicated debug port is coupled to the function circuit block and is used to transmit the received data packet to debug circuitry on the integrated circuit. The interface circuitry may include a peripheral component interconnect express (PCIe) interface circuit. | 05-28-2015 |
20150127856 | CONFIGURABLE MULTI-LANE SCRAMBLER FOR FLEXIBLE PROTOCOL SUPPORT - Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide. | 05-07-2015 |
20150121319 | METHODS AND TOOLS FOR DESIGNING INTEGRATED CIRCUITS WITH AUTO-PIPELINING CAPABILITIES - A circuit designer may use computer-aided design (CAD) tools to implement an integrated circuit design. The CAD tools may include auto-pipelining capabilities to improve the performance of the integrated circuit design. Auto-pipelining may modify the number of pipeline registers in a path within a given range. A description of the integrated circuit design may include different implementation alternatives of a path each having a different number of pipeline registers, and the CAD tools may select one of these implementation alternatives. The CAD tools may further evaluate the performance of a particular implementation alternative and iteratively select a different implementation alternative until a given objective is met. The CAD tool may update a test environment according to the selected implementation alternative once the objective is met and validate the selected implementation alternative using the updated test environment. | 04-30-2015 |
20150113177 | CIRCUITRY AND TECHNIQUES FOR UPDATING CONFIGURATION DATA IN AN INTEGRATED CIRCUIT - A method of operating an integrated circuit may include receiving an update request via an input-Output protocol, such as the Peripheral Interconnect Component Express (PCIe) protocol. The integrated circuit is placed in an update mode when the update request is received. State information is stored in predefined registers on the integrated circuit and configuration data on the integrated circuit may be subsequently updated. An asserted update mode signal is stored in a status register on the integrated circuit to indicate that the integrated circuit is in the update mode. The configuration data may include a core configuration portion and a peripheral configuration portion. When the integrated circuit is in the update mode, only the core configuration is updated while the peripheral configuration portion may be preserved. | 04-23-2015 |
20150070086 | REGULATOR CIRCUITRY CAPABLE OF TRACKING REFERENCE VOLTAGES - An integrated circuit having a regulator circuit capable of tracking reference voltages is provided. The integrated circuit includes shunt regulator circuitry. The shunt regulator circuitry includes a shunt regulator circuit and a voltage tracking circuit. The shunt regulator circuit has an output on which a regulated voltage is provided. The shunt regulator circuit also provides electrical current to the output when the regulated voltage is outside of a voltage range bounded by first and second reference voltages. The voltage tracking circuit may be coupled to the shunt regulator circuit. The voltage tracking circuit may generate the first and second reference voltages. In one instance, the first voltage is greater than the regulated voltage and the second voltage is less than the regulated voltage. | 03-12-2015 |
20150067010 | FLOATING-POINT ADDER CIRCUITRY - An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent. | 03-05-2015 |
20150052380 | METASTABILITY PREDICTION AND AVOIDANCE IN MEMORY ARBITRATION CIRCUITRY - An integrated circuit with hazard prediction and prevention circuitry is provided. The hazard prediction circuitry may predict a future hazard condition between two periodic signals, and the hazard prevention circuitry may selectively delay at least one of the two periodic signals to avoid the predicted hazard condition. Single-port memory cells may provide multiport memory functionality using an arbitration circuit that includes the hazard prediction and prevention circuitry and receives memory access requests from at least two request generators. The arbitration circuit may operate in synchronous mode and perform port selection based on a predetermined logic table. The arbitration circuit may also operate in asynchronous mode and execute a memory access request as soon as it is received by the arbitration circuit. Metastability caused by receiving memory access requests at the same time from at least two request generators may be avoided with the hazard prediction and prevention circuitry. | 02-19-2015 |
20150039856 | Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture - Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described. | 02-05-2015 |
20150033360 | METHOD AND APPARATUS FOR SECURING CONFIGURATION SCAN CHAINS OF A PROGRAMMABLE DEVICE - Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device. | 01-29-2015 |
20150033075 | CACHE DEBUG SYSTEM FOR PROGRAMMABLE CIRCUITS - An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the system-on-chip interconnects by a bus. A command translator may be interposed in the bus. The command translator may have a slave interface that communicates with the interconnects and a master interface that communicates with the memory coherency control unit. The integrated circuit may have programmable circuitry that is programmed to implement a debug master coupled to the interconnects. During debug operations, the command translator may translate commands from the debug master. | 01-29-2015 |
20150032995 | PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT - Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned. | 01-29-2015 |
20150028918 | ERROR RESILIENT PACKAGED COMPONENTS - A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results. | 01-29-2015 |
20140379307 | Method and Apparatus for Implementing a System-Level Design Tool for Design Planning and Architecture Exploration - A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated. | 12-25-2014 |
20140374877 | Integrated Circuits With On-Die Decoupling Capacitors - An integrated circuit includes a decoupling capacitor and an internal circuit. The decoupling capacitor is coupled to a first external terminal of the integrated circuit. The internal circuit in the integrated circuit is coupled to a second external terminal of the integrated circuit. The decoupling capacitor is coupled to provide supply voltage current to the internal circuit through the first and the second external terminals and through external conductors. The external conductors are outside the integrated circuit. | 12-25-2014 |
20140372654 | BRIDGE CIRCUITRY FOR COMMUNICATIONS WITH DYNAMICALLY RECONFIGURABLE CIRCUITS - A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the second interface without interrupting communications with the dedicated circuitry at the first interface. The variable communications requirements may be dependent on which configuration of the dynamically reconfigurable circuitry is currently implemented. | 12-18-2014 |
20140359297 | Systems and Methods for Intermediate Message Authentication in a Switched-Path Network - Systems, methods, and devices are provided for intermediate authentication of a message transmitted through a switched-path network, such as an optical transport network (OTN). In one method, a message transmitted through communication nodes of a switched-path network may be authenticated, at least partially, by authentication logic of one or more of the communication nodes. The one or more communication nodes may identify whether a prior communication node has tampered with or corrupted the message or may generate an authentication tag to enable an authentication authority to authenticate the message. | 12-04-2014 |
20140359219 | Cache Memory Controller for Accelerated Data Transfer - A cache memory controller in a computer system, such as a multicore processing system, provides compression for writes to memory, such as an off-chip memory, and decompression after reads from memory. Application accelerator processors in the system generate application data and requests to read/write the data from/to memory. The cache memory controller uses information relating location parameters of buffers allocated for application data and sets parameters to configure compression and decompression operations. The cache memory controller monitors memory addresses specified in read requests and write requests from/to the first memory. The requested memory address is compared to the location parameters for the allocated buffers to select the set of parameters for the particular application data. Compression or decompression is applied to the application data in accordance with the selected set of parameters. The data size of the data transferred to/from memory is reduced. | 12-04-2014 |
20140355683 | Data Encoding for Attenuating Image Encoders - A hybrid access encoder includes one or more improvements to attenuation-based image and video encoders using images. The hybrid access encoder supports tradeoffs between encoded bit rate and decoded image and video quality. The hybrid access encoder monitors multiple redundancy removal filters and selects the best-performing filter for encoding. The hybrid access encoder operates in a mode that specifies a target decoded image quality and a target encoded bit rate, giving preference to one metric (image quality or bit rate) when both target values cannot be achieved. The hybrid access encoder performs a plurality of passes across each image and can optimize one or more parameters of the encoder settings between passes. A user interface allows users to control the tradeoff between decoded video quality and battery life for a mobile device. | 12-04-2014 |
20140355665 | Adaptive Video Reference Frame Compression with Control Elements - An access encoder reduces power consumption during video playback and recording by reducing the bandwidth between a processor and a memory. A graphical user interface allows user selection, or software control, over the tradeoff between battery life and video quality. Battery life can be increased (decreased) by activating the access encoder. The access encoder may be implemented in a microprocessor, graphics processor, digital signal processor, FPGA, ASIC, or SoC. The access encoder's encoding/decoding can reduce memory and storage bottlenecks, processor access time, and processor and memory power consumption. A user interface allows users to adjust the tradeoff between decoded video quality and battery life for a mobile device. This abstract does not limit the scope of the invention as described in the claims. | 12-04-2014 |
20140314152 | Methods And Apparatus For Motion Search Refinement In A SIMD Array Processor - Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results. | 10-23-2014 |
20140300818 | EFFICIENT 2D ADAPTIVE NOISE THRESHOLDING FOR VIDEO PROCESSING - Various embodiments of the present disclosure provide techniques for performing video denoising (VDN). An adaptive noise threshold is dynamically determined and used to distinguish between frame to frame differences in pixel values that relate to image motion from those differences that relate to noise. The disclosed techniques enable the noise threshold to be continuously updated, for example as frequently as once per frame, so that the noise threshold may closely track to varying levels of noise in the input video data. The techniques may be implemented in, for example, a video format conversion apparatus. Advantageously, the techniques may be incorporated in programmable logic devices (PLD's) or Field Programmable Gate Arrays (FPGA's) configurable to perform video format conversion, while adding only modest additional computational demands on the apparatus. | 10-09-2014 |
20140281379 | Hybrid Programmable Many-Core Device with On-Chip Interconnect - The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner. | 09-18-2014 |
20140269983 | APPARATUS FOR IMPROVED COMMUNICATION AND ASSOCIATED METHODS - An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link. | 09-18-2014 |
20140269890 | DIGITAL EQUALIZER ADAPTATION USING ON-DIE INSTRUMENT - Systems and methods are provided for adjusting gain of a receiver. Adaptation circuitry is operable to identify, based on a matrix representation of a receiver's output generated from horizontal and vertical sweeps of the receiver's output, an eye opening of the receiver's output. The adaptation circuitry is also operable to determine whether a size of the eye opening needs to be changed. When it is determined that the size of the eye opening needs to be changed, the adaptation circuitry is operable to generate a digital signal to change a gain setting of the receiver. When the signal at the receiver's output is under-equalized, the AC gain of the receiver is increased. When the signal at the receiver's output is over-equalized, the AC gain of the receiver is decreased. | 09-18-2014 |
20140269778 | METHODS TO ACHIEVE ACCURATE TIME STAMP IN IEEE 1588 FOR SYSTEM WITH FEC ENCODER - Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer. | 09-18-2014 |
20140264783 | APPARATUS FOR ELECTRONIC ASSEMBLY WITH IMPROVED INTERCONNECT AND ASSOCIATED METHODS - An apparatus includes a substrate that includes electronic circuitry. The apparatus further includes a first die that includes electronic circuitry, and at least one shielded interconnect. The shielded interconnect(s) couple(s) electronic circuitry in the substrate to electronic circuitry in the first die. | 09-18-2014 |
20140258956 | APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS - A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD. | 09-11-2014 |
20140255028 | SUB-RATE MAPPING FOR LOWEST-ORDER OPTICAL DATA UNIT - One embodiment relates a method for communicating data using an optical transport network. Multiple sub-rate client data signals are received from client sources. The sub-rate client data signals each have a data rate which is less than a data rate capacity of a lowest-order data unit. A predetermined number of tributary slots are provided in the lowest-order optical channel data unit, and each sub-rate client data signal are mapped to at least one of the tributary slots. Another embodiment relates to an optical data communication server that includes a sub-rate mapper for mapping multiple sub-rate client data streams to a predetermined number of tributary slots. Other embodiments and features are also disclosed. | 09-11-2014 |
20140245246 | CONFIGURING A PROGRAMMABLE LOGIC DEVICE USING A CONFIGURATION BIT STREAM WITHOUT PHANTOM BITS - Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits. | 08-28-2014 |
20140245113 | Memory Array with Redundant Bits and Memory Element Voting Circuits - An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells. | 08-28-2014 |
20140239487 | HEAT PIPE IN OVERMOLDED FLIP CHIP PACKAGE - The present invention is an improvement in a molded semiconductor package and the method for its manufacture. The package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, a lid on the molding compound, and a heat pipe extending between the semiconductor die and the lid. Preferably, the heat pipe is formed so that it encircles the die. The package is assembled by mounting the die on the substrate, applying the molding compound to the substrate while a channel is formed in the molding compound adjacent the semiconductor die, inserting a heat pipe material in the channel, and mounting the lid on the molding compound and the heat pipe material. | 08-28-2014 |
20140239483 | HEAT SPREADING IN MOLDED SEMICONDUCTOR PACKAGES - A molded semiconductor package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, and one or more heat conductors in the molding compound that are thermally coupled to the substrate. Advantageously, the heat conductors are mounted in the molding compound near one or more of the corners of the die. The package may also include a lid. The heat conductors produce a more uniform distribution of heat in the substrate. The package is assembled by mounting the die on the substrate, mounting the heat conductors on the substrate and applying the molding compound to the substrate, the die, and the heat conductors mounted on the substrate. For packages that use a lid, the lid is then secured to the package and coupled to the heat conductors. | 08-28-2014 |
20140237441 | Method and Apparatus for Placing and Routing Partial Reconfiguration Modules - A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed. | 08-21-2014 |
20140237215 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 08-21-2014 |
20140223403 | Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 08-07-2014 |
20140223034 | APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. | 08-07-2014 |
20140218221 | Techniques For Alignment of Parallel Signals - Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal. | 08-07-2014 |
20140218068 | HARDENED PROGRAMMABLE DEVICES - Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data. | 08-07-2014 |
20140215180 | ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided. | 07-31-2014 |
20140210515 | PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS - In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block. | 07-31-2014 |
20140210510 | BYPASSABLE CLOCKED STORAGE CIRCUITRY FOR DYNAMIC VOLTAGE-FREQUENCY SCALING - Integrated circuits with sequential logic circuitry are provided. Sequential logic circuitry may include a chain of bypassable clocked storage elements coupled between a speed critical input terminal and a speed critical output terminal. Combinational logic circuits may be interposed between each adjacent pair of bypassable clocked storage elements in the chain. Dynamic voltage-frequency scaling (DVFS) control circuitry may provide an adjustable power supply voltage to the combinational logic circuits and may provide an adjustable clock signal to control the clocked storage elements. The DVFS control circuitry may be used to selectively enable at least some of the bypassable clocked storage elements while disabling other bypassable clocked storage elements so that the power supply voltage can be reduced while maintaining the same operating frequency. The power supply voltage and the frequency of the clock signal can be adjusted to provide the desired voltage-frequency tradeoff. | 07-31-2014 |
20140210097 | INTEGRATED CIRCUIT PACKAGE WITH ACTIVE INTERPOSER - An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal. | 07-31-2014 |
20140201852 | SYSTEMS AND METHODS FOR DETECTING AND MITIGATING PROGRAMMABLE LOGIC DEVICE TAMPERING - Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation. | 07-17-2014 |
20140198810 | METHODS AND APPARATUS FOR ALIGNING CLOCK SIGNALS ON AN INTEGRATED CIRCUIT - A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal. The master clock signal may be adjusted based on the intermediate slave clock signal received at the master transceiver channel to obtain a total adjustment value. The phase of the intermediate slave clock signal may further be adjusted at the slave transceiver channel based on the total adjustment made at the master transceiver channel. | 07-17-2014 |
20140197463 | METAL-PROGRAMMABLE INTEGRATED CIRCUITS - A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure. The multi-gate transistor structures may form one or more fin-shaped field effect transistors. The gate structure may at least partially enclose multiple channel structures. Pairs of source-drain structures may be coupled to the channel structures. The transistor structures of each cell may be formed in a substrate covered with one or more metal interconnect layers. Paths formed in the metal interconnect layers may configure the cells to perform desired logic functions. The paths associated with a given cell may be selectively coupled to transistor structures of the cell to configure the cell for a desired logic function and/or for desired output drive strength. | 07-17-2014 |
20140189622 | PARTITIONING DESIGNS TO FACILITATE CERTIFICATION - This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for partitioning FPGA circuit designs to facilitate certification. In one aspect, a method includes generating a hardware description language (HDL) implementation of a circuit design. The method additionally includes partitioning the design into a first portion and a second portion. In some implementations, the second portion corresponds to a safety-critical portion of the design while the first portion corresponds to a non-safety-critical portion. The method additionally includes generating first configuration settings for the first portion and generating second configuration settings for the second portion. The method additionally includes verifying, or providing to a third-party certification body for verification, the first configuration settings for the first portion and the second configuration settings for the second portion. The method further includes providing the configuration settings for the second portion for programming into a PLD. | 07-03-2014 |
20140189459 | METHOD AND SYSTEM FOR OPERATING A COMMUNICATION CIRCUIT CONFIGURABLE TO SUPPORT ONE OR MORE DATA RATES - A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module. | 07-03-2014 |
20140189456 | 3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION - Techniques and mechanisms are provided for an improved built in self-test (BIST) mechanism for 3D assembly defect detection. According to an embodiment of the present disclosure, the described mechanisms and techniques can function to detect defects in interconnects which vertically connect different layers of a 3D device, as well as to detect defects on a 2D layer of a 3D integrated circuit. Additionally, according to an embodiment of the present disclosure, techniques and mechanisms are provided for determining not only the presence of a defect in a given set of interfaces of an integrated circuit, but the particular interface at which a defect may exist. | 07-03-2014 |
20140181126 | System and Method for Scheduling and Arbitrating Events in Computing and Networking - A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O(1) time. | 06-26-2014 |
20140176188 | HETEROGENEOUS HIGH-SPEED SERIAL INTERFACE SYSTEM ARCHITECTURE - One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed. | 06-26-2014 |
20140175666 | INTEGRATED CIRCUIT DEVICE WITH STITCHED INTERPOSER - Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another. Specifically, the component integrated circuits may communicate through a “stitched silicon interposer” that is larger than a reticle limit of the lithography system used to manufacture the interposer. To achieve this larger size, the stitched silicon interposer may be composed of at least two component interposers, each sized within the reticle limit and each separated from one another by a die seal structure. | 06-26-2014 |
20140173575 | PROCESSORS AND COMPILING METHODS FOR PROCESSORS - A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units ( | 06-19-2014 |
20140173253 | Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution - Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units. | 06-19-2014 |
20140169439 | APPARATUS AND METHODS FOR EQUALIZER ADAPTATION - One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal amplitude. The second average signal amplitude may be an average signal amplitude of a high-frequency portion of the equalized signal. Other embodiments and features are also disclosed. | 06-19-2014 |
20140169074 | MEMORY ELEMENTS WITH STACKED PULL-UP DEVICES - Integrated circuits with memory cells are provided. A memory cell may include first and second cross-coupled inverting circuits configured to store a single data bit. The first inverting circuit may have an output serving as a first data storage node for the memory cell, whereas the second inverting circuit may have an output serving as a second data storage node for the memory cell. Access transistors may be coupled between the first and second data storage nodes and corresponding data lines. Each of the first and second inverting circuit may have a pull-down transistor and at least two pull-up transistors stacked in series. The pull-down transistors may have body terminals that are reverse biased to help reduce leakage current through the first and second inverting circuits. The memory cell may be formed using a narrower two-gate configuration or a wider four-gate configuration. | 06-19-2014 |
20140159157 | ANTENNA DIODE CIRCUITRY AND METHOD OF MANUFACTURE - An integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed within the substrate. The transistor has its gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that it separates the first diffusion region from the second diffusion region. The dummy gate structure may also be coupled to the transistor gate structure. | 06-12-2014 |
20140156703 | METHOD AND APPARATUS FOR TRANSLATING GRAPHICAL SYMBOLS INTO QUERY KEYWORDS - Computer equipment operable to translate a graphical symbol into keywords is disclosed. The computer equipment includes a database of keywords. An input analyzer tool may be used to retrieve a list of keywords from the database based on the graphical symbol. The input analyzer tool may be implemented using processing circuitry that accepts graphical input and performs symbol translation to formulate a search query related to the graphical input. An information search may be performed with the formulated search query using a search engine. | 06-05-2014 |
20140145758 | APPARATUS FOR AUTOMATICALLY CONFIGURED INTERFACE AND ASSOCIATED METHODS - An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value. | 05-29-2014 |
20140145756 | MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS - Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller. | 05-29-2014 |
20140140696 | BIDIRECTIONAL WAVELENGTH CROSS CONNECT ARCHITECTURES USING WAVELENGTH ROUTING ELEMENTS - Bidirectional wavelength cross connects include a plurality of ports, each configured to receive an input optical signals, each input optical signal having a plurality of spectral bands. At least one of the plurality of ports is disposed to simultaneously transmit an output optical signal having at least one of the spectral bands. A plurality of wavelength routing elements are configured to selectively route input optical signal spectral bands to output optical signals. | 05-22-2014 |
20140136905 | Methods for Testing Network Circuitry - A method of operating a test equipment system that is coupled to network circuitry is described. The method displays only selected information. Furthermore, the method may display the selected information in a manner as to allow a user of the test equipment to easily identify errors in the network circuitry. The method may select the information to be displayed by processing received signals according to a stacked protocol hierarchical structure. | 05-15-2014 |
20140133529 | APPARATUS AND METHODS FOR ADAPTIVE RECEIVER DELAY EQUALIZATION - Disclosed are apparatus and methods for adaptive receiver delay equalization. One embodiment relates to a method for adaptive receiver delay equalization. Filtered positive and negative polarity signals are generated by a first variable-delay filter and a second variable-delay filter, respectively. A delay difference is determined between the filtered positive and negative polarity signals, and a skew-indication signal is generated based on the delay difference. A delay control signal is generated based on the skew-indication signal, and the delay control signal is sent to at least one of the first and second variable-delay filters. Other embodiments and features are also disclosed. | 05-15-2014 |
20140126572 | PROGRAMMABLE LOGIC DEVICE WITH INTEGRATED NETWORK-ON-CHIP - Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station. | 05-08-2014 |
20140125379 | SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE - Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block. | 05-08-2014 |
20140122764 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 05-01-2014 |
20140119486 | APPARATUS FOR IMPROVED ENCODING AND ASSOCIATED METHODS - An apparatus includes an encoder adapted to encode data bits for transmission via a communication link using pulse amplitude modulation (PAM). The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length and/or improve the DC balance of the data bits. | 05-01-2014 |
20140119388 | Apparatus for Improved Encoding and Associated Methods - An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits. | 05-01-2014 |
20140118026 | TECHNIQUES AND CIRCUITRY FOR CONFIGURING AND CALIBRATING AN INTEGRATED CIRCUIT - A technique for configuring an integrated circuit includes receiving configuration data from an external element with an interface circuit. The configuration data may include an identification field and an instruction for configuring a logic block. Configuration circuitry may be used to identify the logic block to be configured based on the identification field. A storage element in the identified logic block is configured by the configuration circuitry based on the instruction. | 05-01-2014 |
20140111247 | METHODS AND APPARATUS FOR BUILDING BUS INTERCONNECTION NETWORKS USING PROGRAMMABLE INTERCONNECTION RESOURCES - Integrated circuits may include logic regions configurable to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The logic region may be coupled to input selection circuitry for selecting and providing input signals from the interconnects to the logic regions and to output selection and routing circuitry for selecting and transmitting output signals over interconnects to other logic regions. Bypass circuitry may provide direct access to registers inside the logic regions and to the output selection and routing circuitry by bypassing the input selection circuitry and other processing circuitry inside the logic regions. Bus interconnections having logic regions performing register pipelining, wire stitching, and acting as data source/sink stations to get on and off the bus interconnections may be generated by configuring the bypass circuitry and the output selection and routing circuitry appropriately. | 04-24-2014 |
20140107997 | Simulation Tool for High-Speed Communications Links - A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results. | 04-17-2014 |
20140101410 | METHOD AND SYSTEM FOR MANAGING HARDWARE RESOURCES TO IMPLEMENT SYSTEM FUNCTIONS USING AN ADAPTIVE COMPUTING ARCHITECTURE - An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements. | 04-10-2014 |
20140101409 | 3D MEMORY BASED ADDRESS GENERATOR - Systems and methods are disclosed for reducing memory usage and increasing the throughput in variable-size Fast Fourier Transform (FFT) architectures. In particular, 3D symmetric virtual memory is disclosed to exploit the structure inherent in variable-size FFT computations. Data samples may be written to and read from the 3D symmetric virtual memory in a specific sequence of coordinates that exploits the structure inherent in variable-size FFT computations. Memory locations in the 3D symmetric virtual memory may be mapped to memory address in a 1D buffer using an address generation circuit. | 04-10-2014 |
20140101350 | METHOD FOR FINDING STARTING BIT OF REFERENCE FRAMES FOR AN ALTERNATING-PARITY REFERENCE CHANNEL - The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus. | 04-10-2014 |
20140097544 | Side Stack Interconnection for Integrated Circuits and The Like - In an illustrative embodiment, a plurality of integrated circuits are stacked one on top of the other in a block. A plurality of leads on each integrated circuit is made accessible on a first side of the block. An insulating layer is formed on the first side of the block; electrically conducting vias are formed in the insulating layer and coupled to the leads; a conducting layer is formed on the insulating layer and coupled to the conducting vias; and conducting paths are formed in the conducting layer. Additional layers of insulating layer, conducting vias and conducting layer may be formed on top of the first insulating layer and first conducting layer so as to form more complicated interconnection paths to the leads from the integrated circuits. | 04-10-2014 |
20140089677 | METHOD AND APPARATUS FOR SECURING PROGRAMMING DATA OF A PROGRAMMABLE DEVICE - Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides the required key to the control circuitry. The control circuitry may include decryption circuitry that decrypts the at least partially encrypted configuration data using the required key. In some embodiments, different portions of the configuration data, which may represent separate partial reconfigurations of the device, require different decryption keys. Keys may be generated from combinations of the contents of the key stores. | 03-27-2014 |
20140085967 | MEMORY ELEMENTS WITH RELAY DEVICES - Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity. | 03-27-2014 |
20140082035 | MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters. | 03-20-2014 |
20140077839 | CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES - Clock, distribution circuitry for a structured ASIC device includes a deterministic portion, and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served, from that predetermined, location. | 03-20-2014 |
20140075157 | Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type - Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements. | 03-13-2014 |
20140075081 | Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported. | 03-13-2014 |
20140049287 | MULTIPLE DATA RATE INTERFACE ARCHITECTURE - Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation. | 02-20-2014 |
20140048915 | SHIELDING STRUCTURE FOR TRANSMISSION LINES - A shielding structure for transmission lines comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. The comb-like structures, the planar structures and the first, second, third, and fourth electrically conducting vias are all at substantially the same potential, preferably ground. | 02-20-2014 |
20140047405 | Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices - A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints. | 02-13-2014 |
20140047401 | RECONFIGURABLE LOGIC BLOCK - A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors. | 02-13-2014 |
20140037033 | Techniques for Varying a Periodic Signal Based on Changes in a Data Rate - A circuit includes phase detection, frequency adjustment, sampler, and control circuits. The phase detection circuit compares phases of first and second periodic signals to generate a control signal. The frequency adjustment circuit adjusts a frequency of the second periodic signal and a frequency of a third periodic signal based on the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The control circuit adjusts the frequency of the third periodic signal based on the data signal changing from a first data rate to a second data rate while maintaining the frequency of the second periodic signal constant. The control circuit adjusts the frequency of the second periodic signal and the frequency of the third periodic signal based on the data signal changing from the second data rate to a third data rate. | 02-06-2014 |
20140035642 | Techniques for Aligning and Reducing Skew in Serial Data Signals - A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals. | 02-06-2014 |
20140019500 | METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES - A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values. | 01-16-2014 |
20140015565 | APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. | 01-16-2014 |
20130346953 | OPENCL COMPILATION - Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code. | 12-26-2013 |
20130346925 | INTEGRATED CIRCUIT COMPILATION - Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code. | 12-26-2013 |
20130343466 | Methods And Apparatus For Providing A Scalable Deblocking Filtering Assist Function Within An Array Processor - Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters. | 12-26-2013 |
20130332497 | MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters. | 12-12-2013 |
20130328607 | Apparatus for Using Metastability-Hardened Storage Circuits in Logic Devices and Associated Methods - An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch. | 12-12-2013 |
20130328606 | INTEGRATED CIRCUITS WITH DUAL-EDGE CLOCKING - Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle. | 12-12-2013 |
20130324187 | APPARATUS AND METHOD FOR ADAPTIVE MULTIMEDIA RECEPTION AND TRANSMISSION IN COMMUNICATION ENVIRONMENTS - The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions. | 12-05-2013 |
20130318491 | Method and Apparatus for Performing Parallel Routing Using A Multi-Threaded Routing Procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 11-28-2013 |
20130314122 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 11-28-2013 |
20130311534 | DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION - A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary ( | 11-21-2013 |
20130304960 | Apparatus, System and Method For Configuration of Adaptive Integrated Circuitry Having Fixed, Application Specific Computational Elements - The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes. | 11-14-2013 |
20130283012 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 10-24-2013 |
20130283007 | Methods and Apparatus For Attaching Application Specific Functions Within An Array Processor - A multi-node video signal processor (VSP | 10-24-2013 |
20130263070 | Method and Apparatus For Implementing Periphery Devices On A Programmable Circuit Using Partial Reconfiguration - A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module. | 10-03-2013 |
20130262897 | Power Management of Components Having Clock Processing Circuits - A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a cock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. | 10-03-2013 |
20130227182 | Adaptable Datapath for a Digital Processing System - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided. | 08-29-2013 |
20130226498 | METHODS AND APPARATUS FOR AUTOMATIC FAULT DETECTION - Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself. | 08-29-2013 |
20130214815 | PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS - In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block. | 08-22-2013 |
20130212366 | CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE - A method of configuring a programmable integrated circuit device uses a high-level language. The method includes compiling a plurality of virtual programmable devices from descriptions in the high-level language, describing a user configuration for the programmable integrated circuit device in the high-level language, parsing the user configuration using a programming processor, and selecting, as a result of that parsing, one of the compiled virtual programmable devices. That selected one of the compiled virtual programmable devices is instantiated on the programmable integrated circuit device, and the instantiated one of the compiled virtual programmable devices is configured with the user configuration. | 08-15-2013 |
20130212365 | CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE - A method of preparing a programmable integrated circuit device for configuration using a high-level language includes compiling a plurality of virtual programmable devices from descriptions in said high-level language. The compiling includes compiling configurations of configurable routing resources from programmable resources of said programmable integrated circuit device, and compiling configurations of a plurality of complex function blocks from programmable resources of said programmable integrated circuit device. A machine-readable data storage medium may be encoded with a library of such compiled configurations. A virtual programmable device may include a stall signal network and routing switches of the virtual programmable device may include stall signal inputs and outputs. | 08-15-2013 |
20130207688 | Apparatus and Methods for Time-Multiplex Field-Programmable Gate Arrays - A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design. | 08-15-2013 |
20130182771 | Methods And Apparatus For Motion Search Refinement In A SIMD Array Processor - Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results. | 07-18-2013 |
20130148923 | BIDIRECTIONAL WAVELENGTH CROSS CONNECT ARCHITECTURES USING WAVELENGTH ROUTING ELEMENTS - Bidirectional wavelength cross connects include a plurality of ports, each configured to receive an input optical signals, each input optical signal having a plurality of spectral bands. At least one of the plurality of ports is disposed to simultaneously transmit an output optical signal having at least one of the spectral bands. A plurality of wavelength routing elements are configured to selectively route input optical signal spectral bands to output optical signals. | 06-13-2013 |
20130145074 | LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION IMAGE STORED ON AN INTERNAL READ ONLY MEMORY - Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image. | 06-06-2013 |
20130140640 | N-WELL/P-WELL STRAP STRUCTURES - Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 06-06-2013 |
20130140366 | METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES - A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values. | 06-06-2013 |
20130093482 | CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES - An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation. | 04-18-2013 |
20130061247 | PROCESSOR TO MESSAGE-BASED NETWORK INTERFACE USING SPECULATIVE TECHNIQUES - Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput. | 03-07-2013 |
20130019082 | Manifold Array Processor - An array processor includes processing elements arranged in to form a rectangular array. Inter-cluster communication paths are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port and a single receive port. Thus, the individual PEs are decoupled from the array topology. | 01-17-2013 |
20130014095 | SOFTWARE-TO-HARDWARE COMPILER WITH SYMBOL SET INFERENCE ANALYSIS - A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the programmable logic resources (e.g., RAM). This facilitates multiple reads during a single clock cycle. Symbol set analysis is used to minimize the size of regions to allow for more efficient use of hardware resources. | 01-10-2013 |
20130009666 | FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC - A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner. | 01-10-2013 |
20130007689 | Method and Apparatus For Performing Parallel Routing Using A Multi-Threaded Routing Procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 01-03-2013 |
20130007687 | METHOD AND SYSTEM FOR PARTIAL RECONFIGURATION SIMULATION - Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter. | 01-03-2013 |
20130007679 | RECONFIGURABLE LOGIC BLOCK - A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors. | 01-03-2013 |
20130007421 | Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation - Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used. | 01-03-2013 |
20130007331 | System Core for Transferring Data Between an External Device and Memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified. | 01-03-2013 |
20130006617 | Methods and Apparatus for Efficient Vocoder Implementations - Techniques for implementing vocoders in parallel digital signal processors are described. A preferred approach is implemented in conjunction with the BOPS® Manifold Array (ManArray™) processing architecture so that in an array of N parallel processing elements, N channels of voice communication are processed in parallel. Techniques for forcing vocoder processing of one data-frame to take the same number of cycles are described. Improved throughput and lower clock rates can be achieved. | 01-03-2013 |
20130002295 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 01-03-2013 |
20120331185 | Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported. | 12-27-2012 |
20120319730 | SYSTEMS AND METHODS FOR INTERFACING BETWEEN HARD LOGIC AND SOFT LOGIC IN A HYBRID INTEGRATED DEVICE - Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block. | 12-20-2012 |
20120307878 | MULTI-PROTOCOL MULTIPLE-DATA-RATE AUTO-SPEED NEGOTIATION ARCHITECTURE FOR A DEVICE - An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device. | 12-06-2012 |
20120290819 | DSP BLOCK WITH EMBEDDED FLOATING POINT STRUCTURES - A specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, and configurable interconnect within the specialized processing block for routing signals into and out of each of the first and second floating-point arithmetic operator stages. In some embodiments, the configurable interconnect may be configurable to route a plurality of block inputs to inputs of the first floating-point arithmetic operator stage, at least one of the block inputs to an input of the second floating-point arithmetic operator stage, output of the first floating-point arithmetic operator stage to an input of the second floating-point arithmetic operator stage, at least one of the block inputs to a direct-connect output to another such block, output of the first floating-point arithmetic operator stage to the direct-connect output, and a direct-connect input from another such block to an input of the second floating-point arithmetic operator stage. | 11-15-2012 |
20120286821 | SYSTEMS AND METHODS FOR CONFIGURING AN SOPC WITHOUT A NEED TO USE AN EXTERNAL MEMORY - Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space. | 11-15-2012 |
20120278906 | SYSTEMS AND METHODS FOR DETECTING AND MITIGATING PROGRAMMABLE LOGIC DEVICE TAMPERING - Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation. | 11-01-2012 |
20120278632 | METHOD AND APPARATUS FOR SECURING PROGRAMMING DATA OF A PROGRAMMABLE DEVICE - Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides the required key to the control circuitry. The control circuitry may include decryption circuitry that decrypts the at least partially encrypted configuration data using the required key. In some embodiments, different portions of the configuration data, which may represent separate partial reconfigurations of the device, require different decryption keys. Keys may be generated from combinations of the contents of the key stores. | 11-01-2012 |
20120275077 | SYSTEMS AND METHODS FOR SECURING A PROGRAMMABLE DEVICE AGAINST AN OVER-VOLTAGE ATTACK - Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage. | 11-01-2012 |
20120274359 | HIGH-SPEED DIFFERENTIAL COMPARATOR CIRCUITRY WITH ACCURATELY ADJUSTABLE THRESHOLD - A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit. | 11-01-2012 |
20120274353 | SYSTEMS AND METHODS FOR PREVENTING DATA REMANENCE IN MEMORY SYSTEMS - Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory. | 11-01-2012 |
20120274351 | METHOD AND APPARATUS FOR SECURING A PROGRAMMABLE DEVICE USING A KILL SWITCH - A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD. | 11-01-2012 |
20120274350 | SYSTEMS AND METHODS FOR PROVIDING USER-INITIATED LATCH UP TO DESTROY SRAM DATA - Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased. | 11-01-2012 |
20120263000 | PROGRAMMABLE CONTROL BLOCK FOR DUAL PORT SRAM APPLICATION - A dual-port static random access memory (SRAM) includes a multitude of programmable delay elements disposed along the paths of a number signals used to carry out read, write or read-then-write operations. At least one of the programmable delay elements controls the timing margin between a pair of clock signals that trigger a read/write enable signal. A second programmable delay element coarsely adjusts the delay of a first signal associated with a dummy bitline. A third programmable delay element finely adjusts the delay of a second signal associated with the dummy bitline. A fourth programmable delay element controls the delay of a signal used to reset the read/write enable signal. During a read operation, the voltage level of the second signal is used as an indicator to activate the sense amplifiers. During a write operation, the voltage level of the second signal is used to control the write cycle. | 10-18-2012 |
20120260032 | SYSTEMS AND METHODS FOR USING MEMORY COMMANDS - Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device. | 10-11-2012 |
20120256670 | Techniques for Reducing Duty Cycle Distortion in Periodic Signals - A transmitter circuit is operable to provide an output signal in response to a first periodic signal. A multiplexer circuit is operable to provide a second periodic signal as a selected signal during a first phase of operation. The multiplexer circuit is operable to provide the output signal of the transmitter circuit as the selected signal during a second phase of operation. A sampler circuit is operable to generate first samples of the selected signal during the first phase of operation. The sampler circuit is operable to generate second samples of the selected signal during the second phase of operation. A duty cycle control circuit is operable to adjust a duty cycle of the first periodic signal based on the first and the second samples. | 10-11-2012 |
20120251116 | INTEGRATED OPTICAL-ELECTRONIC INTERFACE IN PROGRAMMABLE INTEGRATED CIRCUIT DEVICE - Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels. | 10-04-2012 |
20120233230 | DOUBLE-CLOCKED SPECIALIZED PROCESSING BLOCK IN AN INTEGRATED CIRCUIT DEVICE - Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products. | 09-13-2012 |
20120229169 | Techniques For Measuring Voltages in a Circuit - A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator. | 09-13-2012 |
20120228760 | SYSTEMS INCLUDING AN I/O STACK AND METHODS FOR FABRICATING SUCH SYSTEMS - Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die. | 09-13-2012 |
20120227026 | Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules - A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed. | 09-06-2012 |
20120217998 | PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS - In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block. | 08-30-2012 |
20120213017 | APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. | 08-23-2012 |
20120173849 | Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism. | 07-05-2012 |
20120146700 | MULTIPLE DATA RATE INTERFACE ARCHITECTURE - Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation. | 06-14-2012 |
20120131535 | Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure - A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box. | 05-24-2012 |
20120131310 | Methods And Apparatus For Independent Processor Node Operations In A SIMD Array Processor - A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem) is associated with each PE and contains local PE instructions for execution on the local PE. Local PE Imem fetch, decode, and execute logic are associated with each PE. Instruction path selection logic in each PE is used to select between control processor distributed instructions and local PE instructions fetched from the local PE Imem. Each PE is also initialized to receive control processor distributed instructions. In addition, local hold generation logic is associated with each PE. A PE receiving a Tstart instruction causes the instruction path selection logic to switch to fetch local PE Imem instructions. | 05-24-2012 |
20120124335 | System Core for Transferring Data Between an External Device and Memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified. | 05-17-2012 |
20120110400 | Method and Apparatus for Performing Memory Interface Calibration - A universal memory interface on an integrated circuit includes an external memory interface unit operable to perform data rate conversion for a data signal between a first rate associated with the integrated circuit and a second rate associated with a memory system. The universal memory interface also includes a sequencer unit operable to calibrate at least one of a delay for the data signal and a delay for a strobe for the data signal by executing a calibration procedure instruction. | 05-03-2012 |
20120106264 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 05-03-2012 |
20120072785 | BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER - An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate. | 03-22-2012 |
20120072756 | Power Management of Components Having Clock Processing Circuits - A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. | 03-22-2012 |
20120063556 | Techniques for Varying a Periodic Signal Based on Changes in a Data Rate - A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The circuit varies a frequency of the third periodic signal to correspond to changes in a data rate of the data signal between at least three different data rates that are based on at least three data transmission protocols. | 03-15-2012 |
20120063539 | LANE-TO-LANE SKEW REDUCTION IN MULTI-CHANNEL, HIGH-SPEED, TRANSCEIVER CIRCUITRY - Controllable delay circuitry is included in each channel of multi-channel, high-speed, serial transmitter and/or receiver circuitry to compensate for or to at least help compensate for possible skew (different signal propagation time) between the various channels. In systems employing CDR circuitry, the delay circuitry may be at least partly controlled by a signal derived from the CDR circuitry to make the amount of delay effected by the delay circuitry at least partly responsive to changes in data rate detected by the CDR circuitry. | 03-15-2012 |
20120060140 | Methods and Apparatus For Single Testing Stimulus - Methods and apparatus useful for improving the performance of testing and diagnostic operations on user circuit designs potentially across multiple phases of the development lifecycle and across multiple implementation technologies are described. As one example, a single testing and diagnostic stimulus source can variously provide test pattern data to different potential instantiations of the user circuit design by supporting and selectively utilizing a number of DUT-facing communication channels. | 03-08-2012 |
20120032276 | N-WELL/P-WELL STRAP STRUCTURES - Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. | 02-09-2012 |
20120011344 | METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES - A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values. | 01-12-2012 |
20110320513 | CALCULATION OF TRIGONOMETRIC FUNCTIONS IN AN INTEGRATED CIRCUIT DEVICE - Circuitry for computing a trigonometric function of an input includes circuitry for relating the input to another value to generate an intermediate value, circuitry for selecting one of the input and the intermediate value as a trigonometric input value, circuitry for determining respective initial values of a plurality of trigonometric functions for the trigonometric input value, and circuitry for deriving, based at least in part on a trigonometric identity, a final value of the first trigonometric function from the respective initial values of the plurality of trigonometric functions. The trigonometric function may be any of sine, cosine and tangent and their inverse functions. The trigonometric identities used allow a computation of a trigonometric function to be broken into pieces that either are easier to perform or can be performed more accurately. | 12-29-2011 |
20110314265 | PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT - Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned. | 12-22-2011 |
20110302333 | Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported. | 12-08-2011 |
20110292950 | Input/Output Interface For Periodic Signals - A first periodic signal generation circuit generates first periodic output signals. A second periodic signal generation circuit generates second periodic output signals. A first multiplexer circuit receives the first and the second periodic output signals. An interface circuit coupled to external pins generates a third periodic output signal based on a periodic signal selected by the first multiplexer circuit. A second multiplexer circuit receives the third periodic output signal at an input. A first periodic feedback signal provided to the first periodic signal generation circuit is based on a signal selected by the second multiplexer circuit. A third multiplexer circuit receives the third periodic output signal at an input. A second periodic feedback signal provided to the second periodic signal generation circuit is based on a signal selected by the third multiplexer circuit. | 12-01-2011 |
20110267106 | LOW-POWER ROUTING MULTIPLEXERS - Low-power routing multiplexers that reduce static and dynamic power consumption are provided. A variety of different techniques are used to reduce power consumption of the routing multiplexers without significantly increasing their size. For example, power consumption of the routing multiplexers may be reduced by reducing short-circuit currents, reducing leakage currents, limiting voltage swing, and recycling charge within the multiplexer. Multiple power reduction techniques may be combined into a single routing multiplexer design. Low-power routing multiplexers may also be designed to operate in selectable modes, such as, a high-speed, high-power mode and a low-speed, low-power mode. | 11-03-2011 |
20110260751 | MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE - The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks. | 10-27-2011 |
20110238720 | SOLVING LINEAR MATRICES IN AN INTEGRATED CIRCUIT DEVICE - Circuitry for solving linear matrix equations involving a resultant matrix, an unknown matrix and a product matrix that is a product of the resultant matrix and the unknown matrix includes matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below the resultant matrix elements on the diagonal. The matrix decomposition circuitry includes an inverse square root multiplication path that computes diagonal elements of the resultant matrix having an inverse square root module, and the said inverse square root module computes inverses of the diagonal elements to be used in multiplication in place of division by a diagonal element. Latency is hidden by operating on each nth row of a plurality of matrices prior to any (n+1)th row. | 09-29-2011 |
20110238718 | LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS - A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out. | 09-29-2011 |
20110235756 | SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE - A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated. | 09-29-2011 |
20110227606 | PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 09-22-2011 |
20110225396 | Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution - Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units. | 09-15-2011 |
20110225392 | Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported. | 09-15-2011 |
20110225224 | Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture - Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described. | 09-15-2011 |
20110219210 | System Core for Transferring Data Between an External Device and Memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified. | 09-08-2011 |
20110219052 | DISCRETE FOURIER TRANSFORM IN AN INTEGRATED CIRCUIT DEVICE - Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets. | 09-08-2011 |
20110213952 | Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File - A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports. | 09-01-2011 |
20110213937 | Methods and Apparatus for Address Translation Functions - Techniques are described for efficient reordering of data and performing data exchanges within a register tile or memory, or in general, any device storing data that is accessible through a set of addressable locations. In one technique, an address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable and selectable means of translating the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power. Address translation functions are shown to be useful for vector operations and a new type of storage unit using built in address translation functions is presented. | 09-01-2011 |
20110211621 | HETEROGENEOUS TRANSCEIVER ARCHITECTURE FOR WIDE RANGE PROGRAMMABILITY OF PROGRAMMABLE LOGIC DEVICES - High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates. | 09-01-2011 |
20110204924 | Techniques For Measuring Voltages in a Circuit - A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator. | 08-25-2011 |
20110204476 | Electronic Package with Fluid Flow Barriers - The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region. | 08-25-2011 |
20110188564 | DIGITAL ADAPTATION CIRCUITRY AND METHODS FOR PROGRAMMABLE LOGIC DEVICES - Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal. | 08-04-2011 |
20110172983 | METHOD FOR INCORPORATING PATTERN DEPENDENT EFFECTS IN CIRCUIT SIMULATIONS - Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics. | 07-14-2011 |
20110161389 | LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE - A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. | 06-30-2011 |
20110153998 | Methods and Apparatus for Attaching Application Specific Functions Within an Array Processor - A multi-node video signal processor (VSP | 06-23-2011 |