SPANSION LLC Patent applications |
Patent application number | Title | Published |
20160134103 | PROTECTING CIRCUIT AND INTEGRATED CIRCUIT - A protecting circuit includes: a discharge switch configured to connect to a first terminal and a second terminal; a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal, each of the load devices being configured to consume power; and a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, at least one shunt pathway configured to be capable of bypassing at least one of the load devices. The trigger circuit is configured to turn on the discharge switch when a voltage between the first terminal and the second terminal is higher than a first voltage value, and the shunt circuit is configured to electrically connect the shunt pathway when the voltage is higher than a second voltage value that is greater than the first voltage value. | 05-12-2016 |
20160126250 | CHARGE-TRAPPING MEMORY DEVICE - A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region. | 05-05-2016 |
20160111166 | Simultaneous Programming of Many Bits in Flash Memory - A semiconductor device includes: a plurality of memory cells; a plurality of local bit lines connected to respective memory cells of the plurality of memory cells; and a first amplifier. The first amplifier receives read data from each local bit line of the plurality of local bit lines and determines a transition speed of an output level of the first amplifier in response to receiving a combination of at least two pieces of read data. The first amplifier transfers, based on the determined transition speed, multivalued data of the read data to a read global bit line. | 04-21-2016 |
20160110282 | OVERLAID ERASE BLOCK MAPPING - An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information. | 04-21-2016 |
20160103723 | SYSTEM-ON-CHIP VERIFICATION - Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals. During the hardware verification process, the AIC configures at least one of the communication protocols to enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a register-transfer level model is used for a least one of the plurality of peripherals. The AIC may further configure at least one of the communication protocols to enforce one or more constraints on the transactions to achieve increased hardware verification coverage. | 04-14-2016 |
20160056816 | SWITCHING CIRCUIT - A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The switching circuit further includes a gate voltage generating circuit configured to switch voltage applied to the gate of the PLDMOS between a first voltage and a second voltage, wherein the first voltage is substantially the same as an input voltage from the converting circuit, and wherein a difference between the first voltage and the second voltage is lower than the gate-source breakdown voltage of the PLDMOS. | 02-25-2016 |
20160049416 | INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS - A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing. | 02-18-2016 |
20160036383 | CRYSTAL OSCILLATION CIRCUIT - A crystal oscillation circuit is provided with a crystal oscillator, an inverter unit coupled in parallel with the crystal oscillator and including a plurality of inverters, a current supply unit that supplies current to at least a first inverter of the plurality of inverters a signal converter that supplies current to at least a last inverter of the plurality of inverters and outputs a voltage to an external circuit, and a current controller that makes the current supply unit provide current corresponding to a voltage level of the output voltage of the signal converter. The crystal oscillation circuit is capable of reducing power consumption. | 02-04-2016 |
20160036332 | CONTROL APPARATUS, BUCK-BOOST POWER SUPPLY AND CONTROL METHOD - A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are N-type transistors without changing the switching frequency are provided. A control apparatus for a buck-boost power supply comprises: a pulse-width modulation (PWM) signal generator configured to generate a PWM signal having a pulse whose pulse width is based on an output voltage; a mode pulse signal generator configured to generate a mode pulse signal having a signal whose time period is based on at least one of an input voltage, a difference between an input voltage and the output voltage, and a difference between an input voltage and a voltage proportional to the output voltage; a first delayed signal generator configured to generate a first delayed signal having a pulse whose rising edge or falling edge is delayed for a first delay time from a rising edge or a falling edge of the pulse of the PWM signal; and an output controller configured to control an output part of the buck-boost power supply, based on the PWM signal, the mode pulse signal, and the first delayed signal, the output part comprising: two primary switches that are each an N-type transistor; a boost capacitor for driving the high-side switch of the primary switches; and two secondary switches that are each a transistor, wherein the output controller controls switching of the output part so that a first time period during which the high-side switch of the primary switches is off and the low-side switch of the primary switches is on is longer than or equal to the first delay time. | 02-04-2016 |
20160026593 | DETECTING THE DRIFT OF THE DATA VALID WINDOW IN A TRANSACTION - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for detecting the drift of the data valid window in a transaction. An embodiment operates by configuring a data capture range comprising data capture points, measuring values of a signal at the data capture points, and detecting the drift of the data valid window based on the values at the data capture points. | 01-28-2016 |
20150378882 | BOOTING AN APPLICATION FROM MULTIPLE MEMORIES - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for booting an application from multiple memories. An embodiment operates by executing in place from a first memory a first portion of the application, loading a second portion of the application from a second memory, and executing the second portion of the application. | 12-31-2015 |
20150341034 | Methods, Circuits, Devices and Systems for Integrated Circuit Voltage Level Shifting - Disclosed is an integrated circuit voltage level shifter including: a first set of pull-up transistors to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on the input and a third set of transistors to limit current flow through the second set of pull-down transistors and to mitigate snapback of the second set of pull-down transistors using a bias gate voltage. | 11-26-2015 |
20150341023 | Methods, Circuits, Devices and Systems for Comparing Signals - Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path. | 11-26-2015 |
20150340098 | METHODS, CIRCUITS, DEVICES AND SYSTEMS FOR SENSING AN NVM CELL - Disclosed is a non-volatile memory (NVM) device including an array of NVM cells segmented into at least a first sector and a second sector and at least one sensing circuit to sense a state of a target NVM cell in the first sector using a reference current of the second sector received from at least a dynamic reference cell. | 11-26-2015 |
20150333188 | TILTED IMPLANT FOR POLY RESISTORS - A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor. | 11-19-2015 |
20150262838 | Buried Trench Isolation in Integrated Circuits - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed. | 09-17-2015 |
20150255480 | Method to Improve Charge Trap Flash Memory Top Oxide Quality - A semiconductor processing method to provide a high quality top oxide layer in charged-trapping NAND and NOR flash memory. The top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method described overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride. | 09-10-2015 |
20150253988 | Memory Access Bases on Erase Cycle Time - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality Of indicators for the memory block. The indicator is saved and later retrieved during a read operation. | 09-10-2015 |
20150242129 | MEMORY SUBSYSTEM WITH WRAPPED-TO-CONTINUOUS READ - Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area. | 08-27-2015 |
20150194537 | MULTI-LAYER INTER-GATE DIELECTRIC STRUCTURE - A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second gate conductor can be formed over a second gate dielectric structure, adjacent to the inter-gate dielectric structure. A dielectric layer can be formed over the substrate, the first and second gate conductors, and the inter-gate dielectric structure. The first gate conductor may be used to make a memory gate and the second gate conductor can be used to make a select gate of a split-gate memory cell. | 07-09-2015 |
20150187891 | Formation of Gate Sidewall Structure - A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate. | 07-02-2015 |
20150179817 | Gate Formation Memory by Planarization - Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization. | 06-25-2015 |
20150179656 | CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE - Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines. | 06-25-2015 |
20150162226 | Forming Charge Trap Separation in a Flash Memory Semiconductor Device - During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process. | 06-11-2015 |
20150155162 | Reduction of Charging Induced Damage in Photolithography Wet Process - An approach is developed to use an acidic rinse to reduce charge during the lithographic process, and thereby eliminate the crystalline damage and associated yield loss associated with the accumulated charge. The crystalline damage has been found to occur for certain thicknesses of dielectric layers, and such damage is irreparable. A sparge can be used to dissolve carbon dioxide in water to provide a weak acidic rinse. | 06-04-2015 |
20150154953 | GENERATION OF WAKE-UP WORDS - A method, system and tangible computer readable medium for generating one or more wake-up words are provided. For example, the method can include receiving a text representation of the one or more wake-up words. A strength of the text representation of the one or more wake-up words can be determined based on one or more static measures. The method can also include receiving an audio representation of the one or more wake-up words. A strength of the audio representation of the one or more wake-up words can be determined based on one or more dynamic measures. Feedback on the one or more wake-up words is provided (e.g., to an end user) based on the strengths of the text and audio representations. | 06-04-2015 |
20150149696 | Auto Resume of Irregular Erase Stoppage of a Memory Sector - Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed. | 05-28-2015 |
20150130430 | Output Switching Circuit - An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal. | 05-14-2015 |
20150128011 | METHODS, CIRCUITS, SYSTEMS AND COMPUTER EXECUTABLE INSTRUCTION SETS FOR PROVIDING ERROR CORRECTION OF STORED DATA AND DATA STORAGE DEVICES UTILIZING SAME - Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error. | 05-07-2015 |
20150109594 | Multiple Phase-Shift Photomask and Semiconductor Manufacturing Method - Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device may be raised or lowered relative to other areas of the semiconductor device. Therefore, focusing the light on one area causes another to become unfocused. By carefully designing a photomask to cause phase shifts of the light transmitted therethrough, focus across all areas of the semiconductor device can be achieved during photolithography, which results in sharp and accurate patterns formed on the semiconductor device. | 04-23-2015 |
20150108562 | Three-Dimensional Charge Trapping NAND Cell with Discrete Charge Trapping Film - A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell. | 04-23-2015 |
20150106664 | METHOD FOR PROVIDING READ DATA FLOW CONTROL OR ERROR REPORTING USING A READ DATA STROBE - Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. If the read data strobe signal is not received before expiration of a predetermined maximum latency time, the peripheral controller is indicating a read data error back to the host. | 04-16-2015 |
20150106662 | MEMORY PROGRAM UPON SYSTEM FAILURE - A system and method for programming a memory device with debug data upon a system failure is disclosed herein. For example, the system can include a timer device, a buffer, a register, and a memory device. The buffer can be configured to receive debug data. The register can be configured to receive memory address information. Also, the memory device can be configured to store the debug data from the buffer at a memory address corresponding to the memory address information when a timer value of the timer device reaches zero. Further, the system can include a processing unit configured to provide the timer value to the timer device and the memory address information to the register. | 04-16-2015 |
20150106405 | HIDDEN MARKOV MODEL PROCESSING ENGINE - A method, apparatus, and tangible computer readable medium for processing a Hidden Markov Model (HMM) structure are disclosed herein. For example, the method includes receiving Hidden Markov Model (HMM) information from an external system. The method also includes processing back pointer data and first HMM states scores for one or more NULL states in the HMM information. Second HMM state scores are processed for one or more non-NULL states in the HMM information based on at least one predecessor state. Further, the method includes transferring the second HMM state scores to the external system. | 04-16-2015 |
20150103601 | MULTI-PASS SOFT PROGRAMMING - Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification. | 04-16-2015 |
20150102430 | Spacer Formation with Straight Sidewall - Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device. | 04-16-2015 |
20150102400 | ION IMPLANTATION-ASSISTED ETCH-BACK PROCESS FOR IMPROVING SPACER SHAPE AND SPACER WIDTH CONTROL - Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion that is substantially perpendicular to the substrate. Further, disclosed herein, are methods associated with the fabrication of the aforementioned semiconductor device. | 04-16-2015 |
20150098290 | METHODS CIRCUITS APPARATUSES AND SYSTEMS FOR PROVIDING CURRENT TO A NON-VOLATILE MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICES PRODUCED ACCORDINGLY - Disclosed are methods, circuits, apparatuses and systems for providing power to a dynamic load such as a non-volatile memory array. According to embodiments, a voltage source may be adapted to generate and output a supply current at substantially a target voltage through a regulating transistor whose channel is in series between an output terminal of said charge pump and an input terminal of said NVM array. A discharge circuit branch coupled to an output terminal of the regulating transistor may be adapted to drain away current from the regulating transistor output terminal when a voltage at the regulating transistor output terminal exceeds a first defined threshold voltage. A bulk regulating circuit branch coupled to a bulk of the regulating transistor may be adapted to reduce a bulk-voltage of the regulating transistor when a voltage at the regulating transistor output terminal exceeds a defined threshold voltage. | 04-09-2015 |
20150097245 | SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC. | 04-09-2015 |
20150097224 | BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS - A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is positioned between first and second devices and comprises a first filled portion and a second filled portion. The first filled portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. | 04-09-2015 |
20150091138 | Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device - A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area, however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area, allowing the die seal area to be disregarded for purposes of calculating a process window. | 04-02-2015 |
20150056726 | CHIP POSITIONING IN MULTI-CHIP PACKAGE - Embodiments of the present invention include a method for multi-chip packaging. For example, the method includes positioning a first integrated circuit (IC) on a substrate package based on a first set of reference markers in physical contact with the substrate package and confirming an alignment of the first IC based on a second set of reference markers in physical contact with the substrate package. A second IC is stacked onto first IC based on the first set of reference markers. An alignment of the second IC is confirmed based on the second set of reference markers, where the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers. | 02-26-2015 |
20150054554 | APPARATUS AND METHOD FOR SMART VCC TRIP POINT DESIGN FOR TESTABILITY - An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped. | 02-26-2015 |
20140370698 | Non-Volatile Finfet Memory Array and Manufacturing Method Thereof - An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device. the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction. | 12-18-2014 |
20140351485 | Differential File System for Computer Memory - An approach is described to overcome the rapid consumption of available flash space when frequently modifying files stored on the flash space. This “differential” sector approach determines the correlation between the new content and the old content, and saves only the “delta” part of the old and the new content to the sectorized memory device. A predetermined threshold can be used to determine whether to use the “differential” sector approach or the fixed sector approach, based on the amount of data change in a given memory access request. | 11-27-2014 |
20140312465 | Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device - A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area allowing the die seal area to he disregarded for purposes of calculating a process window. | 10-23-2014 |
20140312409 | SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY - A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process. | 10-23-2014 |
20140312408 | CHARGE-TRAP NOR WITH SILICON-RICH NITRIDE AS A CHARGE TRAP LAYER - A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT-NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device. | 10-23-2014 |
20140306752 | DC-DC Converter With Adaptive Phase Compensation Controller - A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage determined by the output voltage plus said phase compensation component. | 10-16-2014 |
20140304205 | COMBINING OF RESULTS FROM MULTIPLE DECODERS - Embodiments include a method, apparatus, and a computer program product for combining results from multiple decoders. For example, the method can include generating a network of paths based on one or more outputs associated with each of the multiple decoders. The network of paths can be scored to find an initial path with the highest path score based on scores associated with the one or more outputs. A weighting factor can be calculated for each of the multiple decoders based on a number of outputs from each of the multiple decoders included in the initial path with the highest path score. Further, the network of paths can be re-scored to find a new path with the highest path score based on the scores associated with the one or more outputs and the weighting factor for each of the multiple decoders. | 10-09-2014 |
20140303983 | AUTHENTICATION FOR RECOGNITION SYSTEMS - Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device. | 10-09-2014 |
20140301146 | MODIFIED LOCAL SEGMENTED SELF-BOOSTING OF MEMORY CELL CHANNELS - A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level. | 10-09-2014 |
20140289443 | Inter-Bus Communication Interface Device - There is provided an inter-bus communication interface device capable of efficiently performing transfer of data between a plurality of devices connected to different buses, respectively. When communication data is transmitted, a first device writes the communication data into a buffer, whereas when communication control information is transmitted, the first device writes the communication control information into a register. A control circuit passes the communication data stored in the buffer to a second device, and passes the communication control information stored in the register to a second device. | 09-25-2014 |
20140286330 | Node System and Supervisory Node - A node system includes a first node, a second node, and a supervisory node which transmit frames while increasing or decreasing the cycle microtick count, and determines reduced cycle microtick counts by subtracting or adding a rate correction limit value from or to the cycle microtick count of the supervisory node when reception of the first frame transmitted by the first node stop and the cycle microtick count of the supervisory node when reception of the first and second frames stop. | 09-25-2014 |
20140256088 | SEMICONDUCTOR DEVICE HAVING CHIP MOUNTED ON AN INTERPOSER - A semiconductor device | 09-11-2014 |
20140254288 | Pipelining in a Memory - A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array. | 09-11-2014 |
20140244914 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-28-2014 |
20140235106 | CONTACT CONFIGURATION FOR UNDERTAKING TESTS ON CIRCUIT BOARD - An electronic structure (for example a reliability board or a cycling control module) has a body including a body portion insertable into a connector. A plurality of contact structures are provided on a side of the body portion, each contact structure comprising a first contact and a second contact spaced from the first contact, with the first and second contacts of each contact structure being aligned in the direction of insertion of the body portion into the connector. A corresponding second plurality of contact structures is provided on a side of the body portion opposite the first—mentioned side. These contacts connect with respective corresponding contacts of the connector. | 08-21-2014 |
20140233339 | APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS - A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line. | 08-21-2014 |
20140223054 | MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS - A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures. | 08-07-2014 |
20140219035 | SEMICONDUCTOR MEMORY DEVICE - Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in. | 08-07-2014 |
20140219018 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits. | 08-07-2014 |
20140215111 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer. | 07-31-2014 |
20140210012 | Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions - Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing. | 07-31-2014 |
20140209993 | Non-Volatile Memory With Silicided Bit Line Contacts - An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes. | 07-31-2014 |
20140209991 | CONVEX SHAPED THIN-FILM TRANSISTOR DEVICE - The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed. | 07-31-2014 |
20140208554 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened. | 07-31-2014 |
20140203792 | Control Circuit of Step-Down DC-DC Converter, Control Circuit of Step-Up DC-DC Converter and Step-Up/Step-Down DC-DC Converter - A DC-DC converter or the like capable of generating a stable output voltage is provided. A control circuit | 07-24-2014 |
20140203263 | SWITCHABLE MEMORY DIODES BASED ON FERROELECTRIC/CONUUGATED POLYMER HETEROSTRUCTURES AND/OR THEIR COMPOSITES - An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material. The layers are provided between first and electrodes. In another embodiment, a single layer of a composite of conjugated semiconductor polymer and ferroelectric semiconductor material is provided between first and second electrodes. The various embodiments may be part of a memory array. | 07-24-2014 |
20140201403 | DEBUG CONTROL CIRCUIT - An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation. | 07-17-2014 |
20140195233 | Distributed Speech Recognition System - Embodiments of the present invention include an apparatus, method, and system for speech recognition of a voice command. The method can include receiving data representing a voice command, generating a list of targets based on the state information of each target within the system, and selecting a target from the list of targets, based on the voice command. | 07-10-2014 |
20140193972 | Buried Hard Mask for Embedded Semiconductor Device Patterning - Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed. | 07-10-2014 |
20140192581 | PROGRAMMABLE AND FLEXIBLE REFERENCE CELL SELECTION METHOD FOR MEMORY DEVICES - Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells. | 07-10-2014 |
20140191417 | Multi-Chip Package Assembly with Improved Bond Wire Separation - A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances. | 07-10-2014 |
20140191308 | SELF-ALIGNED DOUBLE PATTERNING FOR MEMORY AND OTHER MICROELECTRONIC DEVICES - A semiconductor device is provided. The semiconductor device includes a microelectronic layer, a first mask layer formed on the microelectronic layer having first features separated by first openings, and a second mask layer formed on the first mask layer having second features that are separated by second openings. Each second feature is centrally located on a respective one of the first features. A length each second feature in a dimension is substantially equal to a length of a respective one of the first openings in the dimension. | 07-10-2014 |
20140185393 | DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT - A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses. | 07-03-2014 |
20140180694 | Phoneme Score Accelerator - Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs and HMM state scores. The HMM module is configured to traverse the HMM based on the senone scores and the HMM information. Further, the interface module is configured to transfer one or more HMM scoring requests from the external computing device to the HMM module and to transfer the HMM state scores to the external computing device. | 06-26-2014 |
20140180693 | Histogram Based Pre-Pruning Scheme for Active HMMS - Embodiments of the present invention include an acoustic processing device, a method for acoustic signal processing, and a speech recognition system. The speech processing device can include a processing unit, a histogram pruning unit, and a pre-pruning unit. The processing unit is configured to calculate one or more Hidden Markov Model (HMM) pruning thresholds. The histogram pruning unit is configured to prune one or more HMM states to generate one or more active HMM states. The pruning is based on the one or more pruning thresholds. The pre-pruning unit is configured to prune the one or more active HMM states based on an adjustable pre-pruning threshold. Further, the adjustable pre-pruning threshold is based on the one or more pruning thresholds. | 06-26-2014 |
20140180690 | Hybrid Hashing Scheme for Active HMMS - Embodiments of the present invention include a data storage device and a method for storing data in a hash table. The data storage device can include a first memory device, a second memory device, and a processing device. The first memory device is configured to store one or more data elements. The second memory device is configured to store one or more status bits at one or more respective table indices. In addition, each of the table indices is mapped to a corresponding table index in the first memory device. The processing device is configured to calculate one or more hash values based on the one or more data elements. | 06-26-2014 |
20140177375 | Memory Device with Internal Combination Logic - Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic. | 06-26-2014 |
20140175613 | Chip Positioning in Multi-Chip Package - Embodiments of the present invention include a substrate package, a method for multi chip packaging, and a multi-chip package. For example, the substrate package includes a first set of reference markers and a second set of reference markers. The first set of reference markers is disposed on the substrate package, where the first set of reference markers is configured to provide a first alignment for positioning a first integrated circuit (IC) and a second alignment for positioning a second IC on the substrate package. Further, the second set of reference markers is disposed at a different location on the substrate package than the first set of reference markers, where the second set of reference markers is configured to provide confirmation of the first alignment and the second alignment. | 06-26-2014 |
20140170843 | Charge Trapping Split Gate Device and Method of Fabricating Same - Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device. | 06-19-2014 |
20140167220 | THREE DIMENSIONAL CAPACITOR - Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application. | 06-19-2014 |
20140167211 | METHOD FOR AMNUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method. | 06-19-2014 |
20140167142 | Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells - A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate. | 06-19-2014 |
20140167141 | Charge Trapping Split Gate Embedded Flash Memory and Associated Methods - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different. | 06-19-2014 |
20140167140 | Memory First Process Flow and Device - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer. | 06-19-2014 |
20140167139 | Integrated Circuits With Non-Volatile Memory and Methods for Manufacture - Semiconductor devices and the manufacture of such semiconductor devices are described. According to various aspects of the disclosure, a semiconductor device can include a memory region, a first logic region, and a second logic region. A select gate can be formed in the memory region of the device and a first logic gate formed in the logic region. A charge trapping dielectric can then be disposed and removed from a second logic region. A gate conductor layer can then be disposed on the device and etched to define a memory gate on the sidewall of the select gate and a second logic gate in the second logic region. | 06-19-2014 |
20140167138 | HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions. | 06-19-2014 |
20140167137 | High Voltage Gate Formation - Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an approach is that a thin poly layer may be used to form memory and low voltage gates while protecting high voltage gates from implant penetration. One approach to accomplishing this is to dispose the layer of poly, and then dispose a mask and a thick resist to pattern the high voltage gates. In this manner, the high voltage gates are formed before either the low voltage gates or the memory cells. | 06-19-2014 |
20140167136 | Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation - Embodiments described herein generally relate to charge-trapping memory with improved isolation between a select gate and a memory gate. The isolation is improved because the charge trapping layer is not present in the junction between the select gate and the memory gate. The methods described herein additionally allow insulation to be disposed between the select gate and the memory gate. | 06-19-2014 |
20140167135 | Process Charging Protection for Split Gate Charge Trapping Flash - A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions. | 06-19-2014 |
20140167128 | Memory Gate Landing Pad Made From Dummy Features - Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact. | 06-19-2014 |
20140165217 | AUTHENTICATED MEMORY AND CONTROLLER SLAVE - Systems and methods that can facilitate the utilization of a memory as a slave to a host are presented. The host and memory can provide authentication information to each other and respective rights can be granted based in part on the respective authentication information. The host can determine the available functionality of the memory. The host can activate the desired functionality in the memory and can request memory to perform the desired function(s) with regard to data stored in the memory. An optimized controller component in the memory can facilitate performing the desired function(s) associated with the data to generate a result. The result can be provided to the host, while the data and associated information utilized to generate the result can remain in the memory and are cannot be accessed by the host. | 06-12-2014 |
20140159138 | GATE FRINGINE EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. | 06-12-2014 |
20140153589 | SIGNAL PROCESSOR AND COMMUNICATION DEVICE - A signal processor includes a period detection section which detects that a period is currently used for communication of a frame; a pattern detection section which detects, from the received signal, a first signal pattern by which the end of communication of the frame is recognized; and an output processing section which outputs the received signal to a controller; configured to instruct, upon detection of the first signal pattern in the period being currently used for communication of a frame, the controller to halt startup of communication action of the next frame, until the period being currently used for communication of a frame comes to the end, to thereby reduce an event such that frames are transmitted from a plurality of communication devices simultaneously, and to thereby allow the communication action for the next frame to proceed correctly. | 06-05-2014 |
20140151887 | Memory Device Interconnects and Method of Manufacture - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes. | 06-05-2014 |
20140148010 | Forming Charge Trap Separation in a Flash Memory Semiconductor Device - During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process. | 05-29-2014 |
20140148009 | Forming a Substantially Uniform Wing Height Among Elements in a Charge Trap Semiconductor Device - During formation of a charge trap separation in a semiconductor device, an organic material is formed over a plurality of cells. This organic material is selectively removed in order to create a flat upper surface. An etching process is performed to remove the organic material as well as a charge trap layer formed over the plurality of cells, thereby exposing underlying first oxide layers in each of the cells and forming charge trap separation. Further, because of the selective removal step, the etch results in substantially uniform wing heights among the separated cells. | 05-29-2014 |
20140148001 | NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers. | 05-29-2014 |
20140146606 | PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY - Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories. | 05-29-2014 |
20140145337 | Memory Device Interconnects and Method of Manufacture - An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines extend through the first inter-level dielectric layer. Each of a plurality of source line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines. Each of the plurality of staggered bit line contacts extend through the first and second inter-level dielectric layes to respective bit lines. | 05-29-2014 |
20140143473 | DATA REFRESH IN NON-VOLATILE MEMORY - A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small. | 05-22-2014 |
20140141591 | Method to Improve Charge Trap Flash Memory Core Cell Performance and Reliability - A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride. | 05-22-2014 |
20140138790 | Inter-Layer Insulator for Electronic Devices and Apparatus for Forming Same - A semiconducting device utilizing air-gaps for inter-layer insulation and methods of producing the device are described. The device may be produced by forming a sacrificial layer between two structures. A porous membrane layer is then formed over the sacrificial layer. The membrane layer is porous to an etch product, which allows for the subsequent etching of the sacrificial layer leaving an air gap between the device structures and the membrane intact. The device may also include a cap layer formed above the device structures and the membrane. | 05-22-2014 |
20140134332 | Distribution of Gas Over A Semiconductor Water in Batch Processing - A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections. | 05-15-2014 |
20140129758 | WEAR LEVELING IN FLASH MEMORY DEVICES WITH TRIM COMMANDS - Systems and methods are provided to implement a memory device that includes a memory array having a plurality of sectors, a non-volatile memory that stores sector state information, and a memory controller that performs wear leveling according to the sector state information. The sector state information can specify respective states for respective sectors of the plurality of sectors of the memory array. The memory controller, based on the states of respective sectors, determines whether or not to swap contents of the sectors during wear leveling, thereby reducing write amplification effects. | 05-08-2014 |
20140129218 | Recognition of Speech With Different Accents - Computer-based speech recognition can be improved by recognizing words with an accurate accent model. In order to provide a large number of possible accents, while providing real-time speech recognition, a language tree data structure of possible accents is provided in one embodiment such that a computerized speech recognition system can benefit from choosing among accent categories when searching for an appropriate accent model for speech recognition. | 05-08-2014 |
20140124848 | ELECTRICALLY PROGRAMMABLE AND ERASEABLE MEMORY DEVICE - The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. | 05-08-2014 |
20140122785 | DATA WRITING METHOD AND SYSTEM - A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased. | 05-01-2014 |
20140120662 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved. The height of the semiconductor device can also be reduced since the upper surface of the semiconductor element is not enclosed with the molding portion. | 05-01-2014 |
20140117435 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 05-01-2014 |
20140113411 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip | 04-24-2014 |
20140104957 | PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line. | 04-17-2014 |
20140098624 | Supply Power Dependent Controllable Write Throughput for Memory Applications - Devices and methods that allow dynamic management of throughput in a memory device based on a power supply voltage are provided. According to various embodiments, the power supply level can be monitored. Based on the result of the monitoring, an appropriate throughput can be determined. Once the appropriate throughput is determined, an appropriate control signal based on the determined throughput can be generated. The control signal can be configured to cause a bitline driver circuit in a memory array to activate a number of bitlines consistent with the determined throughput. | 04-10-2014 |
20140097820 | Output Voltage Controller, Electronic Device, and Output Voltage Control Method - An output voltage controller includes a first controller which controls current supply to a inductor based on an output voltage, and a second controller which controls current supply to the inductor by controlling a period when an input end to which an input voltage is inputted, the inductor, and an output end from which the output voltage is outputted are coupled based on the input voltage. | 04-10-2014 |
20140097497 | Spacer Design to Prevent Trapped Electrons - Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices. | 04-10-2014 |
20140094001 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip. | 04-03-2014 |
20140092687 | METHOD, APPARATUS, AND MANUFACTURE FOR STAGGERED START FOR MEMORY MODULE - A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory. | 04-03-2014 |
20140089937 | PROCESSOR SYSTEM OPTIMIZATION - In order to enable the optimization of a processor system without relying upon knowhow or manual labor, an apparatus includes: information obtainment unit for reading, from memory, trace information of the processor system and performance information corresponding to the trace information; information analysis unit for analyzing the trace information and the performance information so as to obtain a performance factor such as an idle time, a processing completion time of a task, or the number of interprocessor communications as a result of the analysis; and optimization method output unit for displaying and outputting a method of optimizing the system in response to a result of the analysis. | 03-27-2014 |
20140085555 | Voltage Adjustment Circuit and Display Device Driving Circuit - A voltage adjustment circuit for adjusting a voltage to be supplied to scanning lines of a display device includes a slope adjustment circuit configured to adjust a slope of a decrease in the voltage based on data that is externally input, and a clamp voltage adjustment circuit configured to adjust a voltage value at which the voltage is clamped based on the data. | 03-27-2014 |
20140077347 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other. | 03-20-2014 |
20140075249 | Execution History Tracing Method - An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target. | 03-13-2014 |
20140070840 | Semiconductor Integrated Circuit, Operating Method of Semiconductor Integrated Circuit, and Debug System - A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced. | 03-13-2014 |
20140061895 | Multi-Chip Module and Method of Manufacture - A multi-chip module and a method for manufacturing the multi-chip module that mitigates wire breakage. A first semiconductor chip is mounted and wirebonded to a support substrate. A spacer is coupled to the first semiconductor chip. A support material is disposed on the spacer and a second semiconductor chip is positioned on the support material. The second semiconductor chip is pressed into the support material squeezing it into a region adjacent the spacer and between the first and second semiconductor chips. Alternatively, the support material is disposed on the first semiconductor chip and a die attach material is disposed on the spacer. The second semiconductor chip is pressed into the die attach material and the support material, squeezing a portion of the support material over the spacer edges. Wirebonds are formed between the support substrate and the first and second semiconductor chips. | 03-06-2014 |
20140061771 | Memory Device with Charge Trap - A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer. | 03-06-2014 |
20140055108 | POWER SUPPLY DEVICE, CONTROL CIRCUIT, ELECTRONIC DEVICE AND CONTROL METHOD FOR POWER SUPPLY - A power supply device that includes a switch circuit to which an input voltage is supplied, a coil coupled between the switch circuit and an output terminal from which an output voltage is outputted. A voltage adding circuit adds a slope voltage to a reference voltage. A control unit compares a feedback voltage corresponding to the output voltage and the reference voltage and switches the switch circuit at a timing corresponding to a comparison result of the feedback voltage and the reference voltage. A slope adjustment circuit differentiates a current flowing in the coil and adjusts a slope amount of the slope based on a differentiation result of the current. | 02-27-2014 |
20140042514 | CONTACTS FOR SEMICONDUCTOR DEVICES - A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts. | 02-13-2014 |
20140040587 | Power Savings Apparatus and Method for Memory Device Using Delay Locked Loop - Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle. | 02-06-2014 |
20140038378 | APPARATUS AND METHOD FOR A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SOURCE SIDE PUNCH-THROUGH PROTECTION IMPLANT - A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region. | 02-06-2014 |
20140035170 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD - The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion. | 02-06-2014 |
20140024190 | DUAL STORAGE NODE MEMORY - An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements. | 01-23-2014 |
20140015138 | Leakage Reducing Writeline Charge Protection Circuit - Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region. | 01-16-2014 |
20140001537 | SELF-ALIGNED SI RICH NITRIDE CHARGE TRAP LAYER ISOLATION FOR CHARGE TRAP FLASH MEMORY | 01-02-2014 |
20130339028 | Power-Efficient Voice Activation - A voice activation system is provided. The voice activation system includes a first stage configured to output a first activation signal if at least one energy characteristic of a received audio signal satisfies at least one threshold and a second stage configured to transition from a first state to a second state in response to the first activation signal and, when in the second state, to output a second activation signal if at least a portion of a profile of the audio signal substantially matches at least one predetermined profile. | 12-19-2013 |
20130337612 | HEAT DISSIPATION METHODS AND STRUCTURES FOR SEMICONDUCTOR DEVICE - A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip. | 12-19-2013 |
20130322181 | METHOD, APPARATUS, AND MANUFACTURE FOR FLASH MEMORY ADAPTIVE ALGORITHM - A method, apparatus, and manufacture for a memory device is provided. The memory device includes a memory cell region including sectors, where each sector includes memory cells. The memory device further includes a memory controller that is configured to control program operations and erase operations to the memory cells. During erase operations to the memory cells, pre-programming occurs in which each un-programmed memory cell in the sector being erased is programmed by applying at least one programming pulse at a program voltage until a program verify passes. Then, the program voltage is adjusted based on the number of programming pulses applied until the program-verify passed. During subsequent program operations in that sector, programming pulses are applied with the adjusted program voltage. | 12-05-2013 |
20130316537 | SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING - A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer. | 11-28-2013 |
20130306885 | SOFT ERROR RESISTANT CIRCUITRY - An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0.5% thermal neutron absorber. The thermal neutron absorber layer can be a glass layer or can include a molding compound. | 11-21-2013 |
20130258775 | Adaptively Programming or Erasing Flash Memory Blocks - Embodiments described herein generally relate to programming and erasing a FLASH memory. In an embodiment, a method of programming or erasing the contents of a block of a FLASH memory includes determining a voltage of a pulse based on an age of the block and outputting the pulse to at least a portion of the block. The pulse is used to program or erase the block. | 10-03-2013 |
20130237030 | METAL-INSULATOR-METAL (MIM) DEVICE AND METHOD OF FORMATION THEREOF - In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. | 09-12-2013 |
20130237022 | METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING - A semiconductor device ( | 09-12-2013 |
20130228851 | MEMORY DEVICE PROTECTION LAYER - A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells. | 09-05-2013 |
20130193537 | SYSTEM AND METHOD FOR DETECTING PARTICLES WITH A SEMICONDUCTOR DEVICE - Systems and methods are described herein for detecting particles emitted by nuclear material. The systems comprise one or more semiconductor devices for detecting particles emitted from nuclear material. The semiconductor devices can comprise a charge storage element comprising several layers. A non-conductive charge storage layer enveloped on top and bottom by dielectric layers is mounted on a substrate. At least one top semiconductor layer can be placed on top of the top dielectric layer. A reactive material that reacts to particles, such as neutrons emitted from nuclear material, can be incorporated into the top semiconductor layer. When the reactive material reacts to a particle emitted from nuclear material, ions are generated that can alter the charge storage layer and enable detection of the particle. | 08-01-2013 |
20130183819 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film. | 07-18-2013 |
20130175601 | FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer. | 07-11-2013 |
20130169841 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention is a semiconductor device including: a resistor R | 07-04-2013 |
20130161728 | FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer. | 06-27-2013 |
20130159371 | Arithmetic Logic Unit Architecture - Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a dimension of a feature vector, a look up table module configured to output a second value based on the variance value, and a combination module configured to combine the first value and the second value to generate the one-dimensional score. | 06-20-2013 |
20130158997 | Acoustic Processing Unit Interface - Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, a speech recognition system is provided. The system includes a processing unit configured to divide a received audio signal into consecutive frames having respective frame vectors, an acoustic processing unit (APU), a data bus that couples the processing unit and the APU. The APU includes a local, non-volatile memory that stores a plurality of senones, a memory buffer coupled to the memory, the acoustic processing unit being configured to load at least one Gaussian probability distribution vector stored in the memory into the memory buffer, and a scoring unit configured to simultaneously compare a plurality of dimensions of a Gaussian probability distribution vector loaded into the memory buffer with respective dimensions of a frame vector received from the processing unit and to output a corresponding score to the processing unit. | 06-20-2013 |
20130158996 | Acoustic Processing Unit - Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. The apparatus can include a senone scoring unit (SSU) control module, a distance calculator, and an addition module. The SSU control module can be configured to receive a feature vector. The distance calculator can be configured to receive a plurality of Gaussian probability distributions via a data bus having a width of at least one Gaussian probability distribution and the feature vector from the SSU control module. The distance calculator can include a plurality of arithmetic logic units to calculate a plurality of dimension distance scores and an accumulator to sum the dimension distance scores to generate a Gaussian distance score. Further, the addition module is configured to sum a plurality of Gaussian distance scores to generate a senone score. | 06-20-2013 |
20130151776 | RAPID MEMORY BUFFER WRITE STORAGE SYSTEM AND METHOD - Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a host for processing information, a memory controller and a memory. The memory controller controls communication of the information between the host and the memory, wherein the memory controller routes data rapidly to a buffer of the memory without buffering in the memory controller. The memory stores the information. The memory includes a buffer for temporarily storing the data while corresponding address information is determined. | 06-13-2013 |
20130140720 | VOID FREE INTERLAYER DIELECTRIC - A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids. | 06-06-2013 |
20130134578 | DEVICE HAVING MULTIPLE WIRE BONDS FOR A BOND AREA AND METHODS THEREOF - Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security. | 05-30-2013 |
20130132706 | TABLE LOOKUP OPERATION ON MASKED DATA - Processing of masked data using table lookups is described. A mask is applied to input data to generate masked input data. The mask and the masked input data are used in combination to locate an entry in a lookup table. The entry corresponds to a transformed version of the input data. | 05-23-2013 |
20130130487 | Integrated Circuit with Metal and Semi-Conducting Gate - A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess. | 05-23-2013 |
20130124789 | PARTIAL ALLOCATE PAGING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 05-16-2013 |
20130107644 | STORAGE DEVICE, CONTROL METHOD OF STORAGE DEVICE, AND CONTROL METHOD OF STORAGE CONTROL DEVICE | 05-02-2013 |
20130105878 | FLASH MEMORY CELL WITH FLAIR GATE | 05-02-2013 |
20130100318 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFORE - Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized. | 04-25-2013 |
20130094297 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device. | 04-18-2013 |
20130083604 | APPARATUS AND METHOD FOR SMART VCC TRIP POINT DESIGN FOR TESTABILITY - An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped. | 04-04-2013 |
20130078795 | ETCH STOP LAYER FOR MEMORY CELL RELIABILITY IMPROVEMENT - A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device. | 03-28-2013 |
20130067153 | HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 03-14-2013 |
20130060980 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer. | 03-07-2013 |
20130032725 | IMAGING DEVICE - An imaging device suitable for detecting certain imaging particles and recording the detection of imaging particles, and as such can include certain recording devices such as a charge storage structure. | 02-07-2013 |
20130024742 | ERROR CORRECTION FOR FLASH MEMORY - Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory. | 01-24-2013 |
20130023101 | METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY SPACERS FOR CORE AND HIGH VOLTAGE DEVICES AND LOW TEMPERATURE SPACERS FOR HIGH PERFORMANCE LOGIC DEVICES - A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section. | 01-24-2013 |
20130005138 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 01-03-2013 |
20130001700 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 01-03-2013 |
20130001428 | RADIATION DETECTING DEVICE AND METHOD OF OPERATING - A method of operating a radiation-detecting device includes charging a first charge storage region of a charge storage structure to place a first charge value at the first charge storage region, and charging a second charge storage region of the charge storage structure to place a second charge value at the second charge storage region. The method further includes conducting a first read operation to determine a change in the first charge value at the first charge storage region at a first time after charging the first charge storage region, and determining a first radiation flux value for an environment containing the charge storage structure based on the change in the first charge value at the first time. | 01-03-2013 |
20120327717 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-27-2012 |
20120320680 | METHOD, APPARATUS, AND MANUFACTURE FOR STAGGERED START FOR MEMORY MODULE - A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory. | 12-20-2012 |
20120317348 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 12-13-2012 |
20120302017 | Method and System for Providing Contact to a First Polysilicon Layer in a Flash Memory Device - A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor. | 11-29-2012 |
20120294103 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 11-22-2012 |
20120275235 | METHOD AND APPARATUS FOR TEMPERATURE COMPENSATION FOR PROGRAMMING AND ERASE DISTRIBUTIONS IN A FLASH MEMORY - A method and apparatus for a memory device is provided. The memory device includes a memory cell, a memory controller, and a temperature-sensing device that detects a temperature. The memory controller enables adjusting, based on the detected temperature, a parameter associated with a bit-altering operation to the memory cell that changes a threshold voltage of the memory cell such that the threshold voltage to which the memory cell is changed to by the bit-altering operation is compensated for variations in temperature. | 11-01-2012 |
20120275231 | METHOD, APPARATUS, AND MANUFACTURE FOR FLASH MEMORY WRITE ALGORITHM FOR FAST BITS - A method, apparatus, and manufacture for a memory device is provided. The memory device includes memory cells that each store two bits, and a memory controller. During write operations, for each bit in each memory cell that is to be programmed, the memory controller determines whether both bits of the memory cell are being programmed. While controlling an application of programming pulses to the memory cell to program the bit, if both bits of the memory cell are being programmed, the memory controller causes the application of each programming pulse to the bit to occur for a standard duration. Otherwise, the memory controller causes the application of each programming pulse to the bit to occur for a reduced duration. The reduced duration is less than three-fourths of the standard duration. | 11-01-2012 |
20120275229 | APPARATUS AND METHOD FOR EXTERNAL CHARGE PUMP ON FLASH MEMORY MODULE - A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages. | 11-01-2012 |
20120271991 | RELOCATING DATA IN A MEMORY DEVICE - Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. | 10-25-2012 |
20120241871 | INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE SAME DIE - A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away. | 09-27-2012 |
20120218700 | ELECTRONIC DEVICES WITH ULTRAVIOLET BLOCKING LAYERS AND PROCESSES OF FORMING THE SAME - An electronic device can include a conductive feature and an ultraviolet (“UV”) blocking layer overlying the conductive feature. The electronic device can also include an insulating layer overlying the UV blocking layer. The electronic device can further include a conductive structure extending into an opening within the insulating layer, wherein the conductive structure is electrically connected to the conductive feature. In one aspect, the UV blocking layer lies within 90 nm of the conductive structure. The insulating layer can be at least 4 times thicker than the UV blocking layer. In another aspect, a method can be used in forming the electronic device. In still a further aspect, a system can include the electronic device, a processor, and a display, wherein the processor is electrically coupled to the electronic device and the display. | 08-30-2012 |
20120202355 | PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD - A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes. | 08-09-2012 |
20120181591 | NON-VOLATILE FINFET MEMORY ARRAY AND MANUFACTURING METHOD THEREOF - An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction. | 07-19-2012 |
20120160807 | SYSTEM, METHOD AND APPARATUS FOR REDUCING PLASMA NOISE ON POWER PATH OF ELECTROSTATIC CHUCK - A vacuum plasma system has a table with a table power connector, and a fixture spaced apart from the table for defining a chamber between the table and the fixture. An electrostatic chuck (ESC) is mounted to the table in the chamber. The ESC has a side for supporting a workpiece, and an ESC power connector that electrically couples with the table power connector. A coupling extends between the table and ESC power connectors to provide electrical connection therebetween. A shield surrounds the coupling and portions of the table and ESC power connectors to reduce external fields applied to the coupling. | 06-28-2012 |
20120142175 | DUAL SPACER FORMATION IN FLASH MEMORY - A method and manufacture for memory device fabrication is provided. In one embodiment, at least one oxide-nitride spacer is formed as follows. An oxide layer is deposited over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick. The flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array. Also, the deposited oxide layer is deposited such that it completely gap-fills the gaps between the word line gates of the dense array of word line gates. Next, a nitride layer is depositing over the oxide layer. Then, the nitride layer is etched until the at least a portion of the oxide layer is exposed. Next, the oxide layer is etched until at least a portion of the substrate is exposed. | 06-07-2012 |
20120139023 | METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION - A method and apparatus for a flash memory is provided. A NAND flash memory array includes a cell body, a first selective gate, and a first edge line. The cell body includes recessed doped source/drain region between the first selective gate and the first edge word line. | 06-07-2012 |
20120066464 | APPARATUS AND METHOD FOR PROGRAMMABLE READ PREAMBLE - A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data. | 03-15-2012 |
20120066434 | APPARATUS, METHOD, AND MANUFACTURE FOR USING A READ PREAMBLE TO OPTIMIZE DATA CAPTURE - A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern. | 03-15-2012 |
20120066433 | Apparatus and method for read preamble disable - A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble. | 03-15-2012 |
20120063243 | APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE - A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to. | 03-15-2012 |
20120056260 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 03-08-2012 |
20120038051 | BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME - A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect. | 02-16-2012 |
20120034755 | METHOD AND MANUFACTURE FOR HIGH VOLTAGE GATE OXIDE FORMATION AFTER SHALLOW TRENCH ISOLATION FORMATION - A method and manufacture for fabrication of flash memory is provided. In fabricating the periphery region of the flash memory, the low voltage gate oxides and high voltage gate oxides are grown to the same height as each other prior to STI etching. After STI etching and gap fill, the nitride above the high voltage gate oxide regions are etched, and the oxide in high voltage gate oxide regions is grown to the appropriate thickness for a high voltage gate oxide. | 02-09-2012 |
20120032308 | GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS - Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD. | 02-09-2012 |
20110317466 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-29-2011 |
20110278660 | ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD. | 11-17-2011 |
20110238866 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus. | 09-29-2011 |
20110237060 | SACRIFICIAL NITRIDE AND GATE REPLACEMENT - Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved. | 09-29-2011 |
20110236773 | FUEL CELL CATALYST REGENERATION - Systems that facilitate operating proton exchange membrane (PEM) fuel cells are provided. The systems employ a fuel supply component that supplies fuel to the proton exchange membrane fuel cell; and a regeneration component that provides a reducing agent comprising a mixture of hydrogen and nitrogen, or a reducing plasma to a cathode catalyst of the proton exchange membrane fuel cell to reduce the cathode catalyst. | 09-29-2011 |