S.O.I.TEC Silicon on Insulator Technologies Patent applications |
Patent application number | Title | Published |
20130146805 | ETCHANT FOR CONTROLLED ETCHING OF GE AND GE-RICH SILICON GERMANIUM ALLOYS - The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application. | 06-13-2013 |
20130093033 | THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS - The invention relates to a method of initiating molecular bonding, comprising bringing one face ( | 04-18-2013 |
20130039615 | THREE DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYSTEMS INCLUDING PHOTOACTIVE DEVICES AND SEMICONDUCTOR-ON-INSULATOR SUBSTRATES, AND METHODS OF FORMING SUCH THREE DIMENSIONALLY INTEGRATED SEMICONDUCTOR SYSTEMS - Three dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling an waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter. | 02-14-2013 |
20130037960 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES IN 3D INTEGRATION PROCESSES USING RECOVERABLE SUBSTRATES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods. | 02-14-2013 |
20130037959 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING INTERCONNECT LAYERS HAVING ONE OR MORE OF ELECTRICAL, OPTICAL, AND FLUIDIC INTERCONNECTS THEREIN, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS - Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods. | 02-14-2013 |
20130020704 | BONDING SURFACES FOR DIRECT BONDING OF SEMICONDUCTOR STRUCTURES - Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods. | 01-24-2013 |
20120252189 | METHODS FOR BONDING SEMICONDUCTOR STRUCTURES INVOLVING ANNEALING PROCESSES, AND BONDED SEMICONDUCTOR STRUCTURES AND INTERMEDIATE STRUCTURES FORMED USING SUCH METHODS - Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods. | 10-04-2012 |
20120248622 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES INCLUDING TWO OR MORE PROCESSED SEMICONDUCTOR STRUCTURES CARRIED BY A COMMON SUBSTRATE, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are formed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods. | 10-04-2012 |
20120248621 | METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS - Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods. | 10-04-2012 |
20120211870 | III-V SEMICONDUCTOR STRUCTURES WITH DIMINISHED PIT DEFECTS AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime. | 08-23-2012 |
20120199845 | METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer. | 08-09-2012 |
20120190170 | PRECISE OXIDE DISSOLUTION - A method for dissolving the buried oxide layer of a SeOI wafer in order to decrease its thickness. The SeOI wafer includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer. The dissolution rate of the buried oxide layer is controlled and set to be below 0.06 Å/sec. | 07-26-2012 |
20120161289 | STRAIN RELAXATION USING METAL MATERIALS AND RELATED STRUCTURES - Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed exposing the metal material to a temperature sufficient it to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods. | 06-28-2012 |
20120153484 | METHODS FOR DIRECTLY BONDING TOGETHER SEMICONDUCTOR STRUCTURES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS - Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods. | 06-21-2012 |
20120094501 | ETCHING COMPOSITION, IN PARTICULAR FOR SILICON MATERIALS, METHOD FOR CHARACTERIZING DEFECTS ON SURFACES OF SUCH MATERIALS AND PROCESS OF TREATING SUCH SURFACES WITH THE ETCHING COMPOSTION - The present invention relates to an etching composition, in particular, for silicon materials, a method for characterizing defects on surfaces of such materials and a process of treating such surfaces with the etching composition, wherein the etching composition comprises an organic oxidant dissolved in a solvent, and a deoxidant, wherein the deoxidant comprises HF or HBF | 04-19-2012 |
20120091100 | ETCHANT FOR CONTROLLED ETCHING OF GE AND GE-RICH SILICON GERMANIUM ALLOYS - The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application. | 04-19-2012 |
20120083101 | SYSTEMS AND METHODS FOR FORMING SEMICONDUCTOR MATERIALS BY ATOMIC LAYER DEPOSITION - Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns. | 04-05-2012 |
20120083100 | THERMALIZING GAS INJECTORS FOR GENERATING INCREASED PRECURSOR GAS, MATERIAL DEPOSITION SYSTEMS INCLUDING SUCH INJECTORS, AND RELATED METHODS - Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors. | 04-05-2012 |
20120074427 | METHOD FOR MANUFACTURING A LAYER OF GALLIUM NITRIDE OR GALLIUM AND ALUMINUM NITRIDE - The present invention relates to a crack-free monocrystalline nitride layer having the composition AlxGa | 03-29-2012 |
20120028440 | METHOD OF FABRICATING A MULTILAYER STRUCTURE WITH CIRCUIT LAYER TRANSFER - A method of producing a composite structure comprises a step of producing a first layer of microcomponents on one face of a first substrate, the first substrate being held flush against a holding surface of a first support during production of the microcomponents, and a step of bonding the face of the first substrate comprising the layer of microcomponents onto a second substrate. During the bonding step, the first substrate is held flush against a second support, the holding surface of which has a flatness that is less than or equal to that of the first support used during production of the first layer of microcomponents. | 02-02-2012 |
20110305835 | SYSTEMS AND METHODS FOR A GAS TREATMENT OF A NUMBER OF SUBSTRATES - Systems and methods for the gas treatment of one or more substrates include at least two gas injectors in a reaction chamber, one of which may be movable. The systems may also include a substrate support structure for holding one or more substrates disposed within the reaction chamber. The movable gas injector may be disposed between the substrate support structure and another gas injector. The gas injectors may be configured to discharge different process gasses therefrom. The substrate support structure may be rotatable around an axis of rotation. | 12-15-2011 |
20110294245 | ADAPTATION OF THE LATTICE PARAMETER OF A LAYER OF STRAINED MATERIAL - The invention relates to a method of adapting the lattice parameter of a seed layer of a strained material, comprising the following successive steps: a) a structure is provided that has a seed layer of strained material, of lattice parameter A | 12-01-2011 |
20110291247 | RELAXATION AND TRANSFER OF STRAINED MATERIAL LAYERS - The present invention relates to a method for the formation of an at least partially relaxed strained material layer, the method comprising the steps of providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment. | 12-01-2011 |
20110287604 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING DIRECT BONDING OF SUBSTRATES - The invention relates to a method of initiating molecular bonding, comprising bringing one face of a first wafer to face one face of a second wafer and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example using a bearing element of a tool, of a mechanical pressure in the range 0,1 MPa to 33.3 MPa. | 11-24-2011 |
20110287571 | METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR - A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality. | 11-24-2011 |
20110284863 | III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME - Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. | 11-24-2011 |
20110278691 | THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS - The invention relates to a method of initiating molecular bonding, comprising bringing one face ( | 11-17-2011 |
20110278597 | METHOD OF PRODUCING A LAYER OF CAVITIES - A method of producing a layer of cavities in a structure comprises at least one substrate formed from a material that can be oxidized or nitrided, the method comprising the following steps: implanting ions into the substrate in order to form an implanted ion concentration zone at a predetermined mean depth; heat treating the implanted substrate to form a layer of cavities at the implanted ion concentration zone; and forming an insulating layer in the substrate by thermochemical treatment from one surface of the substrate, the insulating layer that is formed extending at least partially into the layer of cavities. | 11-17-2011 |
20110266651 | METHOD FOR MANUFACTURING COMPONENTS - The invention relates to a method for manufacturing components on a mixed substrate. It comprises the following steps: —providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, —forming in this substrate a plurality of trenches opening out at the free surface of the thin layer and extending over a depth such that it passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, —forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, —proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof. | 11-03-2011 |
20110233720 | TREATMENT FOR BONDING INTERFACE STABILIZATION - A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process. | 09-29-2011 |
20110233719 | TEST METHOD ON THE SUPPORT SUBSTRATE OF A SUBSTRATE OF THE "SEMICONDUCTOR ON INSULATOR" TYPE - The invention relates to a test method comprising an electrical connection contact on the support of a substrate of the semiconductor-on-insulator type. | 09-29-2011 |
20110230003 | PROCESS FOR FABRICATING A MULTILAYER STRUCTURE WITH POST-GRINDING TRIMMING - The invention relates to a process for fabricating a multilayer structure ( | 09-22-2011 |
20110215380 | ELECTRONIC DEVICES WITH IMPROVED OHMIC CONTACT - In one embodiment, the disclosure relates to an electronic device successively comprising from its base to its surface: (a) a support layer, (b) a channel layer adapted to contain an electron gas, (c) a barrier layer and (d) at least one ohmic contact electrode formed by a superposition of metallic layers, a first layer of which is in contact with the barrier layer. The device is remarkable in that the barrier layer includes a contact region under the ohmic contact electrode(s). The contact region includes at least one metal selected from the metals forming the superposition of metallic layers. Furthermore, a local alloying binds the contact region and the first layer of the electrode(s). | 09-08-2011 |
20110195560 | METHOD OF PRODUCING A SILICON-ON-SAPPHIRE TYPE HETEROSTRUCTURE - The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate onto a sapphire substrate and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate. In accordance with the method, grinding is carried out using a wheel with a grinding surface that comprises abrasive particles having a mean dimension of more than 6.7 μm; further, after grinding and before etching, the method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range of 150° C. to 170° C. | 08-11-2011 |
20110193201 | METHOD TO FABRICATE AND TREAT A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE, ENABLING DISPLACEMENT OF DISLOCATIONS, AND CORRESPONDING STRUCTURE - The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate ( | 08-11-2011 |
20110183493 | PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE - The present invention relates to a process for manufacturing a structure comprising a germanium layer ( | 07-28-2011 |
20110163410 | METHOD FOR PRODUCING HYBRID COMPONENTS - A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling. | 07-07-2011 |
20110156212 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES OR DEVICES USING LAYERS OF SEMICONDUCTOR MATERIAL HAVING SELECTED OR CONTROLLED LATTICE PARAMETERS - Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature. | 06-30-2011 |
20110114965 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES USING GLASS BONDING LAYERS, AND SEMICONDUCTOR STRUCTURES AND DEVICES FORMED BY SUCH METHODS - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to a substrate using a glass may be utilized to control the strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control the strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material. | 05-19-2011 |
20110101373 | METHOD OF FORMING A COMPOSITE LASER SUBSTRATE - A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer ( | 05-05-2011 |
20110076849 | PROCESS FOR BONDING AND TRANSFERRING A LAYER - A method of fabricating a multilayer substrate may include bonding a front face of a donor substrate to a front face of a receiver substrate by molecular adhesion to form a stack and applying a heat treatment to the stack to consolidate a bond interface between the donor substrate and the receiver substrate. The method may further include thinning a back face of the donor substrate, trimming a periphery of the donor substrate and at least a portion of a periphery of the receiver substrate, and etching the back face of the donor substrate, the periphery of the donor substrate, and the at least a portion of the periphery of the receiver substrate subsequent to thinning the back face of the donor substrate and trimming the periphery of the donor substrate and the at least a portion of the periphery of the receiver substrate. | 03-31-2011 |
20110045611 | METHOD OF INITIATING MOLECULAR BONDING - The invention relates to a method of initiating molecular bonding, comprising bringing one face ( | 02-24-2011 |
20110024747 | METHODS FOR IMPROVING THE QUALITY OF GROUP III-NITRIDE MATERIALS AND STRUCTURES PRODUCED BY THE METHODS - The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods. | 02-03-2011 |
20110011450 | METHODS AND STRUCTURES FOR BONDING ELEMENTS - Embodiments of the invention relate to methods and structures for fabricating semiconductor structures that include at least one bonding layer for attaching two or more elements to one another. The at least one bonding layer may be at least substantially comprised of zinc, silicon and oxygen. | 01-20-2011 |
20100323496 | PROCESS FOR MANUFACTURING A COMPOSITE SUBSTRATE - The invention relates to a process for manufacturing a composite substrate comprising bonding a first substrate ( | 12-23-2010 |
20100258846 | ELECTRONIC DEVICE WITH CONTROLLED ELECTRICAL FIELD - The disclosure relates to electronic devices and associated methods of manufacture including materials of the Group III/N. An exemplary device successively includes, from its base towards its surface: (i) a support substrate, (ii) a layer adapted to contain an electron gas, (iii) a barrier layer, and (iv) a superficial layer extending on at least one part of the surface of the barrier layer, wherein the superficial layer has an electrical field of which the current is controlled so that, in at least one first region of the superficial layer, the electrical field is weaker than in a second region of the superficial layer. | 10-14-2010 |
20100244203 | SEMICONDUCTOR STRUCTURE HAVING A PROTECTIVE LAYER - A semiconductor structure includes a substrate having a first nitride-based semiconductor layer. A pseudomorphic protective layer is formed on the first nitride-based semiconductor layer and a second nitride-based semiconductor layer is formed on the pseudomorphic protective layer. The pseudomorphic protective layer has a thickness that is less than a critical thickness so that it drives the material quality of the second nitride-based semiconductor layer to correspond with that of the first nitride-based semiconductor layer. | 09-30-2010 |
20100216316 | TRANSFER OF HIGH TEMPERATURE WAFERS - This invention provides apparatus, protocols, and methods that permit wafers to be loaded and unloaded in a gas-phase epitaxial growth chamber at high temperatures. Specifically, this invention provides a device for moving wafers or substrates that can bath a substrate being moved in active gases that are optionally temperature controlled. The active gases can act to limit or prevent sublimation or decomposition of the wafer surface, and can be temperature controlled to limit or prevent thermal damage. Thereby, previously-necessary temperature ramping of growth chambers can be reduced or eliminated leading to improvement in wafer throughput and system efficiency. | 08-26-2010 |
20100207236 | METHOD FOR MAKING A SUBSTRATE OF THE SEMICONDUCTOR ON INSULATOR TYPE WITH AN INTEGRATED GROUND PLANE - A method for making a semiconductor on insulator (SeOI) type substrate that includes an integrated ground plane under the insulating layer wherein the substrate is intended to be used in making electronic components. This method includes implanting atoms or ions of a metal in at least one portion of a semiconducting receiver substrate, carrying out a heat treatment of the receiver substrate in order to obtain an integrated ground plane on or in at least one portion of that receiver substrate, transferring an active layer stemming from a semiconducting donor substrate onto the receiver substrate, with an insulating layer being inserted in between the donor and receiver substrates to obtain the substrate with an integrated ground plane. | 08-19-2010 |
20100200854 | Method for reclaiming a surface of a substrate - A method for reclaiming a surface of a substrate, wherein the surface, in particular a silicon surface, comprises a protruding residual topography, comprising at least the layer of a first material. By providing a filling material in the non-protruding areas of the surface of the substrate and the subsequent polishing, the reclaiming can be carried out such that the material consuming double-sided polishing step used in the prior art is no longer necessary. | 08-12-2010 |
20100193899 | PRECISE OXIDE DISSOLUTION - In a Semiconductor-on-Insulator (SeOI) wafer that includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer, a method of decreasing the thickness of the BOX layer by dissolving it at a dissolution rate that is controlled and set to be below 0.06 Å/sec in order to avoid increasing Dit. The Dit after dissolution of the BOX layer is typically below 1E12 cm-2 eV-1. | 08-05-2010 |
20100190416 | Device for polishing the edge of a semiconductor substrate - Disclosed are devices and methods for chemical and mechanical polishing of the edge of a semiconductor substrate that includes a protruding residual topography in a peripheral region of the substrate resulting from a layer transfer process based on an ion implantation step, a bonding step and a detachment step, such as Smart-Cut™. To be able to remove this step-like region, exemplary devices include a polishing pad, wherein the polishing pad is arranged and configured such that its cross section in a plane perpendicular to the surface of a substrate holder is curved. The disclosure furthermore relates to a pad holder used certain exemplary devices and methods for polishing a semiconductor substrate that has a protruding residual topography. | 07-29-2010 |
20100190000 | METHOD OF FABRICATING A COMPOSITE STRUCTURE WITH A STABLE BONDING LAYER OF OXIDE - A method of fabricating a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10 | 07-29-2010 |
20100178749 | METHOD OF FABRICATING EPITAXIALLY GROWN LAYERS ON A COMPOSITE STRUCTURE - A method of fabricating materials by epitaxy by epitaxially growing at least one layer of a material upon a composite structure that has at least one thin film bonded to a support substrate and a bonding layer of oxide formed by deposition between the support substrate and the thin film. The thin film and the support substrate have a mean thermal expansion coefficient of 7×10 | 07-15-2010 |
20100164048 | METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE - The disclosure provides a method for fabricating a semiconductor substrate comprising the steps of: providing a semiconductor on insulator type substrate, providing a diffusion barrier layer and providing a second semiconductor layer. By providing the diffusion barrier layer, it becomes possible to suppress diffusion from the highly doped first semiconductor layer into the second semiconductor layer. The invention also relates to a corresponding semiconductor substrate and opto-electronic devices comprising such a substrate. | 07-01-2010 |
20100105217 | DEFECTIVITY OF POST THIN LAYER SEPARATION BY MODIFICATION OF ITS SEPARATION ANNEALING - A method of detaching two substrates at the embrittlement zone situated at a given depth of one of the two substrates. The method includes a separation annealing step implemented in a furnace, wherein the annealing includes a first phase during which the temperature changes along an upgrade allowing a high temperature to be reached and annealing at this high temperature to be stabilized, and a second phase during which the temperature changes along a downgrade, at the end of which the furnace is opened to unload the substrates from the furnace. The second phase is regulated so as to minimize temperature inhomogeneities such as cleavage defects at the detached surfaces of the substrates when the furnace is opened. | 04-29-2010 |
20100087049 | RELAXATION OF A STRAINED MATERIAL LAYER WITH APPLICATION OF A STIFFENER - The invention relates to methods of fabricating a layer of at least partially relaxed material, such as for electronics, optoelectronics or photovoltaics. An exemplary method includes supplying a structure that includes a layer of strained material situated between a reflow layer and a stiffener layer. The method further includes applying a heat treatment that brings the reflow layer to a temperature equal to or greater than the glass transition temperature of the reflow layer, and the thickness of the stiffener layer is progressively reduced during heat treatment. The invention also relates to an exemplary method of fabricating semiconductor devices on a layer of at least partially relaxed material. Specifically, at least one active layer may be formed on the at least partially relaxed material layer. The active layer may include laser components, photovoltaic components and/or electroluminescent diodes. | 04-08-2010 |
20100038756 | (110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES COMPRISING SAID (110) ORIENTED SILICON SUBSTRATE - The present invention relates to method of fabricating a (110) oriented silicon substrate and to a method of fabricating a bonded pair of substrates comprising such a (110) oriented silicon substrate. The invention further relates to a silicon substrate with (110) orientation and to a bonded pair of silicon substrates comprising a first silicon substrate with (100) orientation and a second silicon substrate with (110) orientation. It is the object of the present invention to provide methods and substrates of the above mentioned type with a high efficiency wherein the formed (110) substrate has at least near and at its surface virtually no defects. The object is solved by a method of fabricating a silicon substrate with (110) orientation and by a method of fabricating a bonded pair of silicon substrates, comprising the steps of providing a basic silicon substrate with (110) orientation, said basic silicon substrate having a roughness being equal or less than 0.15 nm RMS in a 2×2 μm | 02-18-2010 |
20100006857 | MULTILAYER STRUCTURE AND FABRICATION THEREOF - A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity. | 01-14-2010 |
20090205563 | TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER - The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl | 08-20-2009 |
20080248631 | WAFER AND METHOD OF PRODUCING A SUBSTRATE BY TRANSFER OF A LAYER THAT INCLUDES FOREIGN SPECIES - A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties. The preferred embodiment produces substrates with a thin InP layer rendered semi-insulating by iron diffusion. | 10-09-2008 |
20080210975 | METHOD OF FABRICATING HETEROEPITAXIAL MICROSTRUCTURES - An efficient method of fabricating a high-quality heteroepitaxial microstructure having a smooth surface. The method includes detaching a layer from a base structure to provide a carrier substrate having a detached surface, and then forming a heteroepitaxial microstructure on the detached surface of the carrier substrate by depositing an epitaxial layer on the detached surface of a carrier substrate. Also included is a heteroepitaxial microstructure fabricated from such method. | 09-04-2008 |