AGERE SYSTEMS INC. Patent applications |
Patent application number | Title | Published |
20140256364 | CORDLESS TELEPHONE ACTIVE-CALL ENABLED INTERCOM - A method of using an intercom on a cordless telephone during an active call. The active call is put on hold while the intercom is in use. Once the call is re-activated, the intercom is shut off. This system may be designed for a cordless telephone with one handset or a plurality of handsets. | 09-11-2014 |
20140065791 | ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS - An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology. | 03-06-2014 |
20130250745 | Systems and Methods for Improved Servo Data Operation - Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker. The interpolation circuit is operable to interpolate the position location data and to provide an interpolated position location data. | 09-26-2013 |
20130205185 | Systems and Methods for Low Latency Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. For example, a media defect detection systems is disclosed that includes a data input derived from a medium, a fast envelope calculation circuit that receives the data input and provides a fast decay envelope value based on the data input, a slow envelope calculation circuit that receives the data input and provides a slow decay envelope value based on the data input, and a media defect detection circuit. The media defect detection circuit receives the slow decay envelope value and the fast decay envelope value, calculates a ratio value of the fast decay envelope value to the slow decay envelope value, and asserts a defect output based at least in part on the comparison of the ratio value to a defect threshold value. | 08-08-2013 |
20130034245 | SPEAKERPHONE USING ADAPTIVE PHASE ROTATION - An improved speakerphone for a cellular telephone, portable telephone handset, or the like. In one embodiment, a receiver provides an audio signal, and a first phase-shifter phase-shifts the audio signal by a first phase-shift amount. A second phase-shifter phase-shifts the audio signal by a second phase-shift amount and drives a loudspeaker. A detector generates average and peak values of the first phase-shifted audio signal. A processor sets the first phase-shift amount to each one of a plurality of phase-shift amounts and calculates a corresponding average-to-peak ratio value from the peak and average values. The processor then selects one of the plurality of phase-shift amounts having a corresponding average-to-peak ratio value that meets at least one criteria (e.g., the largest one of the average-to-peak ratio values), and then sets the second phase-shift amount to be the same as the selected phase-shift amount. This enhances the perceived loudness of sound from loudspeaker. | 02-07-2013 |
20130024620 | METHOD AND APPARATUS FOR ADAPTIVE CACHE FRAME LOCKING AND UNLOCKING - Most recently accessed frames are locked in a cache memory. The most recently accessed frames are likely to be accessed by a task again in the near future and may be locked at the beginning of a task switch or interrupt to improve cache performance. The list of most recently used frames is updated as a task executes and may be embodied as a list of frame addresses or a flag associated with each frame. The list of most recently used frames may be separately maintained for each task if multiple tasks may interrupt each other. An adaptive frame unlocking mechanism is also disclosed that automatically unlocks frames that may cause a significant performance degradation for a task. The adaptive frame unlocking mechanism monitors a number of times a task experiences a frame miss and unlocks a given frame if the number of frame misses exceeds a predefined threshold. | 01-24-2013 |
20120317456 | Method and Apparatus for N+1 Packet Level Mesh Protection - Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN−1, to generate a codeword that includes the message symbols, m0 through mN−1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN−1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN−1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN−1, and the one or more check symbols through the linear feedback shift register. | 12-13-2012 |
20120278056 | Characterizing Performance of an Electronic System - In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level of at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter. | 11-01-2012 |
20120250732 | Technique for Searching for a Preamble Signal in a Spread Spectrum Signal Using a Fast Hadamard Transform - In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined. | 10-04-2012 |
20120239719 | Floating-Point Addition Acceleration - Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods. | 09-20-2012 |
20120238327 | SYSTEM AND METHOD FOR CONSERVING BATTERY POWER IN A MOBILE STATION - In one embodiment, a mobile station including a chassis having a display, a power reducer, a proximity sensor, and a microprocessor. The power reducer controls power consumption of the display. The proximity sensor is coupled to the chassis and causes the power consumption to be reduced when the display is within a predetermined range of an external object. The microprocessor is coupled to the proximity sensor and to the display and automatically activates the proximity sensor based on the mobile station receiving an incoming wireless telephone call. | 09-20-2012 |
20120225689 | Cordless Telephone With Digital Audio Player Capability - A cordless telephone which allows a user to play MP3 digital audio bit stream music, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC. | 09-06-2012 |
20120218986 | Line-Timing in Packet-Based Networks - In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities. | 08-30-2012 |
20120198316 | METHOD AND APPARATUS FOR STORING SURVIVOR PATHS IN A VITERBI DETECTOR USING SYSTEMATIC POINTER EXCHANGE - A survivor path memory is provided for a Viterbi detector. The survivor path memory comprises a plurality of columns, each associated with a different time step, and an input processor. Each column comprises a flip flop for storing one bit or portion of a bit sequence associated with a Viterbi state; and a multiplexer for each state controlled by a case signal indicating a time step, the multiplexer selecting a state from a previous time step, wherein an output of the multiplexer of a given state is connected to at least one data input of a flip flop of the given state. The input processor generates a control signal that exchanges one or more pointers based on a trellis structure, wherein each of the pointers points to one of the flip flops. | 08-02-2012 |
20120195354 | Serial Protocol for Agile Sample Rate Switching - The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the EA rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate. | 08-02-2012 |
20120135720 | CORDLESS TELEPHONE ACTIVE-CALL ENABLED INTERCOM - A method of using an intercom on a cordless telephone during an active call. The active call is put on hold while the intercom is in use. Once the call is re-activated, the intercom is shut off. This system may be designed for a cordless telephone with one handset or a plurality of handsets. | 05-31-2012 |
20120134481 | Retrieval of Deleted Voice Messages in Voice Messaging System - Apparatus and method to allow retrieval of voice messages deleted from the voice message memory of a voice messaging system. A voice messaging system such as a telephone answering device includes a deleted voice message memory for storing voice messages deleted from the voice message memory. The deleted voice messages stored in the deleted voice message memory are retrievable by the user for review subject to rules for permanent deletion of the deleted voice messages (e.g., after a period of time, when the deleted voice message memory approaches capacity, periodically, etc.) | 05-31-2012 |
20120128056 | METHOD AND APPARATUS FOR JOINT EQUALIZATION AND DECODING OF MULTIDIMENSIONAL CODES TRANSMITTED OVER MULTIPLE SYMBOL DURATIONS - A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. | 05-24-2012 |
20120128052 | CARRIER FREQUENCY ACQUISITION METHOD AND APPARATUS HAVING IMPROVED RELIABILITY FOR DETECTING CARRIER ACQUISITION OR LOSS THEREOF - A carrier signal acquisition technique is disclosed. An improved course carrier frequency offset algorithm is employed in conjunction with a conventional fine carrier frequency offset algorithm. The course carrier frequency offset algorithm estimates large offsets that are multiples of the carrier spacing that may occur at system startup. A spectral null is placed in the center of the transmit spectrum and is thereafter located in a received signal. The position of the spectral null provides an estimate of the local oscillator carrier offset. A frequency finite state machine (FSM) processes a number of metrics to ensure the reliability of the course carrier frequency offset and of transitions between acquisition and tracking modes. The frequency FSM will utilize the frequency offset (modin) generated by a MODSC algorithm provided one or more predefined thresholds are satisfied. | 05-24-2012 |
20120113853 | METHOD AND APPARATUS FOR BLIND TRANSPORT FORMAT DETECTION USING DISCONTINUOUS TRANSMISSION (DTX) DETECTION - Methods and apparatus are provided for blind transport format detection using Discontinuous Transmission (DTX) detection. According to one aspect of the invention, the transport format that was used to transmit information is determined by identifying a transition between a Discontinuous Transmission segment and a data segment included in the transmitted information; and determining the transport format based on a location of the transition of the Discontinuous Transmission segment. A cyclic redundancy check can optionally be performed for a plurality of possible transport formats, and then the step of identifying a transition can be to limited to those transport formats having a valid cyclic redundancy check. | 05-10-2012 |
20120106316 | Method and Apparatus for Cross-Talk Cancellation in Frequency Division Multiplexed Transmission Systems - A method and apparatus are disclosed for canceling cross-talk in a frequency-division multiplexed communication system. The disclosed frequency-division multiplexed communication system employs multiple carriers having overlapping channels and provides an improved cross-talk cancellation mechanism to address the resulting interference. Bandwidth compression is achieved using n level amplitude modulation in each frequency band. An FDM receiver is also disclosed that decomposes the received broadband signal into each of its respective frequency bands and returns the signal to baseband in the analog domain. Analog requirements are relaxed by removing cross-talk from adjacent RF channels, from image bands, and minimizing the performance degradation caused by In-phase and Quadrature-phase (I/Q) phase and gain mismatches in modulators and demodulators. The disclosed transmitter or receiver (or both) can be fabricated on a single integrated circuit. | 05-03-2012 |
20120076194 | RECEIVER EMPLOYING NON-PILOT REFERENCE CHANNELS FOR EQUALIZING A RECEIVED SIGNAL - In one embodiment, a receiver has a reference generator and a main equalizer. The reference generator equalizes a received signal using one or more pilot reference signals. Then, the reference generator decodes one or more predetermined data channels of the equalized signal, makes hard decisions on the data of each decoded channel, and regenerates the original coding sequence of each decoded channel. The main equalizer uses each re-encoded channel as an additional reference signal along with one or more pilot signals to equalize a time-delayed version of the received signal. In alternative embodiments, the receiver might also have a step-size generator which selects optimum step sizes from a look-up table based on the number of re-encoded channels and the power of those channels. The step size is then used by the main equalizer along with the re-encoded channels to equalize the time-delayed received signal. | 03-29-2012 |
20120069765 | VIRTUAL GATEWAY NODE FOR DUAL-MODE WIRELESS PHONES - In one embodiment, a virtual gateway mediates between a dual-mode subscriber device and an IP-based PBX. In particular, the virtual gateway includes a WLAN interface for communicating with the dual-mode subscriber device and a network interface (wired or wireless) for communicating with the IP-based PBX over the Internet. As such, the virtual gateway may relay voice and call control instructions between the dual-mode subscriber device and the IP-based PBX, and may provide the same call control functions to the dual-mode subscriber device provided by the call control processor in existing dual-mode phones. The embodiment further provides a dual-mode subscriber device suitable for operation with the virtual gateway. Because the dual-mode subscriber device does not require a call control processor, the battery life and cost of the device are significantly improved. | 03-22-2012 |
20120068762 | Method and Apparatus for Regulating a Power Supply of an Integrated Circuit - Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage. | 03-22-2012 |
20120030539 | ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION - Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous too bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing. | 02-02-2012 |
20120002744 | Methods and Systems for Transmitting an Information Signal in a Multiple Antenna Communication System - Methods and systems are provided for transmitting a plurality of information signals in a multiple antenna communication system. One or more information signals are coded using a plurality of coders to generate the plurality of coded information signals and an Inverse Fast Fourier Transformation is performed on each of the plurality of coded information signals to create a corresponding output signal. Each of the corresponding output signals are transmitted on a different antenna. Each of the plurality of coded information signals can optionally be separated into K signals, On the receiver side, a signal comprising K different frequencies is received on at least N receive antennas and a Fast Fourier Transformation is applied to each of the at least N received versions of the signal comprising K different frequencies to generate N*K low frequency signals. The N*K separate low frequency signals are then combined to recover a transmitted information signal, based on one or more transfer functions from each of a plurality of transmit antennas to each of the N receive antennas. | 01-05-2012 |
20110307852 | SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS - One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report. | 12-15-2011 |
20110299618 | MULTIPLE-BRANCH WIRELESS RECEIVER - A wireless receiver detects signals received at two or more antennas, with each antenna coupled to an input receive chain. A switch is employed to couple selected input receive chains to one or more corresponding output receive chains during listening, coarse-detection, and fine-adjustment modes. At least one channel selection filter (CSF) is employed in each output receive chain, and the receiver employs sub-ranging. During idle mode, one antenna's input receive chain is connected to two or more CSFs to detect the packet. When the packet is detected, during a coarse-adjustment mode, the CSFs are reconfigured to couple each antenna's input receive chain to a corresponding output receive chain using low-gain signals. During fine-adjustment mode, the various gains are adjusted to be either high- or low-gain to maintain signals within the dynamic range of the corresponding CSFs. | 12-08-2011 |
20110274266 | Method and Apparatus for Non-Disruptive Telecommunication Loop Condition Determination - In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook. | 11-10-2011 |
20110267096 | CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING - An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied. | 11-03-2011 |
20110250742 | CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES - Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. | 10-13-2011 |
20110243281 | PIPELINED DECISION-FEEDBACK UNIT IN A REDUCED-STATE VITERBI DETECTOR WITH LOCAL FEEDBACK - A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state. | 10-06-2011 |
20110222682 | Continuous Power Transfer Scheme for Two-Wire Serial Link - The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device. | 09-15-2011 |
20110206022 | QoS WIRELESS NETWORKING FOR HOME ENTERTAINMENT - A layer above the MAC and PHY layers of a wireless network employs a forward error correction (FEC) protocol extension with selective acknowledgement to reduce the likelihood of retries to enhance performance in, for example, home entertainment networking applications. In addition, certain system parameters of the wireless network are controlled so as to either i) align required bandwidth with particular sustainable channel parameters of the wireless network, or ii) modify the channel characteristics. One or more of three mitigation techniques might be employed with the FEC protocol extension to enhance maintenance of radio communication in the wireless network: Physical-layer Rate Adaptation, Dynamic Interference Avoidance, and Media-encoding Layer Adaptation. | 08-25-2011 |
20110201384 | Cordless Telephone with Digital Audio Player Capability - A cordless telephone which allows a user to play MP3 digital audio bit stream music, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC. | 08-18-2011 |
20110188489 | MULTI-CHANNEL RECEIVER WITH IMPROVED AGC - An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, a primary AGC loop controls an analog sub-receiver adapted to simultaneously receive multiple signals. Multiple digital demodulators, coupled to the sub-receiver, demodulate the multiple received signals. Multiple secondary AGC loops, one for each received signal, compensate for variations in demodulated signal strengths caused by the primary AGC loop. A feed-forward AGC compensation technique generates scalar control values for scaling the demodulated signals before the demodulated signals are processed by the secondary AGC loops. This at least partially compensates for gain variations caused by the primary AGC, reducing received signal drop-outs before the secondary AGC loops can compensate for the gain variations. Because of systemic delays in the sub-receiver and the demodulators, the scalar control values are independently timed to be coincident with the variations in the demodulated signal strengths caused by the primary AGC loop. | 08-04-2011 |
20110164756 | Cue-Based Audio Coding/Decoding - Generic and specific C-to-E binaural cue coding (BCC) schemes are described, including those in which one or more of the input channels are transmitted as unmodified channels that are not downmixed at the BCC encoder and not upmixed at the BCC decoder. The specific BCC schemes described include 5-to-2, 6-to-5, 7-to-5, 6.1-to-5.1, 7.1-to-5.1, and 6.2-to-5.1, where “.1” indicates a single low-frequency effects (LFE) channel and “.2” indicates two LFE channels. | 07-07-2011 |
20110163441 | PB-FREE SOLDER BUMPS WITH IMPROVED MECHANICAL PROPERTIES - A method of forming a semiconductor device is disclosed. A semiconductor substrate is provided that has a first contact and an undoped electroplated lead-free solder bump ( | 07-07-2011 |
20110163419 | ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS - An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology. | 07-07-2011 |
20110155418 | MITIGATION OF WHISKERS IN SN-FILMS - An electronic device includes a metallic conducting lead having a surface. A pre-solder coating over the surface consists essentially of tin and one or more dopants selected from Al or a rare earth element. | 06-30-2011 |
20110119566 | Method and Apparatus for Evaluating Performance of a Read Channel - Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | 05-19-2011 |
20110116565 | Method and Apparatus for Preamble Training with Shortened Long Training Field in a Multiple Antenna Communication System - Methods and apparatus are provided for communicating data in a multiple antenna communication system having N transmit antennas. According to one aspect of the invention, a header format includes a legacy preamble having at least one legacy long training field and an extended portion having at least N additional long training fields on each of the N transmit antennas, wherein one or more of the at least N additional long training fields are comprised of only one Orthogonal Frequency Division Multiplexing (OFDM) symbol. The extended portion optionally comprises one or more repeated OFDM symbols for frequency offset estimation. In one implementation, the extended portion comprises a first high throughput long training field comprised of two repeated OFDM symbols and N−1 high throughput long training fields comprised of only one OFDM symbol. In another variation, the extended portion comprises N high throughput long training fields comprised of only one OFDM symbol. | 05-19-2011 |
20110115338 | Methods of Fabricating a Membrane With Improved Mechanical Integrity - Methods for fabricating robust films across a patterned underlying layer's edges or steps are disclosed. The novel methods diminish the negative effects of electrode steps or edges on the integrity of a membrane. Thus, the methods are particularly applicable to membrane release technology. The height of the step or edge is eliminated or reduced to increase the mechanical integrity of the film. | 05-19-2011 |
20110055666 | RECEIVER FOR ERROR-PROTECTED PACKET-BASED FRAME - In one embodiment, a receiver for a frame of media packets employing the real-time transmission protocol (RTP) and forward error correction (FEC) is disclosed. The receiver comprises a packet buffer and an FEC decoder. After a packet is received by the packet buffer, the FEC decoder reads the packet and, as part of FEC processing, performs an XOR operation on the packet, without waiting for the entire frame (or, indeed, for any subsequent packet of the frame) to be received. The XOR operation results are accumulated until sufficient packets are received to reconstruct a missing packet in the frame. Because the XOR operations are performed immediately after a packet is received, without any delay from waiting for subsequent packets, the receiver has a very low latency, and the packet buffer may be relatively small. | 03-03-2011 |
20110044160 | FFT NUMEROLOGY FOR AN OFDM TRANSMISSION SYSTEM - An exemplary fast Fourier transform (FFT) numerology for an orthogonal frequency division multiple access (OFDMA) downlink transmission system is described. The exemplary FFT numerology reduces the FFT sampling rate for a given transmission bandwidth, thereby increasing the battery life of a UE. The FFT numerology increases robustness against Doppler spread, phase noise, and frequency offset, enabling operation in channels with high delay spread, such as occurs in mountainous regions. The described numerology might provide the following without altering standard sub-frame duration: increased intercarrier spacing; reduced FFT sampling frequency across the transmission bandwidths; reduced FFT size across all transmission bandwidths; increased number of OFDM symbols per sub-frame; and/or increased cyclic prefix length choices. | 02-24-2011 |
20110038134 | PREVENTING OR MITIGATING GROWTH FORMATIONS ON METAL FILMS - The disclosure, in one aspect, provides an electronics package | 02-17-2011 |
20110035318 | CREDIT AND DEBIT CARD TRANSACTION APPROVAL USING LOCATION VERIFICATION - In one embodiment, an online credit or debit card transaction is processed by transmitting purchase information, including price of the purchase item and card number, to the company that issued the card. In addition, the location from which the purchase is made is calculated, e.g., using a GPS device, and the location data is transmitted to the card issuer. The card issuer determines if the purchase meets certain specified approval requirements, such as whether the card holder has sufficient funds, the card has been reported missing, or card holder's personal information is correct. Further, the card issuer compares the location data to a number of predetermined purchase locations specified by the customer. If the location data matches one of the predetermined locations and the specified approval requirements are met, then the purchase is approved. | 02-10-2011 |
20110007048 | SYSTEM AND METHOD FOR USING PIXELS OF A DISPLAY DEVICE TO COMMUNICATE OPTICAL INFORMATION OVER A COMMUNICATIONS LINK - A system for communicating over an optical communications link is provided that uses at least one display pixel of a display device to transmit optical information bits and at least one sensor pixel of the display device to receive optical information bits. To transmit optical information bits, a controller of the display device causes the transmitter display pixel to switch between at least first and second optical display conditions to produce a modulated optical signal representative of one or more information bits. To receive optical information bits, the controller reads the electrical sense signal produced by the receiver sensor pixel and interprets the electrical sense signal read from the receiver pixel as corresponding to one or more information bits. | 01-13-2011 |
20110002062 | ANALOG MULTIPLEXER CIRCUITS AND METHODS - A sample and hold circuit is disclosed that provides longer hold times. An analog multiplexer circuit is also disclosed that exhibits low switch leakage. The analog multiplexer circuit comprises a shared node, a plurality of input circuits, a control input for selecting one or more of the plurality of input circuits, and an amplifier coupled to the shared node. Each input circuit comprises an input node, a primary input switch for selectively coupling an input to the input node, and a secondary input switch for selectively coupling the input node to the shared node, wherein the secondary input switch comprises one or more transistor switches. The parasitic drain and source diodes of one or more transistor switches in secondary input switch in a selected input circuit are coupled to a voltage that is distinct from an input signal of the selected input circuit. For input circuits not selected, the parasitic drain and source diodes of secondary input switch transistor switches are coupled to an output of the amplifier. | 01-06-2011 |
20100319967 | INHIBITION OF COPPER DISSOLUTION FOR LEAD-FREE SOLDERING - A device fabrication method, according to which a tin-copper-alloy layer is formed adjacent to a copper-plated pad or pin that is used to electrically connect the device to external wiring. Advantageously, the tin-copper-alloy layer inhibits copper dissolution during a solder reflow process because that layer is substantially insoluble in liquid Sn—Ag—Cu (tin-silver-copper) solder alloys under typical solder reflow conditions and therefore shields the copper plating from direct physical contact with the liquefied solder. | 12-23-2010 |
20100316155 | SCANNING AVAILABLE WIRELESS-DEVICE SERVICES IN MULTIPLE WIRELESS-RADIO TECHNOLOGY COMMUNICATION SYSTEMS - In one embodiment, a wireless device having two or more antennas. The wireless device substantially concurrently determines (a) using a first antenna, whether a first communications service is available for data transfer, and (b) using a second antenna, whether a second communications service is available for data transfer. After determining that at least one communications service is available for data transfer, the wireless device uses both antennas to transfer data using a selected communications service. | 12-16-2010 |
20100302175 | USER INTERFACE APPARATUS AND METHOD FOR AN ELECTRONIC DEVICE TOUCHSCREEN - Embodiments of the invention include a system for entering end user information into an electronic device. The system includes a display unit with a touchscreen having a plurality of locations. The touchscreen is configured to detect the presence of an end user object proximal to one of the touchscreen locations and to detect when an end user object makes contact with one of the touchscreen locations. The system also includes a controller configured to generate an audible sound indicative of the touchscreen location to which an end user object is proximal in response to the display unit detecting the presence of the end user object proximal to the touchscreen location. The controller also is configured to generate contact location information indicative of the touchscreen location with which an end user object makes contact in response to the display unit detecting the contact of the end user object on the touchscreen location. | 12-02-2010 |
20100293388 | PROTECTING SECRET INFORMATION IN A PROGRAMMED ELECTRONIC DEVICE - This disclosure provides a way for securely protecting secret information—for example, a secret key—in a programmed electronic device. A technique is disclosed for protecting secret information in a programmed electronic device that includes a non-trusted memory containing software, a data memory containing the secret information, and an access restriction logic unit that is adapted to allow or block access to the secret information wherein the secret information is adapted to be used for verifying the integrity of the software. In one embodiment, when starting up the programmed electronic device, the access restriction logic unit allows access to the secret information. Then the secret information is accessed for use in verifying the integrity of the software, and subsequently the access restriction logic unit blocks further access to the secret information. Embodiments of a semiconductor device and a programmed electronic device comprising similar features are also disclosed. | 11-18-2010 |
20100290513 | METHOD AND APPARATUS FOR INTEGRAL STATE INITIALIZATION AND QUALITY OF LOCK MONITORING IN A CLOCK AND DATA RECOVERY SYSTEM - Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied. | 11-18-2010 |
20100290497 | WAVEGUIDE DEVICE HAVING DELTA DOPED ACTIVE REGION - Embodiments of the invention include a laser structure having a delta doped active region for improved carrier confinement. The laser structure includes an n-type cladding layer, an n-type waveguide layer formed adjacent the n-type cladding layer, an active region formed adjacent the n-type waveguide layer, a p-type waveguide layer formed adjacent the active region, and a p-type cladding layer formed adjacent the p-type waveguide layer. The laser structure is configured so that a p-type dopant concentration increases across the active region from the n-type side of the active region to the p-type side of the active region and/or an n-type dopant concentration decreases across the active region from the n-type side of the active region to the p-type side of the active region. The delta doped active region provides improved carrier confinement, while eliminating the need for blocking layers, thereby reducing stress on the active region caused thereby. | 11-18-2010 |
20100289476 | METHOD AND APPARATUS FOR REGULATING A POWER SUPPLY OF AN INTEGRATED CIRCUIT - Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage. | 11-18-2010 |
20100275088 | LOW-LATENCY DECODER - In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated. | 10-28-2010 |
20100273301 | THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRNASISTORS FORMED ACCORDING TO THE METHOD - A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step. | 10-28-2010 |
20100270684 | CHIP IDENTIFICATION USING TOP METAL LAYER - An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin. | 10-28-2010 |
20100267431 | RECESSIBLE INTEGRATED POCKET CLIP FOR MOBILE DEVICES AND THE LIKE - In one embodiment, an apparatus comprising a housing and a fastener, such as a clip ( | 10-21-2010 |
20100264478 | METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE - A method is provided that includes forming a trench isolation structure in a dynamic random memory region (DRAM) of a substrate and patterning an etch mask over the trench structure to expose a portion of the trench structure. A portion of the exposed trench structure is removed to form a gate trench that includes a first corner formed by the substrate and a second corner formed by the trench structure. The etch mask is removed and the first corner of the gate trench is rounded to form a rounded corner. This is followed by the formation of an oxide layer over a sidewall of the gate trench, the first rounded corner, and the semiconductor substrate adjacent the gate trench. The trench is filled with a gate material. | 10-21-2010 |
20100253400 | Phase-Locked Loop (PLL) Having Extended Tracking Range - A method for extending a tracking range of a PLL includes the steps of: establishing an initial tracking window of the PLL, the tracking window having a first width associated therewith; and dynamically adjusting the tracking window of the PLL within an extended tracking range when a frequency of an input signal supplied to the PLL is outside of the tracking window, the extended tracking range having a second width associated therewith which is greater than the first width. | 10-07-2010 |
20100246695 | SIGNAL-POWERED INTEGRATED CIRCUIT WITH ESD PROTECTION - The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse. | 09-30-2010 |
20100245111 | END USER CONTROL OF MUSIC ON HOLD - In an exemplary embodiment, a wireless handset allows a user having a connection in an “on-hold” state to select one or more sources for play-out of media at a handset receiver while in the on-hold state, and then be signaled when the on-hold state is terminated. Such on-hold state might be indirectly detected, such as by detection of music-on-hold, or directly detected through on-hold notification. User selected media for play-out might be locally generated at the user's handset, or provided through a separate connection established between the wireless handset and the network. | 09-30-2010 |
20100238751 | Method and Apparatus for Increasing Yield in a Memory Device - An electronic circuit includes multiple circuit elements arranged into multiple distinct subdivisions, each subdivision having a separate voltage supply connection for conveying power to the subdivision. The electronic circuit further includes a controller including multiple outputs, each of the outputs being connected to a corresponding one of the voltage supply connections. When a given one of the subdivisions does not include a weak circuit element, the controller supplies a first voltage level to the given subdivision via the corresponding voltage supply connection. When the given subdivision includes at least one weak circuit element, the controller is operative to supply at least a second voltage level to the given subdivision via the corresponding voltage supply connection, the second voltage level being greater than the first voltage level. | 09-23-2010 |
20100237915 | METHOD AND APPARATUS FOR DIGITAL VCDL STARTUP - Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. | 09-23-2010 |
20100229035 | SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY - In accordance with exemplary embodiments, a multi-level flash memory employs error correction of systematic errors when reading multi-level flash memory. Error correction includes i) detection of each systematic error, ii) feedback of the systematic error to circuitry within the memory, and iii) subsequent adjustment within that circuitry to cause a correction of systematic error in the output signal of the multi-level flash memory. | 09-09-2010 |
20100221893 | METHOD FOR SEPARATING A SEMICONDUCTOR WAFER INTO INDIVIDUAL SEMICONDUCTOR DIES USING AN IMPLANTED IMPURITY - Provided is a method for separating a semiconductor wafer into individual semiconductor dies. The method for separating the semiconductor wafer, among other steps, may include implanting an impurity into regions of a semiconductor wafer proximate junctions where semiconductor dies join one another, the impurity configured to disrupt bonds in the semiconductor wafer proximate the junctions and lead to weakened regions. The method for separating the semiconductor wafer may further include separating the semiconductor wafer having the impurity into individual semiconductor dies along the weakened regions. | 09-02-2010 |
20100220638 | MAC-HS PROCESSING IN AN HSDPA-COMPATIBLE RECEIVER IN A 3G WIRELESS NETWORK - In one embodiment, a method for processing a series of MAC-hs protocol data units (PDUs) in an HSDPA-compatible (high-speed downlink packet access) receiver in a 3G wireless communication network, the method including: (a) receiving a MAC-hs PDU having: (i) a queue identification (QID), (ii) a transmission sequence number (TSN), and (iii) one or more MAC-d PDUs, (b) then disassembling the MAC-hs PDU (c) then distributing the one or more MAC-d PDU to a reordering queue indicated by the QID, and (d) then performing reordering processing for the corresponding reordering queue based on the TSN. Steps (a) and (b) are performed in a physical layer of the receiver. Steps (c) and (d) are performed in a data-link layer of the receiver. | 09-02-2010 |
20100220534 | Memory Device with Reduced Buffer Current During Power-Down Mode - A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device. | 09-02-2010 |
20100218003 | TRANSFORMERLESS POWER OVER ETHERNET SYSTEM - In one embodiment, a powered device (PD) ( | 08-26-2010 |
20100208716 | METHOD FOR SELECTING CONSTELLATION ROTATION ANGLES FOR QUASI-ORTHOGONAL SPACE-TIME AND SPACE-FREQUENCY BLOCK CODING - In one embodiment, the present invention generates a single rotation angle that may be used to maximize diversity of a quasi-orthogonal space-time block code that encodes groups of four data symbols. Two rotation angles corresponding the first two data symbols in a group are set to zero, and two rotation angles corresponding to the second two data symbols in a group are set to a single initial value. A codeword distance matrix is determined for each possible combination of codewords and erroneously decoded codewords that may be generated using the initial rotation angle, and the minimum of the determinants of these matrices is selected. This process is repeated to generate a plurality of minimum determinants, and, for each iteration, a different single rotation angle corresponding to the second two data symbols is used. Then, a single rotation angle is selected that corresponds to the maximum of the minimum determinants. | 08-19-2010 |
20100205462 | Systems and Methods for Modular Power Management - A modular, adaptive power management system includes a hard disk drive controller, a read channel module, a host interface controller and a power manager system. The hard disk controller includes a processor executing firmware, and the host interface controller provides for host access via a host interface. The system includes a power island register and an oscillation control register. Both registers are writable via the firmware and via the host interface. The hard disk controller, the interface controller, the read channel module and the power manager system are implemented across two or more distinct power islands and use two or more distinct clocks. Power to the two or more distinct power islands is at least in part controlled by the power manager system via the power island register, and the two or more distinct clocks are each controlled by the power manager system via the oscillation control register. | 08-12-2010 |
20100203928 | SOFTWARE BASED THERMAL CHARGING REGULATION LOOP - The present invention implements a software controlled thermal feedback system for battery charging circuitry in portable devices, specifically in cellular telephones. The charging hardware block is integrated into a mixed-signal analog base-band (ABB) circuit. In addition to standard function controls, integrated within the ABB are silicon temperature sensors used to monitor the temperature of any silicon components integrated on the ABB and detect any temperature change due to thermal heating. The temperature value is passed to the digital base band (DBB) circuit. Here, a microcontroller is programmed to perform power management functions relating to the ABB. Thermal control software, implemented on the DBB microcontroller, monitors the silicon temperature of the ABB and adjusts the power levels on the ABB accordingly to provide a controlled chip temperature. | 08-12-2010 |
20100203830 | Systems and Methods for Implementing Hands Free Operational Environments - Various systems and methods for implementing operational environments are disclosed. For example, some embodiments of the present invention provide hands free operational environments that include a routing device, an audio transmission device, an audio output device, and an audio input device. The routing device communicably couples the audio transmission device to one or more of the audio input device and the audio output device. The audio input device is operable to receive an audible command. The audible command is operable to cause an operation on at least one of the routing device, the audio output device, and the audio transmission device. | 08-12-2010 |
20100202610 | SYSTEMS AND METHODS FOR ENABLING CONSUMPTION OF COPY-PROTECTED CONTENT ACROSS MULTIPLE DEVICES - Various systems and methods for distributing rights managed content objects arc disclosed. For example, some embodiments of the present invention provide methods for distribution that include providing a mobile storage device that includes a wireless interface and a storage component maintaining a rights managed content object. A first request to provide the rights managed content object to a first mobile application device via the wireless interface is received, and a second request to provide the rights managed content object to a second mobile application device via the wireless interface is received. The rights managed content object is accessed from the storage component, and a digital rights management tool associated with the accessed content object is accessed. The rights managed content object is decrypted using the digital rights management tool, and streamed to both the first mobile application device and the second mobile application device via the wireless interface. | 08-12-2010 |
20100202498 | Compensating Transmission line to Reduce Sensitivity of Performance due to Channel Length Variation - Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold. | 08-12-2010 |
20100201000 | BOND PAD SUPPORT STRUCTURE FOR SEMICONDUCTOR DEVICE - According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent damage to such dielectric material, bond pads are fabricated with support structures that shield the dielectric material from destructive forces during wire bonding. In one implementation, the support structure includes a passivation structure between the bond pad and the topmost metallization layer. In another implementation, the support structure includes metal features between the topmost metallization layer and the next-topmost metallization layer. In both cases, the region of the next-topmost metallization layer under the bond pad can have multiple metal lines corresponding to different signal routing paths. As such, restrictions on the use of the next-topmost metallization layer for routing purposes are reduced compared to prior-art bond-pad support structures that require the region of the next-topmost metallization layer under the bond pad to be a single metal structure. | 08-12-2010 |
20100197264 | UPLINK CHANNEL ESTIMATION - In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions. | 08-05-2010 |
20100195777 | METHOD AND APPARATUS FOR IMPROVING LINEARITY IN CLOCK AND DATA RECOVERY SYSTEMS - Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal. | 08-05-2010 |
20100191943 | COORDINATION BETWEEN A BRANCH-TARGET-BUFFER CIRCUIT AND AN INSTRUCTION CACHE - A digital signal processor (DSP) having (i) a processing pipeline for processing instructions received from an instruction cache (I-cache) and (ii) a branch-target-buffer (BTB) circuit for predicting branch-target instructions corresponding to received branch instructions. The DSP reduces the number of I-cache misses by coordinating its BTB and instruction pre-fetch functionalities. The coordination is achieved by tying together an update of branch-instruction information in the BTB circuit and a pre-fetch request directed at a branch-target instruction implicated in the update. In particular, if an update of the branch-instruction information is being performed, then, before the branch instruction implicated in the update reenters the processing pipeline, the DSP initiates a pre-fetch of the corresponding branch-target instruction. | 07-29-2010 |
20100191913 | RECONFIGURATION OF EMBEDDED MEMORY HAVING A MULTI-LEVEL CACHE - A method of operating an embedded memory having (i) a local memory, (ii) a system memory, and (iii) a multi-level cache memory coupled between a processor and the system memory. According to one embodiment of the method, a two-level cache memory is configured to function as a single-level cache memory by excluding the level-two (L2) cache from the cache-transfer path between the processor and the system memory. The excluded L2-cache is then mapped as an independently addressable memory unit within the embedded memory that functions as an extension of the local memory, a separate additional local memory, or an extension of the system memory. | 07-29-2010 |
20100188987 | Power learning security in wireless routers - In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area. | 07-29-2010 |
20100185924 | Method and Apparatus for Evaluating Performance of a Read Channel - Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | 07-22-2010 |
20100177847 | DYNAMICALLY SELECTING METHODS TO REDUCE DISTORTION IN MULTI-CARRIER MODULATED SIGNALS RESULTING FROM HIGH PEAK-TO-AVERAGE POWER RATIOS - In one embodiment, an algorithm dynamically selects a method for reducing distortion in a multi-carrier modulated signal, such as an orthogonal frequency division multiplexing (OFDM) signal. The algorithm directs a transmitter to transmit peak-to-average power ratio (PAPR)-reduction signals over reserved tones (i.e., frequencies) if reserved tones are available. If reserved tones are not available, then the algorithm directs the transmitter to transmit PAPR-reduction symbols over free tones if free tones are available. If the free tones for this transmitter are used by adjacent transmitters, then interference-reduction techniques may be used to reduce interference with the adjacent transmitters. If reserved tones and free tones are not available, then the transmitter may use an alternative method to reduce distortion, such as successive clipping and filtering. In another embodiment, the transmitter may transmit PAPR-reduction symbols over both free and reserved tones, if available. | 07-15-2010 |
20100177832 | CALCULATING PEAK-TO-AVERAGE POWER RATIO REDUCTION FOR MULTI-CARRIER MODULATED SIGNALS USING A GRADIENT-DESCENT APPROACH - In one embodiment, the present invention is a method for reducing the peak-to-average power ratio (PAPR) of a multi-carrier modulated symbol, such as an orthogonal frequency division multiplexed (OFDM) symbol. The method first transforms a set of data symbols into a multi-carrier modulated symbol. The method then uses the multi-carrier modulated symbol and a gradient-descent algorithm to generate a set of symbols for PAPR-reduction tones. The data symbols and the PAPR-reduction symbols are then transformed to generate an updated multi-carrier modulated symbol. The PAPR-reduction symbols are iteratively updated until a terminating condition occurs (e.g., an acceptable PAPR is achieved for the multi-carrier modulated symbol). In another embodiment, the method uses the multi-carrier modulated symbol generated in the first step and a gradient-descent algorithm to generate an updated multi-carrier modulated symbol directly, where the need for transforming the data symbols and the PAPR-reduction symbols is eliminated for subsequent iterations. | 07-15-2010 |
20100176856 | METHOD AND APPARATUS FOR DETECTING AND ADJUSTING CHARACTERISTICS OF A SIGNAL - Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range. | 07-15-2010 |
20100174973 | EXTRACTION OF VALUES FROM PARTIALLY-CORRUPTED DATA PACKETS - In one embodiment, a method for processing data packets having a payload and a checksum, wherein the payload has a first portion of interest. If a received data packet fails a CRC check, then it is determined whether the first portion has a valid relationship with one or more previous first portions of one or more corresponding previous payloads of one or more corresponding previous data packets. If the relationship is valid, then the first portion is output. The method enables recovery of first portions of interest from corrupted data packets having transmission errors in other parts of the data packets, thereby potentially decreasing retransmissions and increasing throughput. | 07-08-2010 |
20100156454 | Hot-Electron Injection Testing of Transistors on a Wafer - A hot-carrier injection (HCI) test that permits rapid screening of integrated circuit wafers susceptible to possible HCI-induced failures is disclosed. A method is described that determines transistor stress voltages that results in a transistor HCI-induced post-stress drain current differing from a pre-stress drain current within a desired range. These stress voltages are determined using a wafer with acceptable HCI susceptibility. Additional wafers to be tested are first tested using a described method that uses the determined transistor stress voltages to quickly screen the wafers for HCI susceptibility and, if HCI susceptibility is found, then additional conventional HCI testing may be applied to the susceptible wafers. | 06-24-2010 |
20100155956 | FILL PATTERNING FOR SYMMETRICAL CIRCUITS - A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight circuit-matching requirements need to be met. | 06-24-2010 |
20100148329 | QUAD FLAT NO LEAD (QFN) INTEGRATED CIRCUIT (IC) PACKAGE HAVING A MODIFIED PADDLE AND METHOD FOR DESIGNING THE PACKAGE - A QFN IC package is provided that has all of the advantages of the typical QFN IC package, but in addition, has a paddle that is configured to facilitate trace routing and/or via placement on the PWB or PCB on which the IC package is mounted. By configuring the paddle as necessary or desired in order to facilitate routing and/or via placement, the overall size of the PWB or PCB can be reduced without sacrificing the thermal or electrical performance advantages that the paddle provides. In addition, the reduction in the overall size of the PWB or PCB results in reduced cost. | 06-17-2010 |
20100144389 | CORDLESS TELEPHONE WITH MP3 PLAYER CAPABILITY - A cordless telephone which allows a user to play MP3 digital audio bit stream music, a video game, either alone or with a user of another cordless telephone, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC. | 06-10-2010 |
20100142948 | FRAMER/MAPPER/MULTIPLEXOR DEVICE WITH 1+1 AND EQUIPMENT PROTECTION - In one embodiment, the present invention is a framer/mapper/multiplexor (FMM) device that can simultaneously (i) send protection copies of both its working incoming high-speed (e.g., STS-12) signal and incoming low-speed signals to a protection FMM device, and (ii) receive corresponding protection signals from the protection FMM device. Furthermore, the FMM device can select between working and protection signals at a switching level (e.g., STS-1) lower than the high-speed level, allowing for 1+1 APS/MSP protection and equipment protection at the board level, the device level, and at the STS-1 level. Yet further, four or more FMM devices can be configured so that all FMM devices can communicate with their corresponding protection FMM devices using a single, shared, 4-pin link (e.g., quad-OC-3 mode), and still select between working and protection signals at the switching level (e.g., STS-1). | 06-10-2010 |
20100138834 | APPLICATION SWITCHING IN A SINGLE THREADED ARCHITECTURE FOR DEVICES - A method and system for launching multiple applications simultaneously on a device under the control of application switching framework so that the operating system is only running one task for all the applications is provided. A single task is run under the control of an operating system. An application manager is run within the task. One or more applications are launched within the task under the control of the application manager. One of the applications is made the current application by switching, under user control, among the launched applications. A list of application descriptors is maintained for all the launched applications, and when switching, the application descriptor of one of the applications is used for displaying the application to a user on a screen. Each application descriptor contains forms of the launched applications. Each of the application descriptors contains a tree of forms with one root or parent form. A form represents an image to be displayed to the user. The image consists of text, pictures, bitmaps, or menus. | 06-03-2010 |
20100131819 | LDPC DECODER VARIABLE NODE UNITS HAVING FEWER ADDER STAGES - In one embodiment, the present invention is a variable node unit (VNU) of a low-density parity-check (LDPC) decoder. The VNU receives a soft-input value and w | 05-27-2010 |
20100125672 | PERSONAL BROADCAST AND CONTENT DELIVERY ENGINE - A communication system that enables a specified end-user device to obtain a media file corresponding to a delayed-play entry of a content-definition table prior to the scheduled play time. To deliver the media file to the end user, a service provider requests and receives the corresponding content from a content provider, generates the media file based on the received content, and temporarily stores the media file in a storage unit associated with the service provider. The service provider then breaks the media file into a plurality of data frames and transmits them to the end-user device during an appropriate delivery-opportunity window for storage in local storage unit (e.g., a hard drive) associated with the end-user device. At the play time, the service provider transmits to the end-user device a media-activation packet to initiate rendering thereat a copy of the media file assembled from the data frames stored in the local storage unit. | 05-20-2010 |
20100123962 | SINGLE-PASS DEFECT DETECTION FOR HARD-DISK DRIVE SYSTEMS - In one embodiment, defects are detected on the face of a hard-disk drive platter. A preamble, a sync mark, user or pseudorandom data, and a data pad are written to every sector on a track of the platter. Inter-sector gaps that separate consecutive sectors are overwritten with a fixed data pattern such that consecutive sectors are in phase lock with one another. After the track has been written, the track is read back and analyzed. Consecutive sectors are analyzed continuously without stopping. The preambles, sync marks, data pads, and overwritten inter-sector gaps are analyzed using suitable flaw-scan techniques. The user or pseudorandom data is analyzed using both data-integrity checks and suitable flaw-scan techniques. This process is repeated for all tracks on the disk, and defect detection is completed when all tracks have been analyzed. | 05-20-2010 |
20100120216 | TRANSISTOR FABRICATION METHOD - A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed. | 05-13-2010 |
20100120206 | INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR DISSIPATING HEAT IN AN INTEGRATED CIRCUIT PACKAGE - An IC package that is suitable for surface mounting arrangements includes a heat spreader device that is coupled to a bottom portion of the package below the IC die. Coupling the heat spreader device to the bottom portion of the package reduces or eliminates the possibility that placement of the heat spreader device will result in the molding compound bleeding on top of the heat spreader device, and delamination at the footings of the heat spreader device that can cause the package to delaminate, or “popcorn”. | 05-13-2010 |
20100107030 | LDPC DECODERS USING FIXED AND ADJUSTABLE PERMUTATORS - In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between the VNUs and CNUs using a number r of combinations of permutators, wherein each permutator combination includes (i) a cyclic shifter and (ii) a fixed, non-cyclic permutator. The cyclic shifters are capable of supporting a number p of different cyclic LDPC sub-matrices; however, when combined with different fixed permutators, the permutator combinations are capable of supporting up to r×p different LDPC sub-matrices. In other embodiments, the LDPC decoder may have fewer than r fixed permutators such that the LDPC decoder is capable of supporting between p and r×p different LDPC sub-matrices. | 04-29-2010 |
20100103010 | TWO-STEP SUB-RANGING ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR PERFORMING TWO-STEP SUB-RANGING IN AN ANALOG-TO-DIGITAL CONVERTER - A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC. | 04-29-2010 |
20100102418 | BIPOLAR DEVICE HAVING IMPROVED CAPACITANCE - The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns. | 04-29-2010 |
20100091832 | PIPELINED DECISION-FEEDBACK UNIT IN A REDUCED-STATE VITERBI DETECTOR WITH LOCAL FEEDBACK - A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interfence-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state. | 04-15-2010 |
20100090667 | OUTPUT COMPENSATED VOLTAGE REGULATOR, AN IC INCLUDING THE SAME AND A METHOD OF PROVIDING A REGULATED VOLTAGE - A voltage regulator, a method of regulating voltage and an IC including a voltage regulator. In one embodiment, the voltage regulator includes: (1) a DC precision amplifier configured to generate a DC precision signal based on a reference voltage and a regulated output of the voltage regulator and (2) a response amplifier, coupled in parallel with the DC precision amplifier, configured to generate an error signal based on the reference voltage and the regulated output, the response amplifier further configured to generate the regulated output based on a regulating signal comprised of the error signal and the DC precision signal. The DC precision amplifier may be a CMOS amplifier and the response amplifier may be a NPN amplifier. | 04-15-2010 |
20100088457 | CACHE MEMORY ARCHITECTURE HAVING REDUCED TAG MEMORY SIZE AND METHOD OF OPERATION THEREOF - A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address. | 04-08-2010 |
20100072547 | TECHNIQUES FOR CURVATURE CONTROL IN POWER TRANSISTOR DEVICES - Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit. | 03-25-2010 |
20100062800 | WIRELESS COMMUNICATIONS USING MULTIPLE RADIO ACCESS TECHNOLOGIES SIMULTANEOUSLY - In one embodiment, a wireless device communicates an uplink data stream to a wireless network using two radio access technologies (RATs) simultaneously. The wireless device has a host controller unit that segments the uplink data stream and provides each of the segmented portions to either a first baseband module corresponding to a first RAT or a second baseband module corresponding to a second RAT. The first baseband module modulates the data that it receives using the first RAT and provides the modulated data to a first radio frequency (RF) module. The second baseband module modulates the data that it receives using the second RAT and provides the modulated data to a second RF module. The first and second RF modules convert the modulated data to RF and provide the RF signals to first and second antennas, respectively. In alternative embodiments, more than two RATs are used simultaneously for communications. | 03-11-2010 |
20100057977 | REDUCED-POWER PROGRAMMING OF MULTI-LEVEL CELL (MLC) MEMORY - In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log | 03-04-2010 |
20100052174 | COPPER PAD FOR COPPER WIRE BONDING - An integrated circuit package comprising an integrated circuit that includes transistors coupled to copper interconnect structures. The integrated circuit package also comprises copper pads located on the integrated circuit and directly contacting uppermost ones of the copper interconnect structures. Each of copper pads has a thickness of at least about 2 microns. The integrated circuit package further comprises copper wires pressure-welded directly to the copper pads. | 03-04-2010 |
20100050060 | Path Comparison Unit For Determining Paths In A Trellis That Compete With A Survivor Path - A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path. | 02-25-2010 |
20100049896 | PEER-TO-PEER NETWORK COMMUNICATIONS USING SATA/SAS TECHNOLOGY - A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques. | 02-25-2010 |
20100046291 | Process and Temperature Tolerant Non-Volatile Memory - A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory. | 02-25-2010 |
20100045326 | THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS - The invention, in one aspect, provides a semiconductor device ( | 02-25-2010 |
20100044767 | STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS - A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer. | 02-25-2010 |
20100037188 | SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage. | 02-11-2010 |
20100033149 | DIGITALLY CONTROLLED CURRENT-MODE SWITCHED POWER SUPPLY - Disclosed is a current mode switched power supply. The current mode switched power supply includes a switching element and a power stage coupled to the switching element and configured to provide, in response to the switching of the switching element, an output voltage and a feedback voltage related to the output voltage. The current mode switched power supply also includes a digital control circuit connected to the switching element to digitally control the switching of the switching element. | 02-11-2010 |
20100032766 | Bipolar Junction Transistor with a Reduced Collector-Substrate Capacitance - A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance. | 02-11-2010 |
20100027611 | Adaptive equalization employing pattern recognition - In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fibre Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern. | 02-04-2010 |
20100027606 | Adaptive equalization employing pattern recognition - In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fibre Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern. | 02-04-2010 |
20100027592 | TECHNIQUE FOR SEARCHING FOR A PREAMBLE SIGNAL IN A SPREAD SPECTRUM SIGNAL USING A FAST HADAMARD TRANSFORM - In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined. | 02-04-2010 |
20100026378 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to implement a layout from the functional IC design that meets the performance objectives and (6) performing a timing signoff of the layout at the optimization target voltage. | 02-04-2010 |
20100023574 | FLOATING-POINT ADDITION ACCELERATION - Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods. | 01-28-2010 |
20100019579 | VERSATILE AND INTELLIGENT POWER CONTROLLER - The invention provides a monolithic, highly integrated power supply circuit capable of providing various voltages for circuits on an expansion card, either from a main supply source or an auxiliary supply source. The monolithic power supply circuit preferably includes two switching converters, two low-drop-out regulators, a standby regulator, a reset circuit, and a control circuit. An associated method for providing various voltages via a monolithic power supply circuit is also disclosed. | 01-28-2010 |
20100017687 | Method and Apparatus for N+1 Packet Level Mesh Protection - Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoding method is provided that assembles M-T data packets; appends a sequence number and a payload integrity check to each of the M-T data packets; and creates T protection packets having the sequence number and payload integrity check, wherein a payload for each of the T protection packets are formed from corresponding symbols in the M-T data packets. An error correction decoding method is also provided that receives a plurality of error-free packets and one or more packets having an error; and reconstructs the one or more packets having an error by applying block erasure decoding to said plurality of error-free packets, whereby one packet having an error can be reconstructed for each protection packet used to encode the received packets. | 01-21-2010 |
20100017569 | PCB INCLUDING MULTIPLE CHIPS SHARING AN OFF-CHIP MEMORY, A METHOD OF ACCESSING OFF-CHIP MEMORY AND A MCM UTILIZING FEWER OFF-CHIP MEMORIES THAN CHIPS - A PCB having fewer off-chip memories than chips, a MCM, and a method of accessing an off-chip shared memory space. In one embodiment, the method includes: (1) generating a memory request at a first chip of the printed circuit board, (2) transforming the memory request to a shared memory request and (3) directing the shared memory request to an off-chip shared memory space indirectly coupled to the first chip via a second chip of the printed circuit board. | 01-21-2010 |
20100017042 | SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL - A representative digital circuit of the invention has an on-chip, non-volatile memory, to which chip-specific speed-binning data that characterize performance of the digital circuit are written during production testing. During normal operation, the power controller that controls power-supply signals applied to the digital circuit reads the speed-binning data from the on-chip memory for use as input parameters for dynamic supply-voltage scaling, dynamic clock scaling, and/or adaptive power control that optimize (e.g., minimize) power consumption in the digital circuit. Advantageously over the prior art, the accuracy and efficiency of dynamic and/or adaptive power control arc improved because the chip-specific speed-binning data enable the power controller to better customize the power-management algorithm for the given digital circuit. | 01-21-2010 |
20090325353 | METHOD OF MANUFACTURING A LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) device, and an integrated circuit associated therewith. The method includes forming a lightly-doped source/drain region with a first dopant, the lightly-doped source/drain region located between first and second isolation structures. The method further includes creating a gate over the lightly-doped source/drain region. In one advantageous embodiment of the present invention, the method further includes diffusing a second dopant at least partially across the lightly-doped source/drain region and under the gate to form a first portion of a channel. | 12-31-2009 |
20090319875 | Path Metric Difference Computation Unit For Computing Path Differences Through A Multiple-Step Trellis - A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. The disclosed path metric difference computation unit computes differences between paths through a multiple-step trellis, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of the plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of the plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle. The disclosed path metric difference computation unit comprises one or more path metric difference generators for generating a path metric difference Δ | 12-24-2009 |
20090319874 | Reliability Unit For Determining A Reliability Value For At Least One Bit Decision - A reliability unit is disclosed for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis. | 12-24-2009 |
20090319282 | DIFFUSE SOUND SHAPING FOR BCC SCHEMES AND THE LIKE - In one embodiment, C input audio channels are encoded to generate E transmitted audio channel(s), where one or more cue codes are generated for two or more of the C input channels, and the C input channels are downmixed to generate the E transmitted channel(s), where C>E≧1. One or more of the C input channels and the E transmitted channel(s) are analyzed to generate a flag indicating whether or not a decoder of the E transmitted channel(s) should perform envelope shaping during decoding of the E transmitted channel(s). In one implementation, envelope shaping adjusts a temporal envelope of a decoded channel generated by the decoder to substantially match a temporal envelope of a corresponding transmitted channel. | 12-24-2009 |
20090319281 | CUE-BASED AUDIO CODING/DECODING - Generic and specific C-to-E binaural cue coding (BCC) schemes are described, including those in which one or more of the input channels are transmitted as unmodified channels that are not downmixed at the BCC encoder and not upmixed at the BCC decoder. The specific BCC schemes described include 5-to-2, 6-to-5, 7-to-5, 6.1-to-5.1, 7.1-to-5.1, and 6.2-to-5.1, where “0.1” indicates a single low-frequency effects (LFE) channel and “0.2” indicates two LFE channels. | 12-24-2009 |
20090313531 | Methods and Apparatus for Processing a Received Signal Using a Multiple-Step Trellis and Selection Signals for Multiple Trellis Paths - Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle). | 12-17-2009 |
20090311853 | CONTROLLING WARPING IN INTEGRATED CIRCUIT DEVICES - Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. | 12-17-2009 |
20090310795 | Noise Reduction By Mobile Communication Devices In Non-Call Situations - In a preferred embodiment, the invention is a mobile communication device having a digital signal processor (DSP), a speaker output node, a local audio source, and an analog front-end (AFE), wherein: (1) the DSP receives a first audio signal corresponding to sound captured by a microphone near a user of the device, (2) if the device is operating in a call mode, the DSP derives a background noise signal from the first audio signal, for subtraction from the first audio signal before transmission to the AFE, and (3) if the device is operating in a non-call mode, then the DSP (i) generates a speaker output signal which substantially corresponds to the first audio signal subtracted from a local audio signal provided by the local audio source and (ii) provides the speaker output signal to a speaker via the speaker output node. | 12-17-2009 |
20090304124 | REDUCED-COMPLEXITY MULTIPLE-INPUT, MULTIPLE-OUTPUT DETECTION - A wireless receiver detects signals generated with a multiple-input, multiple-output (MIMO) transmitter. The receiver applies maximum-likelihood detection (MLD) for soft-output signal detection, where an MLD exhaustive search across all candidate vectors is performed recursively by computing and accumulating the differences between, for example, the Euclidean metrics of consecutive candidate tests. Difference terms used for the accumulation are also calculated recursively. An ordering of candidates, such as by a triangular-waveform shaped ordering, is employed such that only one candidate variable is changed between any two consecutive candidate evaluations, leading to a reduced set of computations. | 12-10-2009 |
20090303933 | METHOD AND A TRANSCEIVER FOR TRANSMITTING DATA - The present invention provides a method for transmitting data and a transceiver. In one embodiment, the method includes: (1) generating data blocks of a data package in a first transceiver to transmit to a second transceiver, the first transceiver including a micro-controller coupled to a digital signal processor, (2) generating identification data in the first transceiver for the data blocks, wherein the identification data is an index of a list of the data blocks to be transmitted and each of the data blocks is transmitted with the index and (3) identifying the data blocks to be transmitted to the second transceiver based on the identification data, wherein the microcontroller employs the index to manage transmission of the data blocks. | 12-10-2009 |
20090296798 | HSDPA CO-PROCESSOR FOR MOBILE TERMINALS - In one embodiment, an HSDPA co-processor for 3GPP Release 6 Category 8 (7.2 Mb/s) HSDPA that provides all chip-rate, symbol-rate, physical-channel, and transport-channel processing for HSDPA in 90 nm CMOS. The co-processor design is scalable to all HSDPA data rates up to 14 Mb/s. The coprocessor implements an Advanced Receiver based on an NLMS equalizer, supports RX diversity and TX diversity, and provides up to 6.4 dB better performance than a typical single-antenna rake receiver. Thus, 3GPP R6 HSDPA functionality can be added to a legacy R99 modem using an HSDPA co-processor consistent with embodiments of the present invention, at a reasonable incremental cost and power. | 12-03-2009 |
20090296485 | DIFFERENTIAL FLASH MEMORY PROGRAMMING TECHNIQUE - The invention relates flash memory programming techniques. An object of the invention is to provide a flash memory programming technique avoiding problems of the known state of the art and in particular, saving a significant amount of time during the development and/or production phases of any equipment containing flash memory devices and also saving time during an updating or upgrading procedure of such an equipment already being in use. Accordingly, the invention proposes for programming a flash memory device to program only differences in information between data already stored in the flash memory device and new data to be stored. | 12-03-2009 |
20090292975 | METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING - Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information. | 11-26-2009 |
20090292974 | METHOD AND APPARATUS FOR ITERATIVE ERROR-ERASURE DECODING - Methods and apparatus are provided for improved iterative error-erasure decoding. A signal is decoded by obtaining a plurality of symbols associated with the signal and one or more corresponding reliability values; generating at least one erasure list comprised of L symbols and at least one shortened erasure list comprised of L′ symbols, where L′ is less than L; and constructing an erasure set by taking erasures from at least one of the erasure list and the shortened erasure list. A signal is also processed by generating one or more reliability values using a soft-output detector; generating an erasure list of symbols by comparing the reliability values to at least one reliability threshold value (or by sorting); and performing error erasure decoding using the erasure list. The size of the erasure list can optionally be adjusted using feedback information. | 11-26-2009 |
20090287462 | CHARACTERIZING PERFORMANCE OF AN ELECTRONIC SYSTEM - In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level at at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter. | 11-19-2009 |
20090281772 | SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS - One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report. | 11-12-2009 |
20090280585 | HIGH-DENSITY FIELD EMISSION ELEMENTS AND A METHOD FOR FORMING SAID EMISSION ELEMENTS - A method for forming high density emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes. The emission elements formed according to the present invention provide a more uniform emission of electrons. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. The reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image. | 11-12-2009 |
20090279686 | ECHO PATH CHANGE DETECTION IN TELECOMMUNICATIONS NETWORKS - In one embodiment, the present invention is a method for detecting an echo path change (EPC) in a telecommunications network. The method detects whether the effectiveness of echo cancellation of an echo canceller has decreased relatively significantly. Once a relatively significant decrease is detected, the method determines whether the decrease was an EPC or an inadvertent detection of double talk (DT). In particular, the method considers whether echo is effectively cancelled over a hangover period. Further, echo return loss (ERL) estimates are generated over the hangover period and compared to a lowest-possible ERL for the network. If both (1) echo cancellation is ineffective and (2) a sufficient number of ERL estimates are not below the worst-case ERL, then an EPC decision is made. If either (1) echo cancellation is effective or (2) a sufficient number of ERL estimates are below the worst-case ERL, then a DT decision is made. | 11-12-2009 |
20090279685 | DETECTION OF DOUBLE TALK IN TELECOMMUNICATIONS NETWORKS - In one embodiment, the presence of double talk (DT) is detected in a telecommunications network having a near-end user and a far-end user. The energies of both (1) a signal received from the far-end user by the near-end user and (2) a signal to be communicated from the near-end user to the far-end user are computed. An echo return loss (ERL) estimate is calculated based on the energy calculations, and a preliminary decision is made as to whether DT is present based on the ERL estimate and the energy calculations. If DT is detected, then a counter is set to a hangover value. If DT is not detected, then the counter is reduced. This process is repeated, and, for each iteration, a final decision as to whether DT is present is made based on the counter value. | 11-12-2009 |
20090274280 | RETRIEVAL OF DELETED VOICE MESSAGES IN VOICE MESSAGING SYSTEM - Apparatus and method to allow retrieval of voice messages deleted from the voice message memory of a voice messaging system. A voice messaging system such as a telephone answering device includes a deleted voice message memory for storing voice messages deleted from the voice message memory. The deleted voice messages stored in the deleted voice message memory are retrievable by the user for review subject to rules for permanent deletion of the deleted voice messages (e.g., after a period of time, when the deleted voice message memory approaches capacity, periodically, etc.) | 11-05-2009 |
20090254685 | TECHNIQUES FOR MANAGING PRIORITY QUEUES AND ESCALATION CONSIDERATIONS IN USB WIRELESS COMMUNICATION SYSTEMS - In one embodiment, a Universal Serial Bus (USB) system assigns a first priority level to a first USB endpoint and a second priority level that is lower than the first priority level to a second USB endpoint. The USB system has memory that stores first USB data packets corresponding to the first priority level and second USB data packets corresponding to the second priority level. The USB system also has a controller that manages transfers of (i) the first USB data packets to the first USB endpoint and (ii) the second USB data packets to the second USB endpoint. If the memory concurrently stores first and second USB data packets, then the controller determines an order for transferring the first and second USB data packets based on the second priority level being lower than the first priority level and/or detection of a starvation condition for the second endpoint. | 10-08-2009 |
20090253446 | METHOD AND DEVICE FOR PROVIDING A COMMUNICATION SESSION - A method and device for providing a communication session with a plurality of users. In one embodiment, the method includes: (1) transmitting an initiation message from the first terminal to the second terminal, the initiation message including a first address assigned to the first terminal, (2) dividing a display of the first terminal to simultaneously display text to be transmitted from the first terminal and text received from the second terminal, the dividing based on if there is text to be transmitted by the first terminal, (3) receiving the initiation message at the second terminal, (4) transmitting a first reply to the initiation message from the second terminal to the first terminal and (5) receiving the first reply at the first terminal. | 10-08-2009 |
20090239493 | Filter Switching System and Method - A communication system with variable filter bandwidth includes a first mixer circuit configured to receive a communication signal and shift the frequency range of the communication signal to a first frequency range. A second mixer circuit is configured to receive the same communication signal and shift the frequency range of the communication signal to a second frequency range. An activation circuit is coupled to the first and second mixer circuit so as to provide an activation signal that activates at least one of the mixer circuits. A plurality of filter circuits are provided such that each filter circuit is configured to receive a signal from a corresponding mixer circuit, when said corresponding mixer circuit is activated. | 09-24-2009 |
20090235116 | Systems and Methods for Regenerating Data from a Defective Medium - Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived form a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output. | 09-17-2009 |
20090212856 | ANALOG AMPLIFIER HAVING DC OFFSET CANCELLATION CIRCUIT AND METHOD OF OFFSET CANCELLATION FOR ANALOG AMPLIFIERS - An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier | 08-27-2009 |
20090209270 | LOCATION-BASED SEARCH-RESULT RANKING FOR BLOG DOCUMENTS AND THE LIKE - In one embodiment, a mobile communication device is adapted to provide geography-enhanced blog search results. In response to a blog-search query entered by a user, the mobile communication device is adapted to determine a current geographical location for the mobile communication device and a home location for the user. The mobile communication device is further adapted to provide the current location and home location information along with the search query parameters to a search engine. The search engine is adapted to provide results corresponding to blog posts that satisfy the parameters of the search query, wherein the search results are ranked based on at least one of (a) the geographic proximity of a blog post subject to the current location and (b) the geographic proximity of a blog post author's home location to the user's home location. | 08-20-2009 |
20090207926 | ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING USING SUBSYMBOL PROCESSING - In one embodiment, a transmitter converts digital input data into combined-OFDM signals and a receiver recovers data from the transmitted combined-OFDM signals. For transmission, digital data is mapped into data symbols using a commonly known modulation technique, such as QAM or DQPSK. The data symbols are subsequently divided into two or more groups according to a specified grouping pattern. Each group of data symbols is then converted into a separate OFDM subsymbol using IFFT processing. The OFDM subsymbols are then combined according to a specified combining pattern to create a combined-OFDM symbol. Combined-OFDM symbols are then prepared for transmission by affixing cyclic prefixes, converting the symbols to analog format, and performing spectral shaping of the analog signal. Upsampling may be employed to increase the signal bandwidth. In alternative embodiments, OFDM subsymbols may be combined using interleaving to create an interleaved-OFDM symbol. | 08-20-2009 |
20090199076 | ACKNOWLEDGEMENT MESSAGE MODIFICATION IN COMMUNICATION NETWORKS - A station for a communications network. In one embodiment, the station includes a decoder, a check processor, and a transmitter. The decoder is adapted to decode a received encoded data unit. The check processor is adapted to determine whether the encoded data unit has been correctly received. The transmitter is adapted to initiate, prior to the check processor completing the determination whether the encoded data unit has been correctly received, the transmission of an acknowledgment message comprising a frame having a plurality of different fields of data. The transmitter is adapted to modify the transmission of the acknowledgment message if the check processor determines that the data unit has not been correctly received. | 08-06-2009 |
20090196605 | Communications System with Symmetrical Interfaces and Associated Methods - A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs. The PLD send interface and the LLD send interface are substantially identical, and the PLD receive interface and the LLD receive interface are substantially identical to thereby define the symmetrical interfaces for the system. In view of the symmetrical interfaces, the PLD and the LLD may operate in a push-push configuration. Deskewing features are also provided. | 08-06-2009 |
20090190697 | DECODING TECHNIQUES FOR MULTI-ANTENNA SYSTEMS - In one embodiment, a wireless device for a wireless data communication system including the wireless device and a base station. The base station includes a plurality of first groups and a signal-processing unit. Each first group includes a receiver and at least one antenna connected to the receiver. The signal-processing unit includes memory and a processor adapted to process signals received by the first groups using a Maximum Likelihood Detection (MLD) method. The wireless device includes a plurality of second groups, each second group adapted to transmit a wireless signal to at least one first group via a corresponding communication channel. Each second group further includes a transmitter and at least one antenna connected to the transmitter. The signal-processing unit is adapted to store, in the memory, information corresponding to one or more transfer functions, each transfer function corresponding to transmission of a wireless signal from an antenna of the second groups to an antenna of the first groups. The transmitters and receivers are adapted to operate at essentially the same frequency or frequency band. Two or more of the communication channels are generated simultaneously. Each transmitter is adapted to modulate an information signal on a radio-frequency signal according to a Quadrature Amplitude Modulation (QAM) method to transmit QAM symbols. Each receiver is adapted to demodulate information signals from a received radio-frequency signal according to the QAM method. | 07-30-2009 |
20090180564 | DITHERING SCHEME USING MULTIPLE ANTENNAS FOR OFDM SYSTEMS - A ground- or roof-top-based repeater in an OFDM system uses multiple transmission antennas to transmit multiple identical OFDM signals. Dithering is performed by introducing a slight variable-frequency phase offset to all but one of the multiple identical transmitted OFDM signals. The effective overall channel is more dynamic and provides spatial diversity to minimize long periods of fading in fading subchannels of the OFDM signals when the receiver is in a slow moving or stationary situation. To overcome the additional cancellation problem that can occur when two or more of the transmitting antennas are (i) in a line-of-site position with the receiver and (ii) approximately the same distance from the receiver, a delay is deliberately introduced to make the delayed signals appear to be reflected signals. This delay will not negatively impact the OFDM receiver performance as long as the delay is within the guard interval used in the OFDM process. | 07-16-2009 |
20090177457 | DUTY CYCLE DISTORTION (DCD) JITTER MODELING, CALIBRATION AND GENERATION METHODS - A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal. | 07-09-2009 |
20090177442 | ON-CHIP VARIATION, SPEED AND POWER REGULATOR - Operational speed of an integrated circuit chip is measured using one or more speed measurement elements, such as ring oscillators, disposed at various regions of the chip. Each speed measuring element can include several ring oscillators, each corresponding to a different technology threshold voltage. The speed measurement data collected from the speed measurement elements can be used to determine on-chip variation (OCV). Circuitry either on the chip itself or, alternatively, external to the chip can adjust a chip operational parameter, such as core voltage or clock speed, in response to the speed measurement data. Speed measurement data can be read out of the chip through JTAG pins or an interface to an external host. | 07-09-2009 |
20090175395 | DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO - In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams. | 07-09-2009 |
20090175272 | ADAPTIVE ALGORITHM FOR REDUCING CHANNEL ZAPPING TIME IN MULTICAST MEDIA - A method and system for reducing channel changing time in multicast media, that can include the steps of receiving at least one of a plurality of available channels from a service provider at a residential gateway through a network, ranking the popularity of at least one of the available channels at a ranking engine connected to the residential gateway, and requesting to receive a number of the channels available from the service provider at the residential gateway based on the ranking. The rank is at least partly based on the data stored in the database. | 07-09-2009 |
20090172464 | METHOD AND APPARATUS FOR REPAIRING UNCORRECTABLE DRIVE ERRORS IN AN INTEGRATED NETWORK ATTACHED STORAGE DEVICE - In one embodiment, the invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause based on the disk error; processing one or more outstanding data storage or retrieval requests; and generating a new data storage request instructing the physical disk device array having the defective storage device to store valid data associated with the data storage or retrieval request corresponding to the disk device error, whereby the defective storage device is repaired. | 07-02-2009 |
20090172069 | METHOD AND APPARATUS FOR INTEGER DIVISION - The invention provides a method, arithmetic divider unit, and system for dividing a dividend D | 07-02-2009 |
20090172013 | Method to Improve Unfolding in Petri Nets - Petri net models, of systems, communication protocols, and software programs, which include place objects, transition objects, arcs, and initial markings, may be used for testing and verification. To reduce computations, a new unfolding process is performed on the net models. Two or more candidate buffer place interfaces are selected from the input net model. The input net is subdivided with a preliminary cut to form two subnets, wherein the preliminary cut passes through suitable candidate buffer place interfaces, objects of each of the subnets other than the suitable candidate buffer place interfaces are reachable from at least one initial marking, and the subnets do not include a mix of initial and non-initial marking places. Each of the two subnets are unfolded and then joined to form an unfolded net that is behaviorally equivalent to original input net model. The unfolded net is then stored in a storage unit. | 07-02-2009 |
20090170424 | LOW POWER MODE FOR SDARS RECEIVER - The present invention implements a method and system for receiving content in a Satellite Digital Audio Radio Service (SDARS) system. The method includes receiving a first signal stream in an SDARS receiver, the first signal stream including the SDARS content. The method further includes receiving a second signal stream in the SDARS receiver, the second signal stream including the SDARS content, the second signal stream being delayed relative to the first signal stream by a predetermined delay time. The method further includes combining the first signal stream and the second signal stream in to a composite signal that includes the SDARS content. The method further includes powering off a portion of the SDARS receiver, wherein the powering off of the portion of the SDARS receiver does not cause a disruption in the composite signal. | 07-02-2009 |
20090161904 | SPEAKERPHONE USING ADAPTIVE PHASE ROTATION - An improved speakerphone for a cellular telephone, portable telephone handset, or the like. In one embodiment, a receiver provides an audio signal, and a first phase-shifter phase-shifts the audio signal by a first phase-shift amount. A second phase-shifter phase-shifts the audio signal by a second phase-shift amount and drives a loudspeaker. A detector generates average and peak values of the first phase-shifted audio signal. A processor sets the first phase-shift amount to each one of a plurality of phase-shift amounts and calculates a corresponding average-to-peak ratio value from the peak and average values. The processor then selects one of the plurality of phase-shift amounts having a corresponding average-to-peak ratio value that meets at least one criteria (e.g., the largest one of the average-to-peak ratio values), and then sets the second phase-shift amount to be the same as the selected phase-shift amount. This enhances the perceived loudness of sound from loudspeaker. | 06-25-2009 |
20090161747 | NOISE PREDICTION-BASED SIGNAL DETECTION AND CROSS-TALK MITIGATION - In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment. | 06-25-2009 |
20090161459 | Dynamic Random Access Memory With Low-Power Refresh - A technique to reduce refresh power in a DRAM is disclosed. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Also disclosed is a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory. | 06-25-2009 |
20090160516 | DUTY CYCLE CORRECTION CIRCUIT FOR HIGH-SPEED CLOCK SIGNALS - The present invention implements an apparatus for correcting duty cycle distortion in high speed clock signals. The apparatus includes delay cells that delay each of first and second differential initial clock signals. The apparatus further includes a latch that generates an output clock signal based on the delayed first and second differential initial clock signals. The apparatus further includes a differential feedback buffer that converts the output clock signal into first and second differential feedback signals. The apparatus further includes a feedback circuit that adjusts the delay cells based on the first and second differential feedback signals. | 06-25-2009 |
20090154613 | TIMING-FREQUENCY OFFSET AND CARRIER-FREQUENCY OFFSET ESTIMATIONS FOR MULTI-CARRIER MODULATED SIGNALS USING PILOT TONES - In one embodiment, a demodulator demodulates a multi-carrier modulated signal having two pilot tones. The demodulator calculates a first phase angle for the first pilot tone and a second phase angle for the second pilot tone based on the time-domain multi-carrier modulated signal. A timing-frequency offset estimate is calculated using the first and second phase angles. Further, a fine carrier-frequency offset estimate is calculated for each pilot tone based on the corresponding phase angle and the timing-frequency offset estimate. Each fine carrier-frequency offset estimate is combined with a coarse estimate and weighted. The weighted estimates are then combined. In further embodiments, the timing-frequency offset estimate is weighted and combined with a weighted timing-frequency offset estimate generated using a cyclic prefix. In yet further embodiments, the weighted carrier-frequency offset estimates are combined with a weighted carrier-frequency offset estimate generated using a cyclic prefix. | 06-18-2009 |
20090152689 | Integrated Circuit Package for High-Speed Signals - An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel. | 06-18-2009 |
20090150754 | High Speed Syndrome-Based FEC Encoder and System Using Same - A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding. | 06-11-2009 |
20090150161 | SYNCHRONIZING PARAMETRIC CODING OF SPATIAL AUDIO WITH EXTERNALLY PROVIDED DOWNMIX - Embodiments of the present invention are directed to a binaural cue coding (BCC) scheme in which an externally provided audio signal (e.g., a studio engineering audio signal) is transmitted, along with derived cue codes, to a receiver instead of an automatically downmixcd audio signal. The cue codes are (adaptively) synchronized with the externally provided audio signal to compensate for time lags (and changes in those time lags) between the externally downmixed audio signal and the multi-channel signal used to generate the cue codes. If the receiver is a legacy receiver, then the studio engineered audio signal will typically provide a higher-quality playback than would be provided by the automatically downmixed audio signal. If the receiver is a BCC-capable receiver, then the synchronization of the cue codes with the externally provided audio signal will typically improve the quality of the synthesized playback. | 06-11-2009 |
20090147899 | CLOCK CALIBRATION IN SLEEP MODE - In one embodiment, an improvement is described for synchronization between devices in, e.g., a wireless network, wherein at least one device includes both a slow clock and a fast clock for different modes of operation. The fast clock for an active mode of operation is calibrated after a sleep mode of operation during which the slow clock is employed for device timing. Calibration employs a filter-based technique. Counts for the slow clock and for the fast clock are measured over a first interval, and the number of slow-clock counts is measured over a second interval. An estimate for the number of fast counts over the second interval is generated, filtered to reduce noise and error effects, and then employed to update the fast clock in the active mode of operation. | 06-11-2009 |
20090146687 | INTEGRATED CIRCUIT FEATURE DEFINITION USING ONE-TIME-PROGRAMMABLE (OTP) MEMORY - In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser. | 06-11-2009 |
20090141844 | Methods and apparatus for interface buffer management and clock compensation in data transfers - A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a clock recovered from the data stream. The RapidIO® data stream has embedded special characters, where a select sequence of embedded characters is a clock compensation pattern. A look ahead circuit is used to detect the clock compensation pattern early and generate a clock compensation indicator signal. The FIFO writes data and the associated clock compensation indicator signal in a clock compensation indicator bit in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the first clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface. A clock compensation control circuit generates a selection signal based on an AND of the almost empty signal and the clock compensation indicator bit associated with a data element read out of the FIFO and using the selection signal to control the multiplexer selection signal. | 06-04-2009 |
20090141725 | LINE-TIMING IN PACKET-BASED NETWORKS - In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities. | 06-04-2009 |
20090141723 | FRAME AGGREGATION - A packet network employs frame aggregation to reduce the number of physical-layer frames employed to transfer a given amount of user data. A packet network might employ physical (PHY) and medium access control (MAC) layers of a wireless local area network (WLAN) operating in accordance with one or more IEEE 802.11 standards. Frame aggregation combines several separate, higher-layer frames with user data into one PHY-layer frame, thus increasing the amount of user data per PHY-layer frame transmitted. Frame aggregation improves the efficiency by reducing both PHY-layer overhead and MAC-layer overhead. | 06-04-2009 |
20090130810 | Fabrication method - A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer. | 05-21-2009 |
20090129451 | Data Transmission Rate Adaptation in a Wireless Communication System - A method for controlling a data transmission rate of at least one transceiver in a wireless system, the transceiver including a transmitter and a receiver, the method including the steps of: determining a signal quality characteristic corresponding to a signal received at the receiver by measuring a difference between one or more reference constellation points and one or more received constellation points, the signal quality characteristic representing an estimation of signal degradation through the wireless communication channel; and modifying a data transmission rate of the transmitter as a function of the signal quality characteristic. The step of modifying the data transmission rate of the transmitter includes: determining lower and upper threshold levels representing reference minimum and maximum signal quality characteristics, respectively, corresponding to the data transmission rate; measuring a signal quality characteristic of the received signal; determining whether the measured signal quality characteristic is within the lower and upper threshold levels; maintaining the data transmission rate when the measured signal quality characteristic is between the lower and upper threshold levels; and increasing the data transmission rate when the measured signal quality characteristic is less than one or more lower threshold levels associated with one or more corresponding higher data rates. | 05-21-2009 |
20090128391 | SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period. | 05-21-2009 |
20090128389 | Multi-bit Per Stage Pipelined Analog to Digital Converters - Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches. | 05-21-2009 |
20090119554 | BACKPLANE EMULATION TECHNIQUE FOR AUTOMATED TESTING - The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable. | 05-07-2009 |
20090116637 | METHOD FOR SEAMLESS NOISE SUPPRESSION ON WIDEBAND TO NARROWBAND CELL SWITCHING - A method for seamless noise suppression on wideband to narrowband cell switching is described. In one embodiment the method includes applying noise suppression to a telephone signal using a first noise suppressor while operating a telephone in a first operating mode, the first noise suppressor generating an estimate of a noise components of the telephone signal; switching the telephone from the first operating mode to a second operating mode; providing the estimate of the noise component as an input to a second noise suppressor different from the first noise suppressor, when the switching step is performed; and applying noise suppression to the telephone signal using the second noise suppressor by using the estimate of the noise component provided by the first noise suppressor when the switching step is performed. | 05-07-2009 |
20090116134 | Methods and Apparatus for Controlling Write Driver Current - A hard disk drive write driver circuit is described that can change the output impedance of the write driver by use of a lookup table of control values. A control value is selected from the lookup table by using an address based on a dynamic system variable and a program controlled value. The dynamic system variable is converted to a digital representation. The digital representation and a portion of the program controlled value are used as an address to the lookup table to select a control value. The write driver is responsive to the selected control value to control overshoot current. A method to digitally program the output impedance of a preamp write driver based on realistic operating data is also discussed. An additional approach to controlling overshoot current in a write driver through digital control of overshoot duration is also described. | 05-07-2009 |
20090115536 | PROGRAMMABLE LINEAR TRIMMING METHOD AND SYSTEM FOR PHASE LOCKED LOOP CIRCUIT CALIBRATION - The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process. | 05-07-2009 |
20090113320 | Method and Apparatus for Generating a Graphical Interface to Enable Local or Remote Access to an Application Having a Command Line Interface - A method and apparatus are disclosed for generating a graphical interface for software applications having a command line interface to enable local or remote access of such software applications in a uniform manner without regard to the location of the remote application. The location and syntax of a new software application, and any required environment settings, are specified in response to a sequence of queries. The specifications for each software application is parsed to generate a graphical client interface listing the available software applications and enabling remote access to such software applications. A desired software application is selected by a user from the client interface and the user specifies any necessary parameters for the selected software application. An input file is transferred from the client to the remote server where the selected software application is located. Any output or log files are returned to the client, for example, using the FTP protocol. The client interface permits distributed processing through a web interface and enables software applications to be accessed and used from a remote location. | 04-30-2009 |
20090113166 | HASHING METHOD FOR NAND FLASH MEMORY - In accordance with exemplary embodiments, a flash memory, such as a NAND flash memory, selectively updates blocks based on hash values associated with the blocks, wherein the hashing codes are generated for each block from the software image to be programmed into the flash memory. Selectively updating blocks in accordance with an embodiment of the present invention might reduce re-programming time and potentially destructive pre-mature aging of cells in the flash memory. | 04-30-2009 |
20090113141 | MEMORY PROTECTION SYSTEM AND METHOD - A shared memory controller is provided for controlling access to a shared memory by a plurality of processors. At least one device includes a storage area for storing a respective address range for each of a plurality of memory regions. The at least one device further includes a permission table containing, for each of the plurality of memory regions, read and write permission data for each of the plurality of processors. A memory fault detector is coupled to the at least one device and has an input for receiving a memory access request including a memory address, a processor identification and a read/write indicator. The memory fault detector includes logic for determining whether a memory access according to the memory access request would conflict with the read and write permission data in the permission table. | 04-30-2009 |
20090112603 | CONTROL OF A NON-ACTIVE CHANNEL IN A MULTI-CHANNEL RECEIVER - In one embodiment, a satellite radio receiver is capable of simultaneously processing (i) a first radio channel that is playing on a first speaker and (ii) a second radio channel, different from the first radio channel, that is not playing on the first speaker. The second radio channel can simultaneously be playing on a second speaker, be recorded onto a non-volatile memory, and/or have its processing modified. A user can control the satellite radio receiver using vocal commands, while the first channel is playing on the first speaker. The radio receiver has a microphone connected to a voice-recognition command interpreter that includes an interfering-sound canceller, which reduces sounds interfering with the vocal commands, and a command-recognition module, which recognizes vocal commands and provides a control signal to a multi-channel control processor, which processes and controls the first and second radio channels, received from corresponding decoders connected to a satellite radio receiver antenna. | 04-30-2009 |
20090111518 | INTERFACE FOR CELLULAR AND LOCAL NON-CELLULAR COMMUNICATIONS - Interface apparatus supports communications between a cellular network and a local non-cellular network, such as a Bluetooth, cordless phone, or PBX network. In an exemplary embodiment, the interface apparatus connects a conventional cellular phone to the base of a conventional cordless phone set. By placing the cordless phone, interface apparatus, and cordless phone base at a location of acceptable cellular signal strength, a user may communicate with the cellular network via the cordless phone set using the cordless phone's handset, even in locations of low cellular signal strength. The orientation of the interface apparatus may be (manually or automatically) controlled using a motorized base to optimize reception of cellular signals. | 04-30-2009 |
20090111395 | PROVIDING A VIRTUAL LOCAL CHANNEL IN A SATELLITE BROADCAST SYSTEM - In one embodiment, a receiver for providing a virtual local channel in a broadcast radio system that transmits a plurality of sets of local content corresponding to a plurality of different geographic regions is disclosed. The receiver includes a detector (e.g., | 04-30-2009 |
20090110047 | DEMODULATOR WITH CONFIGURABLE ADAPTIVE EQUALIZER - An improved multi-channel receiver for satellite broadcast applications or the like. In an exemplary embodiment, the receiver has an adaptive equalizer configurable to operate with QPSK or 8PSK modulated signals. In the equalizer, a slicer table memory responsive to an 8-level quantizer (slicer) and a select signal is configured to map the output of the quantizer into QPSK or 8PSK symbol coordinates depending on whether the QPSK or the 8PSK signal is being received. The slicer table memory may be loaded with the symbol coordinates calculated from data in the 8PSK signal. A pattern matcher determines if the 8PSK or the QPSK signal is being received and asserts the select signal to configure the slicer table memory accordingly. | 04-30-2009 |
20090108898 | METHODS AND APPARATUS FOR IMPROVED PHASE SWITCHING AND LINEARITY IN AN ANALOG PHASE INTERPOLATOR - Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal. | 04-30-2009 |
20090108359 | A SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREFOR - The present invention provides a semiconductor device, and an integrated circuit including the semiconductor device. The semiconductor device, in one embodiment, includes: (1) a gate structure located over a substrate, the gate structuring including a gate dielectric and gate electrode; (2) source/drain regions located within the substrate proximate the gate structure, (3) a multi layer etch stop located over the substrate, wherein the etch stop has a first insulative layer and a second silicon-rich nitride layer located over the first insulative layer, (4) a dielectric layer located over the etch stop, the dielectric layer having an opening formed therein that extends through at least a portion of the multi layer etch stop, (5) a conductive plug located within the opening and electrically contacting the gate electrode and one of the source/drain regions, and (6) an insulative spacer located between the conductive plug and the second silicon-rich nitride layer. | 04-30-2009 |
20090100668 | INDUCTOR FORMED IN AN INTEGRATED CIRCUIT - An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line. | 04-23-2009 |
20090092181 | SCALING EQUALIZER COEFFICIENTS AFTER AUTOMATIC GAIN CONTROLLER GAIN ADJUSTMENTS - In one embodiment, a receiver comprises an automatic gain controller (AGC), an equalizer, a controller, and a register interface. The AGC makes gain adjustments to compensate for changes in the average amplitude of a received signal. The equalizer has a coefficient updater that calculates coefficients and a finite impulse response (FIR) filter that applies the coefficients to the received signal to generate an equalized signal. During gain adjustments by the AGC, the register interface provides a weight freeze signal to the coefficient updater, which subsequently freezes the updating of the coefficients for a freeze duration period. Then, register interface provides a scaling factor, generated by the controller based on the size of the gain adjustment, to the coefficient updater. At the end of the freeze period, coefficient updater applies the scaling factor to the coefficients and unfreezes the coefficient updating. | 04-09-2009 |
20090092101 | WIRELESS LAN WITH CHANNEL SWAPPING BETWEEN DFS ACCESS POINTS - The present invention enhances the dynamic frequency selection 9DFS) algorithms used in Wireless LANs by adding a channel swapping mechanism. The aim of the traditional DFS algorithm is to dynamically select channels in a wireless LAN in such a way that the best performance is achieved. However, not always the optimal channel selection is achieved. This invention describes an addition to the DFS algorithm in such a way that two APs can decide to swap channels instead of one AP switching to another channel. To avoid the problem of sub-optimal channel selection, a requesting AP sends Swap Requests to other APs in order to sense the willingness of other APs to swap channels with the requesting AP. | 04-09-2009 |
20090092038 | TIMING-OFFSET ESTIMATION IN MODULATED SIGNALS USING WEIGHTED CORRELATION VALUES - In one embodiment, a timing-offset estimator calculates a correlation value for each sample of an OFDM signal having a cyclic prefix for each OFDM symbol. The correlation value is provided to a tapped delay line that applies a separate weight to each of 2V correlation values, where V is the length of the cyclic prefix and the weights are based on a triangular weighting scheme that increases linearly from the first value, peaks at the V | 04-09-2009 |
20090085642 | PASSIVE MIXER HAVING TRANSCONDUCTANCE AMPLIFIER WITH SOURCE DEGENERATION CAPACITANCE - A passive mixer includes a transconductance amplifier having a source degeneration capacitance. The transconductance amplifier has an input for receiving an input signal and an output for outputting a current signal. A multiplier is provided for mixing a local oscillator signal with the current signal so as to provide an output signal at an output of the passive mixer. A capacitive load is connected to the output of the passive mixer. | 04-02-2009 |