Semiconductor Manufacturing International (Shanghai) Corporation Patent applications |
Patent application number | Title | Published |
20160133744 | TRANSISTOR AND FABRICATION METHOD THEREOF - A method for forming transistors includes providing a substrate having at least a dummy gate structure having at least dummy gate layer; forming a first dielectric layer on the substrate; thinning the first dielectric layer with a pre-determined depth to cause a top surface of the dielectric layer to be lower than a top surface of the dummy gate structure and expose top portions of side surfaces of the dummy gate structure; forming a stress layer on the exposed portions of the side surfaces of the dummy gate structure; forming a second dielectric layer on the thinned first dielectric layer; removing the dummy gate layer to form an opening with an enlarged top size caused by releasing stress in the stress layer previously formed on the exposed portions of the side surfaces of the dummy gate structure; and forming a gate electrode layer in the opening. | 05-12-2016 |
20160126338 | TRANSISTOR AND FABRICATION METHOD THEREOF - A method for forming transistors is provided. The method includes providing a substrate having a base and at least a fin on the base; and forming a gate layer on the fin, the gate layer has first side surfaces parallel to a longitudinal direction of the fin and second side surfaces perpendicular to the fin. The method also includes forming a protective layer on the first side surfaces of the gate layer to protect a vertex of the top of the gate layer from having EPI particles; and forming sidewall spacers on side surfaces of the protective layer and the second side surfaces of the gate layer. Further, the method includes forming a stress layer in the fin at both sides of the sidewall spacers and the gate layer. | 05-05-2016 |
20160118338 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a plurality of first through holes exposing the surface of the substrate by etching the dielectric layer; forming first conductive vias by filling the plurality of first through holes using a first metal material and first conductive lines on the first conductive vias also using the first metal material; forming a plurality of second through holes exposing the surface of the substrate by etching the dielectric layer; and forming second conductive vias by filling the plurality of second through holes using a second metal material, different from the first metal material, and second conductive lines over the second conductive vias also using the second metal material, wherein the second metal material has a different anti-electromigration ability from the first metal material. | 04-28-2016 |
20160116332 | LIGHT SOURCE AND PHOTOLITHOGRAPHY APPARATUS CONTAINING THE SAME, CALIBRATING APPARATUS AND METHOD - The present disclosure provides an extreme ultraviolet (EUV) light source. The EUV light source includes a droplet array with a plurality of nozzles arranged along a straight scanning direction, the plurality of nozzle sequentially and intermittently ejecting droplets downward to a radiating position; a laser source configured to generate at least two laser beams and scan the at least two laser beams along the straight scanning direction, the at least two laser beams alternately bombarding droplets arriving at the radiating position to form EUV light; and a condenser with a condenser mirror having a reflective ellipsoidal surface, configured to collect the EUV light and converge collected EUV light at a center of focus. | 04-28-2016 |
20160113101 | EUV LIGHT SOURCE AND EXPOSURE APPARATUS - An extreme ultraviolet (EUV) light source is provided. The EUV light source comprises a spray nozzle array having a plurality of spray nozzles configured to spray a plurality of rows of droplets to an irradiating position. The EUV light source also includes a laser source having a first reflective mirror and a second reflective mirror configured to generate a first laser beam and a second laser beam, and to cause the first laser beam and the second laser beam to sequentially bombard the plurality of droplets arriving at the irritating position to generate EUV light with increased output power. Further, the EUV light source includes a light focusing device a light focusing device comprising a first partial focusing mirror and a second partial focusing mirror configured to perform a rotating scanning to collect EUV light and focus the collected EUV light at a central focusing point. | 04-21-2016 |
20160113100 | EUV LIGHT SOURCE AND EXPOSURE APPARATUS - An extreme ultraviolet (EUV) light source is provided. The EUV light source comprises a spray nozzle array having a plurality of spray nozzles configured to spray a plurality of rows of droplets to an irradiating position; a laser source configured to generate a first laser beam and a second laser beam and cause the first laser beam and the second laser beam to alternately bombard the rows of droplets to generate EUV light with increased output power; a focusing mirror having at least two first sub-focusing mirrors and at least two second sub-focusing mirrors; and a first driving device having at least two first sub-driving device and at least two second sub-driving device, each of first driving devices driving one of the first sub-focusing mirrors and each of the second sub-driving devices driving one of the second sub-focusing mirrors. | 04-21-2016 |
20160111516 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate. | 04-21-2016 |
20160111368 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings. | 04-21-2016 |
20160111329 | INTERCONNECT STRUCTURE AND FABRICATION METHOD THEREOF - A method for forming an interconnect structure is provided. The method includes providing a substrate with a surface; and forming a metal layer covering the surface of the substrate and with a desired grain size to reduce grain boundary scattering of the interconnect structure subsequently formed with the metal layer. The method also includes etching the metal layer to form a plurality of metal lines on the surface of the substrate and a plurality of metal pillars on each of the plurality of the metal lines of the interconnect structure; and forming a dielectric layer covering the surface of the substrate, surfaces of the metal lines, and side surfaces of the metal pillars. | 04-21-2016 |
20160093601 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor structure and fabrication methods are provided. The semiconductor structure includes a first wafer having a first metal layer therein and having a first material layer thereon, and a second wafer having a second metal layer therein and having a second material layer thereon. An alignment process and a bonding process are preformed between the first wafer and the second wafer, such that the first material layer and the second material layer are aligned and in contact with one another to provide a first alignment accuracy between the first metal layer and second metal layer. A heating process is performed on the first material layer and the second material layer to melt the first material layer and the second material layer to provide a second alignment accuracy between the first metal layer and second metal layer. The second alignment accuracy is greater than the first alignment accuracy. | 03-31-2016 |
20160093574 | PHOTOLITHOGRAPHY ALIGNMENT MARK STRUCTURES, SEMICONDUCTOR STRUCTURES, AND FABRICATION METHOD THEREOF - A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; thrilling a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center along a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer: and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer. | 03-31-2016 |
20160091436 | METHOD AND SYSTEM FOR OPTICAL MEASUREMENTS - The present disclosure includes a method for optical measurements. The method includes providing a substrate with a structure for optical measurement on the substrate; and illuminating a light spot on the structure for optical measurement to obtain a measured light scattering spectrum. The method also includes performing a first matching process to obtain a plurality of matching standard optical scattering spectra and a plurality of first matching degrees, each standard optical scattering spectrum corresponding to one first matching degree; obtaining a plurality of combined optical scattering spectra based on the plurality of matching standard optical scattering spectra; and performing a second matching process to obtain a plurality second matching degree, each corresponding to one combined optical scattering spectrum. | 03-31-2016 |
20160087075 | TRANSISTOR DEVICE AND FABRICATION METHOD - The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance. | 03-24-2016 |
20160086857 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - The present disclosure provides a method for fabricating semiconductor devices. The method includes providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode film; forming at least one pattern layer on the gate electrode pattern film; and using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern layer including a hard mask layer and a silicon layer, and sidewalls of the silicon layer in a direction perpendicular to a first direction having a first poly line width roughness. The method also includes performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction. | 03-24-2016 |
20160083248 | MEMS DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for forming micro-electro-mechanical-system (MEMS) devices. The method includes providing a plurality of wafers; bonding a front surface of at least a first wafer onto a front surface of a second wafer; trimming an edge of and thinning the at least first wafer after the at least first wafer is bonded onto the second wafer; and bonding a first supporting plate onto a front surface of a third wafer. The method further includes thinning a back surface of the third wafer and forming alignment marks on a thinned back surface of the third wafer; bonding a second supporting plate onto the thinned back surface of the third wafer according to the alignment marks; and removing the first supporting plate and bonding the at least first wafer onto the third wafer according to the alignment marks to form a stack structure. | 03-24-2016 |
20160064657 | PHASE CHANGE RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A method for forming a phase change random access memory is provided. The method includes providing a substrate having a surface; and forming a dielectric layer on the surface of the substrate. The method also includes forming a through-hole penetrating through the dielectric layer; and forming an adhesion layer on inner surface of the through-hole. Further, the method includes forming a metal layer doped with inorganic ions on the adhesion layer to reduce over-etching of the metal layer and increase heating efficiency of the metal layer on the surface of the adhesion layer; and forming a phase change layer on the dielectric layer, the adhesion layer and the doped metal layer. | 03-03-2016 |
20160064552 | LDMOS TRANSISTOR AND FABRICATION METHOD THEREOF - A LDMOS transistor includes a semiconductor substrate with a first doping type; a plurality of first trenches formed in the semiconductor substrate; a wave-shaped drift region with an increased conductive path and a second doping type formed on the semiconductor substrate between adjacent first trenches and the semiconductor substrate exposed by side and bottom surfaces of the first trenches; a first shallow trench isolation (STI) structure formed in each of the first trenches; a body region with the first doping type formed in semiconductor substrate at one side of the drift region; a gate structure formed over portions of the body region, the drift region and the first STI structure most close to the body region; a source region formed in the body region; and a drain region formed in the drift region at one side of the first STI structure most far away from the body region. | 03-03-2016 |
20160064522 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer. | 03-03-2016 |
20160064506 | SEMICONDUCTOR DEVICE HAVING METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor device including a metal gate structure and formation method thereof. The semiconductor device includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a trench. A diffusion barrier layer is disposed over a bottom surface and sidewall surfaces of the trench in the dielectric layer. The diffusion barrier layer includes at least a titanium-nitride stacked layer. The titanium-nitride stacked layer includes a TiNx layer disposed over the bottom surface and the sidewall surfaces of the trench, a TiN layer on the TiNx layer, and a TiNy layer on the TiN layer, x<1 and y>1. A metal gate is filled in the trench and disposed on the diffusion barrier layer. | 03-03-2016 |
20160064379 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHODS THEREOF - A method for forming FinFETs includes, sequentially, providing a substrate; forming a plurality of fins on a surface of the substrate; forming a gate structure overlying on at least one of the plurality of fins; forming a barrier layer covering top and side surfaces of the gate structures, and top and side surfaces of the plurality of fins; performing a radical oxidation process to convert a top portion of the barrier layer to a passive layer to form a remaining barrier layer and to cause the top surfaces of the fins to be flat after subsequent etching processes; performing an etch-back process on the passive layer to form passive sidewalls on side surfaces of the portions of the remaining barrier on the side surfaces of the fins; and removing portions of the remaining barrier layer on the top surfaces of the fins by a wet etching process using the passive sidewalls as an etching mask. | 03-03-2016 |
20160064290 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench. | 03-03-2016 |
20160064289 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for forming a semiconductor structure includes sequentially providing a semiconductor substrate having NFET regions and NFET regions; forming an insulation layer on the semiconductor substrate; forming a sacrificial layer on the insulation layer; forming first trenches in the PFET regions, and second trenches in in the NFET regions; forming a third trench on the bottom of each of the first trenches and the second trenches; forming a first buffer layer in each of the first trenches and the second trenches by filling the third trenches; forming a first semiconductor layer on each of the first buffer layers in the first trenches and the second teaches; removing the first semiconductor layers in the second trenches; forming a second buffer layer with a top surface lower than the insolation layer in each of second trenches; and forming a second semiconductor layer on each of the second buffer layers. | 03-03-2016 |
20160062231 | PHOTOLITHOGRAPHIC MASK AND FABRICATION METHOD THEREOF - A method is provided for fabricating a photolithographic mask. The method includes providing a transparent substrate; and forming an opaque layer on the transparent substrate. The method also includes writing layout patterns with at least one sub-resolution assistant feature with non-uniform size along a longitudinal direction to increase an adhesion force between the sub-resolution assistant feature with non-uniform size along the longitudinal direction and the transparent substrate in the opaque layer. Further, the method include cleaning residual matters generated by writing the layout patterns in the opaque layer. Further, the method also includes spin-drying the transparent substrate with the layout patterns and the sub-resolution assistant feature with non-uniform size along the longitudinal direction. | 03-03-2016 |
20160060097 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for forming a semiconductor structure is provided. The method includes providing a substrate having a device region; and forming a sacrificial layer on a surface of the substrate in the device region. The method also includes forming a device layer having a plurality of openings exposing a portion of the surface of the sacrificial layer on the sacrificial layer; and removing the sacrificial layer to expose the surface of the substrate in the device region. Further, the method includes forming a cavity in the substrate in the device region by simultaneously etching the surface of the substrate in the device region exposed by the removed sacrificial layer and the plurality of openings using an anisotropic etching process. | 03-03-2016 |
20160035816 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure. | 02-04-2016 |
20160035439 | MEMORY ARRAY, MEMORY DEVICE, AND METHODS FOR READING AND OPERATING THE SAME - The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row. | 02-04-2016 |
20160035434 | MEMORY ARRAY, MEMORY DEVICE, AND METHODS FOR READING AND OPERATING THE SAME - The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of column. A memory cell is connected to at least one redundant memory cell in a same row for storing same data as the memory cell; and a column of memory cells correspond to one redundant column of redundant memory cells wherein each redundant memory cell in the redundant column stores same data as the memory cell in a same row. | 02-04-2016 |
20160028376 | INTEGRATED CIRCUIT DEVICE AND REPAIR METHOD THEREOF - The present disclosure provides integrated circuit (IC) devices and repair methods of the IC devices. An IC device includes a PMOS transistor including a substrate, a gate dielectric layer on the substrate, and a gate on the gate dielectric layer. The IC device also includes a repair circuit configured to apply a negative bias voltage to the substrate of the PMOS transistor, when the PMOS transistor is in an OFF state, to cause injections of electrons in the substrate into the gate dielectric layer to neutralize holes caused by negative bias temperature instability (NBTI) effect. The repair circuit is further configured to stop applying the negative bias voltage to the substrate of the PMOS transistor when the PMOS transistor is in an ON state. As such, the disclosed IC device repairs defect caused by NBTI effect in the PMOS transistor and prolongs the lifespan of the PMOS transistor. | 01-28-2016 |
20160027670 | HEAT RESERVOIR CHAMBER, AND METHOD FOR THERMAL TREATMENT - The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder. | 01-28-2016 |
20150380519 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes providing a substrate; and forming at least one dummy gate structure on the substrate. The method also includes forming doping regions in the substrate at both sides of the dummy gate structure; forming an interlayer dielectric layer on the d the dummy gate structure; performing a first step thermal annealing process to increase a density of the interlayer dielectric layer; and activating doping ions for a first time without an excess diffusion of the doping ions in the doping region; and removing the dummy gate structure to expose the surface of the substrate to form a trench in the annealed interlayer dielectric layer. Further, the method also includes forming a gate dielectric layer on the surface of the substrate on bottom of the trench; and performing a second step thermal annealing process to activate the doping ions for a second time. | 12-31-2015 |
20150380327 | WAFER BONDING STRUCTURES AND WAFER PROCESSING METHODS - A wafer processing method is provided. The method includes providing a to-be-processed wafer having a first surface with a plurality of the device regions and dicing groove regions between adjacent device regions and a second surface; and providing a capping wafer having a first surface and a second surface. The method also includes bonding the first surface of the capping wafer with the first surface of the to-be-processed wafer. Further, the method includes performing an edge trimming process onto the to-be-processed wafer to cause a radius of the to-be-processed wafer to be smaller than a radius of the capping wafer; and grinding the second surface of the capping wafer. Further, the method also includes cleaning the second surface of the capping wafer; and etching a portion of the grinded and cleaned capping wafer to expose the dicing groove regions on the first surface of the to-be-processed wafer. | 12-31-2015 |
20150380241 | FIN FIELD-EFFCT TRANSISTOR AND FABRICATION METHOD THEREOF - A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins. | 12-31-2015 |
20150364598 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a first conductivity type; forming a first shallow trench isolation (STI) structure in the semiconductor substrate; and applying a first ion implantation to form a drift region of a second conductivity type into the semiconductor substrate with the drift region surrounding the first STI structure. The method also includes applying a counter-doping implantation to form a counter-doped region having the first conductivity in the drift region and forming a body region on one side of the drift region in the semiconductor substrate. The method further includes forming a gate structure on the semiconductor substrate, wherein one end of the gate structure extends to an area on the body region another end of the gate structure extends to an area on the first STI region. | 12-17-2015 |
20150364415 | METAL INTERCONNECT STRUCTURE AND FABRICATION METHOD THEREOF - A method is provided for fabricating a metal interconnect structure. The method includes forming a reticle having a metal line pattern region and at least a scattering bar by an optical proximity correction process; and providing a semiconductor substrate having a first dielectric layer and at least one conductive via. The method also includes aligning the reticle with the semiconductor substrate with the conductive via to align the scattering bar next to the conductive via; and forming metal line patterns on the first dielectric layer and a top surface of the conductive via to completely cover the conducive via. | 12-17-2015 |
20150349789 | OSCILLATOR CIRCUIT AND CONFIGURATION METHOD THEREOF - The present disclosure provides an oscillator circuit. The oscillator circuit includes a signal selecting unit, a control voltage generating unit, a reference voltage generating unit, an output adjusting unit, and a frequency-dividing unit. The signal selecting unit is configured to select a reference signal or a frequency-divided signal as an input signal. The control voltage generating unit is configured to generate a control voltage based on the input signal. The reference voltage generating unit is configured to generate a reference voltage. The output adjusting unit is configured to generate an output signal based on the control voltage and the reference voltage. The frequency-dividing unit is configured to divide the frequency of the output signal and generate the frequency-divided signal. | 12-03-2015 |
20150348966 | FIN FIELD-EFFCT TRANSISTORS AND FABRICATION METHOD THEREOF - A method for fabricating fin field-effect transistors includes providing a semiconductor substrate; and forming a plurality of fins on a surface of the semiconductor substrate. The method also includes forming dummy gates formed over side and top surfaces of the fins; forming a precursor material layer with a surface higher than top surfaces of the fins to cover the dummy gates and the semiconductor substrate; performing a thermal annealing process to convert the precursor material layer into a dielectric layer having a plurality of voids; and planarizing the dielectric layer to expose the top surfaces of the dummy gates. Further, the method also includes performing a post-treatment process using oxygen-contained de-ionized water on the planarized dielectric layer to eliminate the plurality of voids formed in the dielectric layer; removing the dummy gates to form trenches; and forming a high-K metal gate structure in each of the trenches. | 12-03-2015 |
20150348911 | INTERCONNECT STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnect structure. The method includes providing a substrate; and forming a first conductive layer; and forming a sacrificial layer on the substrate and the first conductive layer. The method also includes forming an opening exposing a surface of the first conductive layer in the sacrificial layer; and forming a catalyst layer on the exposed portion of the surface of the first conductive layer and a top surface of the sacrificial layer. Further, the method includes forming carbon nanotube bundles perpendicular to the surface of the substrate on the catalyst layer; and removing the sacrificial layer and the carbon bundles on the sacrificial layer. Further, the method also includes forming a first dielectric material layer covering top surfaces of the carbon nanotube bundles and a portion the surface of the substrate without carbon nanotubes to seal the carbon nanotube bundles in a space. | 12-03-2015 |
20150348835 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for forming an interconnect device is provided by the present disclosure. The method includes providing a dielectric layer on a substrate, forming openings in the dielectric layer to expose a portion of a surface of the substrate at a bottom of each opening and forming a metal layer to fill up the openings. The method also includes forming a semiconductor cover layer on the metal layer and on the dielectric layer, and performing a thermal annealing reaction to convert portions of the semiconductor cover layer that are on the metal layer into a metal capping layer. The method further includes performing a nitridation process on the metal capping layer and a remaining semiconductor cover layer to convert the metal capping layer into a metal nitride capping layer and the remaining semiconductor cover layer into a semiconductor nitride layer. | 12-03-2015 |
20150348788 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region; and forming a first dummy gate on the semiconductor substrate in the first region and a device layer on the semiconductor substrate in the second region. The method also includes forming a dielectric layer on of the first dummy gate and the device layer; and removing the first dummy gate to form a first trench. Further, the method includes forming a first metal layer on the first trench and the surfaces of the dielectric layer and the device layer; and performing a first planarization process onto the first metal layer using a polishing slurry having a first protective agent to form a first gate electrode in the first trench and form a protective layer on the device layer preventing the device layer being damaged during the first planarization process. | 12-03-2015 |
20150348777 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate and forming a dielectric layer on the substrate by a deposition process using reactant gases. The reactant gases include a silicon-source gas and an oxygen-source gas under a radio-frequency (RF) power. The deposition process performed for a total deposition time to form the dielectric layer is divided into a first time length, a second time length and a third time length. The RF power of the deposition process in the first time length is a first power, the first power gradually increases from the first power to a second power in the second time length, the RF power in the third time length is the second power, and the first power is less than the second power. | 12-03-2015 |
20150333063 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region; and forming at least one first dummy gate in the first region and at least one second dummy gate in the second region. Further, the method includes forming a dielectric layer with a top surface leveling with a surface of the first dummy gate on the semiconductor substrate; oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region; removing the first dummy gate to form a first gate trench; forming a first metal layer to fill the first gate trench and cover the protective layer and the dielectric layer; and removing a portion of the first metal layer higher than the dielectric layer to form a first metal gate in the first gate trench. | 11-19-2015 |
20150325544 | CHIP PACKAGING STRUCTURES AND TREATMENT METHODS THEREOF - A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer. | 11-12-2015 |
20150318364 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - According to a semiconductor structure fabrication method, a semiconductor substrate having gate structures is provided. Sidewalls of the gate structures may be covered by a spacer layer. An epitaxy process is performed to form a semiconductor epitaxial material layer covering the gate structures, the spacer layer, and the semiconductor substrate. Then, an etching process is performed to form a first semiconductor epitaxial layer on the semiconductor substrate at the two sides of the gate structures. Further, a selective epitaxy process is performed by using a deposition gas and an etching gas, forming a second semiconductor epitaxial layer. The formed second semiconductor epitaxial layer may repair or compensate the first semiconductor epitaxial layer along the horizontal direction. The epitaxy process, the etching process, and the selective epitaxy process are repeated successively to form elevated source/drain regions. The formed elevated source/drain regions may have a flat top surface without any angles. | 11-05-2015 |
20150318294 | FLASH MEMORY DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate; and forming a first polysilicon layer. The method also includes forming a hard mask layer; and forming a plurality of first openings exposing the first polysilicon layer in the hard mask layer and the first polysilicon layer. Further, the method includes forming a plurality of grooves by etching the semiconductor substrate along the first openings; and forming liner oxide layers by oxidizing the first polysilicon layer. Further, the method also includes forming shallow trench isolation structures by filling the first openings; and forming second openings by removing the hard mask layer and the non oxidized first polysilicon layer. Further, the method also includes forming a tunnel oxide layer on a bottom of the second opening; and forming a floating gate on each of the tunnel oxide layers. | 11-05-2015 |
20150318279 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. A semiconductor substrate is provided having dummy gate structures formed thereon. A stress layer is formed in the semiconductor substrate between adjacent dummy gate structures. A first dielectric layer is formed on the semiconductor substrate, the stress layers, and the sidewall spacers of the dummy gate structures, exposing dummy gate electrode layers. Gate structures are formed in the dielectric layer to replace the dummy gate structures. The gate structures include functional gate structures and at least one non-functional gate structure. The at least one non-functional gate structure is removed to form at least one second opening in the first dielectric layer. At least one third opening is formed in the semiconductor substrate at a bottom of the at least one second opening. A second dielectric layer is formed in the at least one second opening and the at least one third opening. | 11-05-2015 |
20150318050 | MEMORY ARRAY AND OPERATION METHOD FOR MEMORY DEVICE - A method for operating a memory is disclosed. The memory has an array of memory cells arranged in a plurality of rows and columns. Each row includes a label storage unit. The method includes receiving a first to-be-programmed data set to be stored into a target row and determining whether a condition is satisfied. When the condition is satisfied, performing a first operation on the first to-be-programmed data set to obtain a second to-be-programmed data set, programming the second to-be-programmed data set into the target row of memory cells, and setting the value of the label storage, unit to be a first labeling value. When the condition is not satisfied, performing a second operation on the first to-be-programmed data set to program the first to-be-programmed data set into the target row of memory cells, and setting the value of the label storage unit to be a second labeling value. | 11-05-2015 |
20150311311 | STATIC MEMORY CELL AND FORMATION METHOD THEREOF - The present disclosure provides a static memory cell and fabrication method. A first fin part is formed on a semiconductor substrate. An isolation layer is formed to cover a lower portion of sidewalls of the first fin part. A first dummy gate structure is formed across the first fin part. A dielectric layer is formed on the isolation layer. A mask layer is formed on the dielectric layer with a first opening to expose the top surface of the first dummy gate structure. The first dummy gate structure is removed through the first opening to form a first trench exposing the first fin part. A portion of the isolation layer is removed through the first opening to form a second trench exposing a portion of sidewalls of the first fin part below the top surface of the isolation layer. A first gate structure is formed by filling up the first and the second trenches. | 10-29-2015 |
20150311288 | MULTI-GATE VDMOS TRANSISTOR - Various embodiments provide multi-gate VDMOS transistors. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches. Each trench can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer to electrically connecting the plurality of doped regions, and a drain metal layer on the second surface of the substrate. | 10-29-2015 |
20150288173 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND CONFIGURATION METHOD - The present disclosure provides an electrostatic discharge (ESD) protection circuit and configuration method thereof. The ESD protection circuit includes first and second power supply terminals, first and second detection units, a control unit, a clamping unit, and a voltage-dividing output node defined between the first and second power supply terminals. The first detection unit detects an electrostatic signal, based on a signal between the first power supply terminal and the voltage-dividing output node, and outputs a first signal. Likewise, the second detection unit outputs a second signal. The control unit is configured to be driven by the first signal to convert into a first discharge control signal and by the second signal to convert into a second discharge control signal. The clamping unit is configured to receive the first and second discharge control signals to discharge an electrostatic current between the first and the second power supply terminals. | 10-08-2015 |
20150287621 | METHOD AND SYSTEM FOR AUTOMATICALLY COLLECTING SEMICONDUCTOR MANUFACTURING PARAMETERS - A method for automatically collecting semiconductor manufacturing parameters of a manufacturing equipment is provided. The method includes reporting semiconductor manufacturing parameters obtained by self-monitoring of the manufacturing equipment and obtaining storage locations in an electronic data capture corresponding to reported semiconductor manufacturing parameters and transporting the reported semiconductor manufacturing parameters and corresponding storage locations. The method further includes receiving the reported semiconductor manufacturing parameters and the corresponding storage location and storing each reported semiconductor manufacturing parameters automatically into the electronic data capture of a manufacturing execution system according to the corresponding storage location. | 10-08-2015 |
20150287611 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor device. The method includes providing a substrate having a device region and a peripheral region; and forming device structures on the substrate in the device region so as to form trenches between adjacent device structures. The method also includes forming a stop layer on the substrate and the device structures; and forming a first dielectric layer on the stop layer such that a portion of the densified first dielectric layer fills the trenches and a top surface of a portion of the first dielectric layer in the peripheral region is lower than a surface of the stop layer on the device structures by a densify high aspect ratio process. Further, the method includes forming a second dielectric layer on the densified first dielectric layer; and performing a plurality of polishing processes until the top surface of the device structures is exposed. | 10-08-2015 |
20150286131 | METHOD AND SYSTEM FOR OPTICAL PROXIMITY CORRECTION (OPC) - An Optical Proximity Correction (OPC) method is provided for compensating the Optical Proximity Effect (OPE) influence. The method include providing a substrate having at least one semiconductor structure and with a plurality of regions, providing a target pattern to be formed on the substrate, and respectively obtaining aerial image light intensity functions of the plurality of regions of the substrate. The method also includes establishing an OPC model based on the aerial image light intensity functions of the plurality of regions, and performing an OPC process to the target pattern by using the OPC model to adjust the target pattern factoring in optical effect of the plurality of regions. | 10-08-2015 |
20150279795 | METAL PILLAR BUMP PACKAGING STRCTURES AND FABRICATION METHODS THEREOF - A method for fabrication a metal pillar bump packaging structure is provided. The method includes providing a semiconductor substrate; and forming a metal interconnect structure and a dielectric layer exposing a portion of the metal interconnect structure on the semiconductor substrate. The method also includes forming a photoresist layer having an opening with an undercut with a bottom area greater than a top area at the bottom of the opening to expose the metal interconnect structure and a portion of the dielectric layer on the semiconductor substrate; and forming a metal pillar bump structure having a pillar body and an extension part with an enlarged bottom area in the opening and the undercut. Further, the method includes forming a soldering ball on the metal pillar bump structure. | 10-01-2015 |
20150279785 | ELECTRICAL INTERCONNECTION STRUCTURE AND FABRICATION METHOD THEREOF - An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench. | 10-01-2015 |
20150279662 | PHOTOLITHOGRAPHIC METHOD FOR FORMING A COATING LAYER - A method for forming a coating layer includes spraying coating material having a first flowability onto a substrate; performing a first spin coating process with a first spin speed to form an initial coating layer; and performing a first baking process to the initial coating layer to form a first material layer having a second flowability and a second material layer having a third flowability. The third flowability is less than the first flowability but larger than the second flowability, which is less than the first flowability. Further, the method includes performing a second spin coating process with a second spin speed to drive the coating material in the second material layer flowing on the surface of the first material layer to form a third material layer with a uniform thickness, and performing a second baking process to form a final coating layer on the substrate. | 10-01-2015 |
20150274512 | MEMS DEVICE AND FORMATION METHOD THEREOF - The present disclosure provides MEMS devices and their fabrication methods. A first dielectric layer is formed on a first substrate including integrated circuits therein. One or more first metal connections and second metal connections are formed in the first dielectric layer and are electrically connected to the integrated circuits. A second dielectric layer is formed on the first dielectric layer. An acceleration sensor is formed in the second dielectric layer to electrically connect to the one or more first metal connections. A second substrate is bonded to the second dielectric layer. One or more first metal vias are formed in the second substrate and in the second dielectric layer to electrically connect to the second metal connections. A pressure sensor is formed on the second substrate to electrically connect to the first metal vias. | 10-01-2015 |
20150255610 | SEMICONDUCTOR TRANSISTOR STRUCTURE AND FABRICATION METHOD THEREOF - FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions. | 09-10-2015 |
20150255473 | FLASH MEMORY AND FABRICATION METHOD THEREOF - A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance. | 09-10-2015 |
20150214112 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor devices and methods for forming the same. A substrate having a dielectric layer formed thereon is provided. The dielectric layer has six openings. A gate dielectric layer and a cap layer are sequentially formed in each opening of the six openings. A first work function layer is formed in a first opening and a second opening. A diffusion layer is formed in the first opening, a fifth opening, and a sixth opening. A material of the diffusion layer is diffused into the first work function layer and the cap layer, to form a doped work function layer in the first opening and a doped cap layer in the fifth opening and in the sixth opening. A second work function layer is formed in a fourth opening and the fifth opening. A third work function layer and a metal gate are formed in the each opening. | 07-30-2015 |
20150206949 | TRANSISTORS AND FABRICATION METHODS THEREOF - A method is provided for fabricating transistors. The method includes providing a substrate; and forming at least one dummy gate structure having a dummy gate dielectric layer and a dummy gate electrode layer on the substrate. The method also includes forming a dielectric film on the substrate and the dummy gate structure; and performing a thermal annealing process onto the dielectric film to increase the density of the interlayer dielectric film. Further, the method includes planarizing the dielectric film having the increased density until the top surface of the dummy gate structure is exposed; and forming a dense layer having an increased density on the dielectric film having the increased density. Further, the method also includes removing the dummy gate dielectric layer and the dummy gate electrode layer to form an opening; and forming a gate dielectric layer and a gate electrode layer sequentially in the opening. | 07-23-2015 |
20150206888 | STATIC RANDOM ACCESS MEMORY AND FABRICATION METHODS THEREOF - A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate. The method also includes forming a plurality of transistors on the semiconductor substrate. Further, the method includes forming a first metal layer having a word line electrically connecting with a partial number of the transistors. Further, the method also includes forming a second metal layer having a first bit line, a second bit line, a first power source line and second power source lines electrically connect with a partial number of the transistors. | 07-23-2015 |
20150205215 | EXPOSURE APPARATUS, PHOTOLITHOGRAPHICAL RETICLES AND EXPOSURE METHODS THEREOF - An exposure apparatus is provided for performing a column scan-exposure process. The exposure apparatus includes a base for supporting the exposure apparatus; and a reticle stage configured for holding a reticle having at two mask pattern regions and carrying the reticle to move reciprocally along a scanning direction. The exposure apparatus also includes a wafer stage configured for holding a wafer and carrying the wafer to move reciprocally along the scanning direction. Further, the exposure apparatus includes a control unit configured to control the reticle stage and the wafer stage to cooperatively move to cause the at least two mask pattern regions of the reticle on the reticle stage to be continuously and sequentially projected on at least two corresponding exposure shots of the wafer on the wafer stage along the scanning direction to perform a column scan-exposure process. | 07-23-2015 |
20150205209 | PATTERNING APPARATUS AND PATTERNING METHODS THEREOF - A patterning apparatus is provided. The patterning apparatus includes a plurality of liquid jet units arranged in one or more groups and configured to jet an anti-etching liquid onto a surface of a substrate. The patterning apparatus also includes a plurality of exposure units configured to expose light on the anti-etching liquid jetted on the surface of the substrate to heat and cure the jetted anti-etching liquid to form anti-etching patterns on the surface of the substrate. Further, the patterning apparatus includes a control unit configured to control motion status and jetting status of the plurality of liquid jet units and motion status and exposure status of the plurality of exposure units, so as to form the anti-etching patterns at a predetermined line width and thickness. | 07-23-2015 |
20150203351 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top surface coplanar with a top surface of the semiconductor substrate. A sacrificial layer is formed on the semiconductor substrate and the first electrode layer. A first mask layer made of a conductive material is formed on the sacrificial layer. The first mask layer and the sacrificial layer are etched until a surface of the first electrode layer is exposed to form openings through the first mask layer and the sacrificial layer. A cleaning process is performed to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls and bottom surfaces of the openings. Conductive plugs are formed in the openings after the cleaning process. | 07-23-2015 |
20150188038 | PHASE CHANGE MEMORIES - A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode. | 07-02-2015 |
20150187781 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells formed thereon. Each memory cell includes a gate structure, a control gate layer, and a first mask layer. A portion of the control gate layer is removed, to reduce a size of an exposed portion of the control gate layer in a direction parallel to a surface of the substrate. An electrical contact layer is formed on an exposed sidewall of the control gate layer and an exposed surface of the substrate. A barrier layer is formed on a sidewall of the memory cell. A conductive structure is formed on the substrate. The conductive structure has a significantly larger distance from control gate layer than from the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer. | 07-02-2015 |
20150187780 | MEMORY DEVICE AND METHOD FOR FORMING THE SAME - Various embodiments provide memory devices and methods for forming the same. In an exemplary method, a provided substrate has one or more memory cells, a memory cell of which includes a control gate layer. The control gate layer has a first portion and a second portion on the first portion. A silicide layer is formed in the control gate layer and covers at least a sidewall of the second portion. A portion of the silicide layer is removed to reduce a size of the silicide layer in a direction parallel to the substrate. A fourth dielectric layer is formed on the substrate and on the memory cell, and has a top surface higher than a top surface of the memory cell. An opening is formed in the fourth dielectric layer and exposes a portion of the substrate between adjacent memory cells. A conductive structure is formed in the opening. | 07-02-2015 |
20150187749 | SILICON-CONTROLLED RECTIFIER ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD FOR FORMING THE SAME - Various embodiments provide SCR ESD protection devices and methods for forming the same. An exemplary device includes a semiconductor substrate having a P-type well region, an N-type well region adjacent to the P-type well region, a first P-type doped region and a first N-type doped region in the P-type well region, and a second N-type doped region and a second P-type doped region in the N-type well region. A first center-doped region and a second center-doped region doped with impurity ions of a same type are located between the first N-type doped region and the second P-type doped region and extend across the P-type well region and the N-type well region. The first center-doped region is located within the second center-doped region, has a doping concentration higher than a doping concentration in the second center-doped region, and has a depth smaller than a depth of the second center-doped region. | 07-02-2015 |
20150187601 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor devices and methods for forming the same. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via. | 07-02-2015 |
20150185828 | WEARABLE INTELLIGENT SYSTEMS AND INTERACTION METHODS THEREOF - A wearable intelligent system is provided. The system includes a frame; and a micro projector disposed on the frame configured to project an image interface onto a beam splitter. The system also includes the beam splitter disposed on the frame configured to receive the image interface and form a virtual image in a user's eye; and a position sensor disposed on the front of the frame configured to sense a position of at least a body part and a change mode of the position with time and convert the change mode of the position into operation commands and the position into a position data. Further, the system includes a central data hub disposed on the frame configured to at least receive the position data and the operation commands and adjust the image interface to match the part of the user's body and perform corresponding operations according to the position data. | 07-02-2015 |
20150183081 | CHEMICAL MECHANICAL PLANARIZATION APPARATUS AND METHODS - A chemical mechanical planarization (CMP) apparatus is provided. The CMP apparatus includes at least one platen; and a polishing pad disposed on the platen. The CMP apparatus also includes a polishing head disposed above the platen and configured to clamp a to-be-polished wafer; and a basic solution supply port disposed above the platen and configured to supply a basic solution onto a surface of the polishing pad. Further, the CMP apparatus includes a slurry arm disposed above the platen and configured to supply a polish slurry on the surface of the polishing pad; and a deionized water supply port configured to supply deionized water onto the surface of the polishing pad. Further, the CMP apparatus also includes a negative power source configured to apply a negative voltage onto the surface of the polishing pad. | 07-02-2015 |
20150179647 | CMOS INVERTERS AND FABRICATION METHODS THEREOF - A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure. | 06-25-2015 |
20150179571 | METAL INTERCONNECT STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a metal interconnection structure. The method includes providing a semiconductor substrate having an active region and an isolation structure surrounding the active region; and forming a metal layer on a surface of the semiconductor substrate. The method also includes forming a metal silicide layer on the active region by a reaction of the metal layer and material of the active regions; and forming an inter metal connection layer electrically connecting with the active regions on the isolation structure. Further, the method includes forming a dielectric layer covering the metal silicide layer, the isolation structure and the inter metal connection layer on the semiconductor substrate; and forming a metal contact via electrically connecting with the active region through the inter metal connection layer in the dielectric layer. | 06-25-2015 |
20150179528 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device may include forming a gate structure that includes a dummy gate member on a substrate. The method may further include forming two first-type spacers such that the dummy gate member is positioned between the first-type spacers. The method may further include forming two second-type spacers such that the first-type spacers are positioned between the second-type spacers. The method may further include forming two third-type spacers such that the second-type spacers are positioned between the third-type spacers. The method may further include performing etch to remove the third-type spacers and to at least partially remove the second-type spacers. The method may further include removing at least a portion of the dummy gate member to form a space between remaining portions of the first-type spacers. The method may further include providing a metal material in the space for forming a metal gate member. | 06-25-2015 |
20150162444 | TRANSISTOR DEVICE AND FABRICATION METHOD - A transistor and a fabrication method are provided. In an exemplary transistor, a gate structure is formed on a surface of the substrate. A first doped region is formed in the substrate on both sides of the gate structure. An opening is formed in the first doped region. A stress layer is formed in the opening of the first doped region on the both sides of the gate structure. The stress layer has a thickness in the substrate less than a depth of the first doped region. The first doped region has a bottom in the substrate surrounding a bottom of the stress layer. The stress layer further contains a second doped region. The second doped region and the first doped region form a source region or a drain region. | 06-11-2015 |
20150162285 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer. | 06-11-2015 |
20150155381 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers. | 06-04-2015 |
20150145054 | TRANSISTOR AND METHOD FOR FORMING THE SAME - Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening. | 05-28-2015 |
20150145017 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a substrate can be provided. The substrate can have a plurality of isolation structures. A top surface of the plurality of isolation structures can be higher than a surface of the substrate. A device layer can be formed on the substrate and on the plurality of isolation structures. The device layer can be polished using a polishing process, such that the top surface of the plurality of isolation structures are exposed, with residue remaining on the device layer and on the plurality of isolation structures. The residue can be removed from the device layer and from the plurality of isolation structures using a non-polishing-removal process, such that the top surface of the plurality of isolation structures and a top surface of the device layer are substantially leveled and smooth. | 05-28-2015 |
20150137881 | High-Voltage-Tolerant Pull-Up Resistor Circuit - A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage. | 05-21-2015 |
20150132954 | METHOD FOR PROCESSING STRUCTURE IN MANUFACTURING SEMICONDUCTOR DEVICE - A method used for processing a structure in manufacturing of a semiconductor device may include polishing the structure to form a polished structure. The polished structure may include a metal member, a dielectric layer that contacts the metal member, and a particle that contacts at least one of the metal member and the dielectric layer. The method may further include applying an organic acid to the polished structure to remove at least a portion of the particle. The particle may be substantially removed, such that satisfactory quality of the semiconductor may be provided. | 05-14-2015 |
20150129926 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A field effect transistor is provided. The field effect transistor includes a semiconductor region formed on a substrate, wherein the semiconductor region comprises an undoped channel region, a source region including a first dopant type, and a drain region including a second dopant type, and wherein the channel region is formed of a group III-V compound semiconductor material. The field effect transistor further includes a high-K gate formed on the channel region, wherein the high-K gate is configured to generate electron tunneling between the source region and the drain region when a gate voltage is applied, and wherein a first contact surface between the source region and the channel region and a second contact surface between the drain region and the channel region are inclined. | 05-14-2015 |
20150123147 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches. | 05-07-2015 |
20150116017 | SELF-BIASED PHASE LOCK LOOP - A self-biased Phase Locked Loop (PLL) is provided. The self-biased PLL includes a bias current generator configured to generate a bias current Ib, wherein the bias current Ib includes one or more adjustable parameters for adjusting a loop bandwidth wn of the self-biased PLL. The one or more adjustable parameters in the bias current Ib includes at least one of a reference voltage Vref and a reference frequency Fref. | 04-30-2015 |
20150113486 | ENHANCED OPTICAL PROXIMITY CORRECTION (OPC) METHOD AND SYSTEM - An enhanced optical proximity correction method is provided. The method includes providing a mask substrate and a substrate and obtaining a customer target pattern. The method also includes obtaining a production layout by performing an optical proximity correction process onto the customer target pattern using the pattern and a pattern formed on the substrate. Further, the method includes obtaining the light intensity information instead of dimension of the production layout. Further, the method includes storing the light intensity information of the production layout, the production layout and surrounding coherence radius in an optical proximity correction model database if the light intensity information of the production layout does not coincide with light intensity information of original modeling patterns already stored in the optical proximity correction model database. Further, the method also includes generating actual patterns using the stored optical proximity correction model corresponding to the stored light intensity information. | 04-23-2015 |
20150102455 | METHOD OF FABRICATING DUAL TRENCH ISOLATED SELECTIVE EPITAXIAL DIODE ARRAY - Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process. The method also includes forming a semiconductor epitaxial layer on the N+ buried layer, forming deep trench isolations through the epitaxial layer and the N+ buried layer into a portion of the substrate in the first direction, and forming shallow trench isolations in the diode array region and in the peripheral region in the second direction. The shallow trench isolation has a depth equal to or greater than a thickness of the epitaxial layer. | 04-16-2015 |
20150102451 | NANOSCALE SILICON SCHOTTKY DIODE ARRAY FOR LOW POWER PHASE CHANGE MEMORY APPLICATION - Methods and devices associated with a phase change memory include Schottky diodes operating as selectors having a low turn-on voltage, low sneak current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate having a diode array region and a peripheral device region, forming an N+ buried layer in the diode array region, forming a semiconductor epitaxial layer on the N+ buried layer, and forming deep trench isolations through the epitaxial layer and the N+ buried layer along a first direction. The method also includes forming shallow trench isolations in the diode array region and in the peripheral region along a second line direction. The method also includes forming an N− doped region between the deep and shallow trench isolations and forming a metal silicide on a surface of the N− doped region. | 04-16-2015 |
20150102423 | METHOD FOR FINFET SRAM RATIO TUNING - A semiconductor device and method of forming the same include a substrate having a plurality of memory cells formed thereon. A memory cell includes pass-gate transistors, pull-up transistors, and pull-down transistors. The pass-gate transistors and a portion of the pull-down transistors have different doping concentrations. | 04-16-2015 |
20150093871 | ENHANCED STRESS MEMORIZATION TECHNIQUE FOR METAL GATE TRANSISTORS - A method of manufacturing a semiconductor device includes forming a dummy gate structure on a semiconductor substrate, forming sidewall spacers, and forming heavily doped source/drain regions. After removing the spacers, a stress material layer is formed over the dummy gate structure. An annealing process is performed to transfer the stress to the device channel region. After the annealing process, the stress material layer is removed. The dummy gate structure is replaced by a high-k dielectric layer and a metal gate structure. Subsequently, contact holes are formed to expose at least part of the heavily doped source/drain regions, and self-aligned silicide is formed over exposed portions of the heavily doped source/drain regions. | 04-02-2015 |
20150091091 | JUNCTION-LESS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a junction-less transistor. The method includes providing a semiconductor substrate having a dielectric layer; and forming a semiconductor layer including a first heavily doped layer formed on the dielectric layer, a lightly doped layer formed on the first heavily doped layer and a second heavily doped layer formed on the lightly doped layer. The method also includes etching the semiconductor layer and the dielectric layer to form trenches to expose side surfaces of a portion of the semiconductor layer and a portion of the dielectric layer; and removing the portion of the dielectric layer between the adjacent trenches to form a chamber. Further, the method includes forming a gate structure around the portion of the semiconductor layer between the adjacent trenches; and forming a source region and a drain region in the semiconductor layer at both sides of the gate structure. | 04-02-2015 |
20150091065 | PIXEL STRUCTURES OF CMOS IMAGING SENSORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a pixel structure of a CMOS transistor. The method includes providing a semiconductor substrate doped with first type doping ions; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The method also includes forming isolation layers on side surfaces of the trench to prevent dark current from laterally transferring; and forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping ions in the trench. Further, the method includes forming a pinning layer on a top surface of the epitaxial layer; and forming a gate structure on a surface of the semiconductor substrate at one side of the epitaxial layer. Further, the method also includes forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial layer. | 04-02-2015 |
20150090952 | RESISTOR MEMORY BIT-CELL AND CIRCUITRY AND METHOD OF MAKING THE SAME - A resistive memory cell control unit, integrated circuit, and method are described herein. The resistive memory cell control unit includes a switching transistor and a resistive memory cell. The switching transistor includes a gate disposed on a first surface of a semiconductor substrate, a source, and a drain each disposed in the semiconductor substrate, a gate terminal disposed on the first surface and connected to the gate, a source terminal disposed on the first surface and connected to the source, and a drain terminal connected to the drain and disposed on a second surface opposite the first surface. The resistive memory cell is disposed on the second surface and has a first end connected to the drain terminal. The structure provides a small area and simple manufacturing process for a resistive memory cell integrated circuit. | 04-02-2015 |
20150078067 | METHOD OF MEASURING THRESHOLD VOLTAGE OF MOS TRANSISTOR IN SRAM ARRAY - Methods of measuring threshold voltages of MOS transistors in a SRAM array are provided. The SRAM array includes array-arranged cells having a first pass NMOS transistor, a second pass NMOS transistor, a first pull-down NMOS transistor, a second pull-down NMOS transistor, a first pull-up PMOS transistor, and a second pull-up transistor. A cell is selected from the SRAM array by a row decoding and a column decoding. A voltage is applied to a word line, a first bit line, a second bit line, a first power line, a second power line, a first substrate terminal, and/or a second substrate terminal, that are connected to the selected cell. A bit line current of the selected cell is measured to obtain a threshold voltage of a MOS transistor in the selected cell. Threshold voltages of a large number of MOS transistors in a SRAM array can be measured. | 03-19-2015 |
20150076555 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; and a body region and a drift region formed in the semiconductor substrate. The semiconductor device also includes a bulk region and a source region formed in the body region. Further, the semiconductor device includes a drain region and a first shallow trench isolation structure having a ladder-like bottom formed in the drift region. Further, the semiconductor device also includes a gate structure spanning over an edge of the body region and an edge of the drift region formed on the semiconductor substrate and covering a portion of the first shallow trench isolation structure. | 03-19-2015 |
20150061087 | TRIPLE PATTERNING METHOD - A triple patterning method is provided. The method includes providing a substrate having a first region and a second region; and forming a first material layer. The method also includes forming a second material layer; and forming a plurality of core patterns on the second material layer in the first region. Further, the method includes forming sidewall spacers on side surfaces of the core patterns; and forming first patterns on the first material layer. Further, the method includes forming a third material layer on the first material layer and the first patterns; and forming second patterns on the third material layer in the first region and third patterns on the third material layer in the second region. Further, the method also includes forming fourth patterns; and forming triple patterns on the substrate in the first region and fifth patterns on the substrate in the second region. | 03-05-2015 |
20150061047 | CAPACITIVE PRESSURE SENSORS AND FABRICATION METHODS THEREOF - A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate. | 03-05-2015 |
20150060961 | FINFET DEVICE AND METHOD OF FORMING FIN IN THE SAME - A method for manufacturing a fin for a FinFET device includes providing a semiconductor substrate, forming a plurality of implanted regions in the semiconductor substrate, and epitaxially forming fins between two adjacent implanted regions. The method also includes forming an insulating structure between two adjacent fins. | 03-05-2015 |
20150058814 | METHOD AND SYSTEM FOR OBTAINING OPTICAL PROXIMITY CORRECTION MODEL CALIBRATION DATA - A method may be implemented for obtaining calibration data for use in calibrating an optical proximity correction model. The method may include capturing an image for each portion of a plurality of portions of a wafer to obtain captured images. The method may further include assembling at least portions of the captured images to form an assembled image. The method may further include mapping layout data of the wafer with the assembled image. The method may further include selecting portions of the assembled image based on the layout data of the wafer. The method may further include obtaining data associated with the portions of the assembled image as the calibration data. | 02-26-2015 |
20150054051 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region. A gate dielectric material layer is formed to cover the first region, and a control gate dielectric layer is formed over a surface portion of the second region. The control gate dielectric layer has a top surface higher than the gate dielectric layer. A gate material layer is conformally formed to cover an entire surface of the semiconductor substrate and has a top surface in the second region higher than a top surface in the first region. A first filling material layer is formed on the gate material layer. A first patterned mask layer is formed on the first filling material layer to form a gate on a gate dielectric layer in the first region. A control gate is formed on the control gate dielectric layer of the second region. | 02-26-2015 |
20150041948 | SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND METHOD FOR FORMING THE SAME - Semiconductor devices and fabrication methods are disclosed. A mask layer having an opening is formed on a semiconductor substrate. The semiconductor substrate is etched along the opening of the mask layer to form a trench therein. The mask layer is laterally etched from the opening of the mask layer along a top surface of the semiconductor substrate to expose a surface portion of the semiconductor substrate on each side of the opening. A liner oxide layer is formed by a thermal oxidation process on interior surface of the trench and on the exposed surface portion of the semiconductor substrate. The thermal oxidation process is controlled such that an upper corner between the top surface of the semiconductor substrate and the trench is rounded after the liner oxide layer is formed. An insulation layer is formed on the liner oxide layer and fills the trench. | 02-12-2015 |
20150041893 | LDMOS DEVICE AND FABRICATION METHOD - Various embodiments provide LDMOS devices and fabrication methods. An N-type buried isolation region is provided in a P-type substrate. A P-type epitaxial layer including a first region and a second region is formed over the P-type substrate. The first region is positioned above the N-type buried isolation region, and the second region surrounds the first region. An annular groove is formed in the second region to surround the first region and to expose a surface of the N-type buried isolation region. Isolation layers are formed on both sidewalls of the annular groove. An annular conductive plug is formed in the annular groove between the isolation layers. The annular conductive plug is in contact with the N-type buried isolation region at the bottom of the annular conductive plug. A gate structure of an LDMOS transistor is formed over the first region of the P-type epitaxial layer. | 02-12-2015 |
20150041867 | FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FORMING THE SAME - Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width is measured as a distance between adjacent first sidewall spacers, and a second width is measured as a distance between adjacent second sidewall spacers. When the first width is not equal to the second width, the first sidewall spacers or the second sidewall spacers are correspondingly etched such that the first width is equal to the second width. The semiconductor substrate is etched using the first sidewall spacers and the second sidewall spacers as an etch mask, to form fins, such that a top of each fin has a symmetrical morphology. | 02-12-2015 |
20150037714 | PHOTOLITHOGRAPHIC MASKS AND FABRICATION METHOD THEREOF - A photolithographic mask is provided. The photolithographic mask includes a substrate having a first surface configured as a light incidence plane of an exposure light and a second surface. The photolithographic mask also includes a plurality of scattering centers functioning as a refractive index disturbance inside the substrate. Further, the photolithographic mask includes a plurality of mask patterns on the second surface of the substrate. | 02-05-2015 |
20150035152 | Interconnection structures for semiconductor devices and fabrication methods of forming interconnection structures for semiconductor devices utilizing to-be-etched layer made of porous low-K dielectric material and a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) - A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a to-be-etched layer made of porous low dielectric constant material on one surface of the semiconductor substrate. The method also includes forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) on the to-be-etched layer; and etching the first hard mask layer to have patterns corresponding to positions of subsequently formed openings. Further, the method includes forming the plurality of openings without substantial undercut between the to-be-etched layer and the first hard mask layer in the to-be-etched layer using the first hard mask layer as an etching mask; and forming a conductive structure in each of the openings. | 02-05-2015 |
20150035084 | MOS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K gate dielectric layer, a high-K gate dielectric protection layer containing nitrogen and a poly silicon dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the poly silicon dummy gate structure. Further, the method includes removing the poly silicon dummy gate to form a trench exposing the high-K gate dielectric protection layer containing nitrogen and performing a nitrogen treatment process to repair defects in the high-K gate dielectric protection layer containing nitrogen caused by removing the poly silicon dummy gate. Further, the method also includes forming a metal gate structure in the trench. | 02-05-2015 |
20150035083 | MOS TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; forming a metal gate structure; and forming a source region and a drain region. The method also includes forming a contact-etch-stop layer; forming an interlayer dielectric layer on the contact-etch-stop layer and the metal gate structure; and forming a first opening in the interlayer dielectric layer with a portion of the sidewall spacer and the contact-etch-stop layer left on the bottom. Further, forming a first contact hole in the interlayer dielectric layer by removing the portion of the sidewall spacer and the contact-etch-stop layer. Further, the method also includes forming a first conductive via in the first contact hole. | 02-05-2015 |
20150035079 | METHOD FOR CORE AND IN/OUT-PUT DEVICE RELIABILITY IMPROVE AT HIGH-K LAST PROCESS - A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device, removing the dummy gates of the core and IO devices, removing the dummy gate interface layer of the core device, forming a gate interface layer in the original location of the removed dummy gate interface layer, forming a high-k dielectric layer each on the gate interface layer of the core and IO devices, and submitting the semiconductor substrate to a high-pressure fluorine annealing. The high-pressure fluorine annealing causes the gate interface layer and the high-k dielectric layer of the core and IO devices to be doped with fluoride ions. | 02-05-2015 |
20150035038 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a semiconductor substrate is provided. A first stop layer, a first sacrificial layer, a second stop layer, and a second sacrificial layer are formed sequentially on the semiconductor substrate. The second sacrificial layer, the second stop layer, the first sacrificial layer, the first stop layer, and the semiconductor substrate are etched to form a groove, the groove then being filled to form an isolation structure. The second sacrificial layer is removed to expose sidewalls and a top of an exposed portion of the isolation structure. The second stop layer is removed, and the exposed portion of the isolation structure is etched to reduce a width of the top of the exposed portion of the isolation structure. The first sacrificial layer is removed. A floating gate is formed on the first stop layer. | 02-05-2015 |
20150034906 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a fin-shaped buffer layer formed on the surface of the substrate. A QW material layer is formed on the surface of the fin-shaped buffer layer. A barrier material layer is formed on the QW material layer. The QW material layer is suitable for forming an electron gas therein. Thereby the short-channel effect is improved, while high mobility of the semiconductor device is guaranteed. In addition, according to the present disclosure, thermal dissipation of the semiconductor device may be improved, and thus performance and stability of the device may be improved. | 02-05-2015 |
20150034905 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device is provided. The method includes forming a substrate structure, wherein the substrate structure includes a substrate and a fin-shaped barrier layer formed on a surface of the substrate; forming a quantum well (QW) material layer on a surface of the fin-shaped barrier layer; and forming a barrier material layer on the QW material layer. | 02-05-2015 |
20150034845 | EUVL LIGHT SOURCE SYSTEM AND METHOD - EUVL light source systems and methods are provided. A laser or a high-voltage-discharge device is used to excite EUV light source material to generate EUV light along with droplets flying out of the EUV light source material. A collector is positioned to guide the EUV light into a desired direction. A cooling assembly is configured to wrap around the collector along the EUV light in the desired direction. At least a first portion of the plurality of molten droplets reaches and condenses on a surface of the cooling assembly. | 02-05-2015 |
20150034844 | SYSTEM AND METHOD FOR REDUCING CONTAMINATION IN EXTREME ULTRAVIOLET LITHOGRAPHY LIGHT SOURCE - Various embodiments provide systems and methods for extreme ultraviolet (EUV) lithography light source. An exemplary system can include a laser radiation apparatus configured to provide laser radiation. The system can further include an EUV light excitation source material configured to receive the laser radiation to generate an EUV light. The laser radiation can generate droplets from the EUV light excitation source material. The system can further include a collector configured to collect the EUV light. The collector can include a plurality of reflective mirrors surrounding the EUV light excitation source material. The plurality of reflective mirrors can be movable. The collector can further include a mirror control system synchronized with the laser radiation apparatus and configured to set the plurality of reflective mirrors to be in one of a reflective state for reflecting the EUV light and a non-reflective state for preventing contamination by the droplets. | 02-05-2015 |
20150028483 | NOVEL METHOD FOR ELECTROMIGRATION AND ADHESION USING TWO SELECTIVE DEPOSITION - A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination. | 01-29-2015 |
20150008543 | MEMS CAPACITIVE PRESSURE SENSORS AND FABRICATION METHOD THEREOF - A MEMS capacitive pressure sensor is provided. The MEMS capacitive pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The capacitive pressure sensor also includes a second dielectric layer having a step surface profile formed on the first dielectric layer, and a first electrode layer having a step surface profile formed on the second dielectric layer. Further, the MEMS capacitive pressure sensor includes an insulation layer formed on the first electrode layer, and a second electrode layer having a step surface profile with a portion formed on the insulation layer in the peripheral region and the rest suspended over the first electrode layer in the device region. Further, the MEMS capacitive pressure sensor also includes a chamber having a step surface profile formed between the first electrode layer and the second electrode layer. | 01-08-2015 |
20150008541 | MEMS PRESSURE SENSORS AND FABRICATION METHOD THEREOF - A MEMS capacitive pressure sensor is provided. The pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The pressure sensor also includes a first electrode layer formed on the first dielectric layer, and a second dielectric layer having first openings formed on the first electrode layer. Further, the pressure sensor includes conductive sidewalls connecting with the first electrode layer formed on sidewalls of the first openings, and a second electrode layer with a portion formed on the second dielectric layer in the second region and the rest suspended over the conductive sidewalls in the first region. Further, the pressure sensor also includes a chamber between the conductive sidewalls and the second electrode layer; and a third dielectric layer formed on the second electrode layer exposing a portion of the second electrode layer in the first region. | 01-08-2015 |
20140374916 | TSV INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for forming a through-substrate-via structure includes forming a via hole in a substrate, depositing a conductive material in the via hole, forming an annular groove in the substrate surrounding the conductive material, and depositing a dielectric material in the annular groove with overhang portions of the deposited dielectric material at a top surface of the groove forming an air gap in an interior portion of the groove. | 12-25-2014 |
20140374911 | DEVICE HAVING REDUCED PAD PEELING DURING TENSILE STRESS TESTING AND A METHOD OF FORMING THEREOF - The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer. | 12-25-2014 |
20140367777 | DOUBLE-SIDE PROCESS SILICON MOS AND PASSIVE DEVICES FOR RF FRONT-END MODULES - A method for forming integrated circuit includes providing a first semiconductor substrate having a front surface and a back surface that is opposite to the front surface. One or more first trenches are in the first semiconductor substrate from the front surface side, the first trenches being characterized by a first depth. One or more second trenches are formed in the first semiconductor substrate from the front surface side, the second trenches being characterized by a second depth which greater than the first depth. A horizontal isolation layer is formed parallel to the front surface and at a third depth from the front surface. The method also includes forming a first recessed region extending in the first semiconductor substrate from the back surface side to the horizontal isolation layer that results in a thinned semiconductor region having a thickness substantially equal to the third depth. The method further includes forming a bulk dielectric layer covering the back surface side of the first semiconductor substrate. | 12-18-2014 |
20140367753 | CMOS DEVICE WITH DOUBLE-SIDED TERMINALS AND METHOD OF MAKING THE SAME - A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the first surface and configured to form a channel region, and source and drain regions disposed on opposite sides of the channel region. The device also includes a source terminal and a drain terminal disposed on the second surface. The source and drain terminals are connected to the respective source and drain regions. The transistor device further include a body terminal disposed. on the second. surface and configured to connect the highest or lowest voltage supply to the semiconductor substrate. | 12-18-2014 |
20140365265 | SEMICONDUCTOR BULLET LOT DISPATCH SYSTEMS AND METHODS - A semiconductor bullet lot dispatch system is provided. The semiconductor bullet lot dispatch system includes a plurality of lots having bullet lots and non-bullet lots, and a processing site having a plurality of load ports used to run the lots. The semiconductor bullet lot dispatch system also includes a bullet lot arriving time initial module configured to collect work flow information of the lots and calculate bullet lot arriving time intervals; and a port remaining time initial module configured to calculate port next available time intervals. Further, the semiconductor bullet lot dispatch system includes a future constraint check module configured to match the bullet lots with the load ports, and a bullet lot scenario engine module configured to calculate a total available lot count of each of available load ports and dispatch the bullet lots to the load ports. | 12-11-2014 |
20140363565 | PHOTORESIST COATING APPARATUS AND METHODS - A photoresist coating apparatus is provided. The photoresist coating apparatus includes a base; and a position platform moving back and forth along a scanning direction on the base. The photoresist coating apparatus also includes an imprinter having a trench configured to hold photoresist and fixed on the position platform; and a photoresist spray nozzle disposed above the imprinter and configured to spray the photoresist into the trench. Further, the photoresist coating apparatus includes a reticle frame configured to install a cylindrical reticle and enable the cylindrical reticle to rotate around a center axis and contact with the imprinter so as to coat the photoresist in the trench on a surface of the cylindrical reticle. | 12-11-2014 |
20140362363 | METHODS FOR MONITORING SOURCE SYMMETRY OF PHOTOLITHOGRAPHY SYSTEMS - A method for monitoring the source symmetry of a photolithography system is provided. The method includes providing a first reticle; and providing a second reticle. The method also includes forming first bottom overlay alignment marks on a first wafer using the first reticle; and forming first top overlay alignment marks on the first bottom overlay alignment marks using the second reticle. Further, the method includes forming second bottom overlay alignment marks on a second wafer using the first reticle; and forming second top overlay alignment marks on the second bottom overlay alignment marks using the second reticle. Further, the method also include measuring a first overlay shift; measuring a second overlay shift; and obtaining an overlay shift caused by the source asymmetry based on the first overlay shift and the second overlay shift. | 12-11-2014 |
20140361417 | GROUND SHIELD STRUCTURE AND SEMICONDUCTOR DEVICE - Various embodiments provide ground shield structures, semiconductor devices, and methods for forming the same. An exemplary structure can include a substrate and a dielectric layer disposed on the substrate. The structure can further include multiple conductive rings disposed in the substrate, in the dielectric layer, and/or on the dielectric layer. Each conductive ring of the multiple conductive rings can have openings of about three or more, and the openings of the each conductive ring can divide the multiple conductive rings into a plurality of sub-conductive rings arranged spaced apart. The structure can further a ground ring electrically connected to each of the plurality of sub-conductive rings. | 12-11-2014 |
20140361401 | PATTERNED GROUND SHIELD STRUCTURES AND SEMICONDUCTOR DEVICES - A patterned ground shield structure is provided. The patterned ground shield structure includes a substrate having a dielectric layer. The patterned ground shield structure also includes a plurality of conductive rings having a plurality of sub conductive rings in the dielectric layer. Further, the patterned ground shield structure includes an interconnection line connecting with all of the sub conductive rings in the dielectric layer. Further, the patterned ground shield structure also includes a ground ring connecting with the interconnection line. | 12-11-2014 |
20140361400 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide electrostatic discharge protection structures and methods for forming the same. An exemplary structure can include a semiconductor chip including a through hole. The structure can further include a through silicon via (TSV) structure disposed within the through hole and passing through the semiconductor chip. The TSV structure can have a first surface and a second surface. The structure can further include a tunneling dielectric layer disposed on the first surface of the TSV structure. The tunneling dielectric layer can have a surface area covering a top view surface area of the TSV structure and a surface portion of the semiconductor chip surrounding the TSV structure. Yet further, the structure can include a metal material discretely dispersed in the tunneling dielectric layer, a first electrode disposed on the tunneling dielectric layer, and a second electrode disposed on the second surface of the TSV structure. | 12-11-2014 |
20140361384 | METAL GATE TRANSISTOR AND METHOD FOR FORMING THE SAME - Various embodiments provide metal gate transistors and methods for forming the same. In an exemplary method, a substrate having a top surface and a back surface can be provided. A dummy gate can be formed on the top surface. A first interlayer dielectric layer can be formed on the top surface and planarized to expose the dummy gate. The dummy gate can be removed to form a trench. A metal gate stack can be formed to cover the first interlayer dielectric layer and to fill the trench. The metal gate stack can be planarized to remove a portion of the metal gate stack from the first interlayer dielectric layer to form a metal gate electrode in the trench. A remaining edge portion of the metal gate stack can exist over an annular region of the substrate and can be removed from the annular region by an edge cleaning process. | 12-11-2014 |
20140361366 | LATERAL DOUBLE DIFFUSION METAL-OXIDE-SEMICONDUCTOR (LDMOS) TRANSISTORS AND FABRICATION METHOD THEREOF - A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well region and a drain region in the well region. The LDMOS transistor also includes at least one drifting region in the well region and an annular source region in the drifting region surrounding the drain region. Further, the LDMOS transistor includes at least one annular isolation structure surrounding the drain region in the drifting region. Further, the LDMOS transistor also includes an annular gate dielectric layer on the well region and an annular gate on the annular gate dielectric layer. | 12-11-2014 |
20140361339 | PMOS TRANSISTORS AND FABRICATION METHODS THEREOF - A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate; and forming gate structures on a surface of the semiconductor substrate. The method also includes forming sidewall spacers around the gate structures; and forming a protection layer on the sidewall spacers. Further, the method includes forming sigma shape trenches in the semiconductor substrate at sides of the gate structures; and forming SiGe structures with a surface protruding from the surface of the semiconductor substrate in the sigma shape trenches. Further, the method also includes removing the sidewall spacers and a portion of the protection layer; and forming lightly doped drain regions in the semiconductor substrate at both sides of the gate structures. | 12-11-2014 |
20140360539 | EDGE BEAD REMOVAL APPARATUS AND METHODS - An edge bead removal apparatus is provided. The edge bead removal apparatus includes a clamping unit configured to clamp a cylindrical reticle and cause the cylindrical reticle to incline with a pre-determined angle and to rotate around a central axis. The edge bead removal apparatus also includes an edge bead removal solvent nozzle configured to spray an edge bead removal solvent to remove edge beads on both edges of the cylindrical reticle. | 12-11-2014 |
20140353715 | FINFET DEVICE AND FABRICATION METHOD THEREOF - A transistor device may include a substrate that has a well portion. The transistor device may further include a source member and a drain member. The transistor device may further include a fin bar. The fin bar may be formed of a first semiconductor material, may be disposed between the source member and the drain member, and may overlap the well portion. The transistor device may further include a fin layer. The fin layer may be formed of a second semiconductor material, may be disposed between the source member and the drain member, and may contact the fin bar. | 12-04-2014 |
20140347917 | STATIC RANDOM ACCESS MEMORY STRUCTURES - A static random access memory structure is provided. The static random access memory structure includes a storage region having a first storage node and a second storage node which is complementary to the first storage node. The static random access memory structure also includes a reading region having a first reading transfer gate and a second reading transfer gate, and a reading word line electrically connecting with the gate of the first reading transfer gate and the gate of the second reading transfer gate. Further, the static random access memory structure includes a writing region independent of the reading region having a first writing transfer gate and a second writing transfer gate and a writing word line electrically connecting with the gate of the first writing transfer gate and the gate of the second transfer gate. | 11-27-2014 |
20140346565 | MOS TRANSISTORS AND FABRICATION METHODS THEREOF - A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second region; and forming first transistors on the semiconductor substrate. Wherein source/drain regions of the first transistors are configured as SiGe growth regions; and a first density of SiGe growth regions in the first region is smaller than a second density of SiGe growth regions in the second region. The method also includes forming dummy SiGe growth regions in the first region to increase the first density such that the total density of SiGe growth regions in the first region is in a range similar to the second density; and forming trenches in the first region and the second region and the dummy SiGe growth region. Further, the method includes forming embedded source/drain regions of the first transistors and dummy SiGe regions. | 11-27-2014 |
20140342559 | METHOD OF FORMING A SPACER PATTERNING MASK - The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask. | 11-20-2014 |
20140332932 | SHALLOW TRENCH AND FABRICATION METHOD - Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative. | 11-13-2014 |
20140332753 | NANO FIELD-EFFECT VACUUM TUBE AND FABRICATION METHOD THEREOF - A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer. | 11-13-2014 |
20140323018 | POLISHING DEVICE FOR REMOVING POLISHING BYPRODUCTS - A method for removing polishing byproducts and a polishing device are provided. The method includes mounting a positive electrode on the center of a polishing platen and a negative electrode on an edge of the polishing platen, applying a voltage between the positive electrode and the negative electrode after a polishing process for metal is finished, and rotating the polishing platen and rinsing a polishing pad with deionized water or a chemical cleaning solution to remove polishing byproducts that are formed in the polishing process. The combination of the centrifugal force and the electromotive force increases the removal rate of the polishing byproducts. | 10-30-2014 |
20140319625 | TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The methods also includes forming a threshold-adjusting layer doped with a certain type of threshold-adjusting ions to adjust the threshold voltage of the transistor on the semiconductor substrate in the trench; and forming a carrier drifting layer on the threshold-adjusting layer. Further the method includes forming a gate structure on the carrier drifting layer corresponding to the trench. | 10-30-2014 |
20140319543 | FIN FIELD-EFFECT TRANSISTORS - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins. | 10-30-2014 |
20140312471 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a SiGe layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent Fins are selectively thinned so as to prevent an undesired bridging of SiGe material between immediately adjacent ones of the Fins. A method of manufacturing the same comprises: providing a substrate having a plurality of tri-gate transistors, at least two fins of the tri-gate transistors being closely adjacent to each other, where respective top and sidewall surfaces of the fins are coated with a SiGe layer; performing a tilted ion implantation on the SiGe coated fins so as to partially convert the SiGe material into a predetermined etch resistant material (e.g., and oxide of the SiGe); and etching away the non-converted sidewall parts of the SiGe coating layers so as to provide greater spacing between the immediately adjacent sidewalls of the SiGe coated fins. | 10-23-2014 |
20140306352 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Various embodiments provide semiconductor devices and fabrication methods. In an exemplary method, a dielectric layer can be formed on a semiconductor substrate. A plurality of pillar structures having a matrix arrangement can be formed on the dielectric layer. A plurality of sidewall spacers can be formed on the dielectric layer. Each sidewall spacer can be formed on a sidewall surface of one of the plurality of pillar structures. A distance between adjacent pillar structures in a same row or in a same column can be less than or equal to a double of a thickness of the each sidewall spacer on the sidewall surface. The plurality of pillar structures can be removed. The dielectric layer can be etched using the plurality of sidewall spacers as an etch mask to form a plurality of trenches or through holes in the dielectric layer. | 10-16-2014 |
20140291856 | TSV LAYOUT STRUCTURE AND TSV INTERCONNECT STRUCTURE, AND FABRICATION METHODS THEREOF - TSV layout structure and TSV interconnect structure, and their fabrication methods are provided. An exemplary TSV interconnect structure includes a semiconductor substrate having a first region and a second region; and a plurality of through-holes disposed in the first region and the second region of the semiconductor substrate. An average through-hole density of the first region is greater than an average through-hole density of the entire semiconductor substrate. The average through-hole density of the entire semiconductor substrate is less than or equal to about 2%. A metal layer having a planarized surface is filled in the plurality of through-holes in the semiconductor substrate. | 10-02-2014 |
20140291817 | SEMICONDUCTOR DEVICE INCLUDING POROUS LOW-K DIELECTRIC LAYER AND FABRICATION METHOD - Semiconductor devices including porous low-k dielectric layers and fabrication methods are provided. A dielectric layer is formed on a substrate by introducing and polymerizing a main reaction gas on a surface of the substrate. The main reaction gas has a chemical structure including a ring-shaped group, silicon, carbon, and hydrogen, and the ring-shaped group includes at least carbon and hydrogen. A porous low-k dielectric layer is then formed from the dielectric layer by curing the dielectric layer with UV light. | 10-02-2014 |
20140291805 | SEMICONDUCTOR DEVICE CONTAINING MIM CAPACITOR AND FABRICATION METHOD - A semiconductor device containing an MIM capacitor and its fabrication method are provided. A metal-insulator-metal (MIM) capacitor is formed on a first interlayer dielectric layer covering a substrate. The MIM capacitor includes a bottom electrode layer and a top electrode layer that are isolated from and laterally staggered with one another. A second interlayer dielectric layer is formed to cover both the MIM capacitor and the first interlayer dielectric layer. A first conductive plug and a second conductive plug are formed each passing through the second interlayer dielectric layer. The first conductive plug contacts a sidewall and a surface portion of the top electrode layer of the MIM capacitor and the second conductive plug contacts a sidewall and a surface portion of the bottom electrode layer of the MIM capacitor. | 10-02-2014 |
20140291799 | SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND FABRICATION METHOD - Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching along the opening. A first dielectric layer is formed in the trench and has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate. An epitaxial layer is formed on the uncovered sidewall surface of the trench in the semiconductor substrate. The epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer. A second dielectric layer is formed on the exposed surface portion of the first dielectric layer to fill the spacing formed in the epitaxial layer. | 10-02-2014 |
20140291765 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference. | 10-02-2014 |
20140291764 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. Second doped base regions discretely located in a fourth region of a first P-type well region are P-type doped and connected to the external trigger-voltage adjustment circuit. A first N-region is located in the fourth region, surrounding the second doped base regions, and connected to the I/O interface terminal. A second N-region is located in the fourth region, surrounding the first N-region and the second doped base regions, and connected to the ground terminal. | 10-02-2014 |
20140291759 | MOS TRANSISTOR AND FABRICATION METHOD - MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure. | 10-02-2014 |
20140253897 | EXPOSURE APPARATUS AND EXPOSURE METHOD THEREOF - A wafer alignment system is provided for performing a unidirectional scan-exposure. The wafer alignment system includes a plurality of wafer stages successively moving from a first position to a second position of a base cyclically. The wafer alignment method also includes an encoder plate having a first opening and a second opening. Further, the wafer alignment system includes a plurality of encoder plate readers and a plurality of wafer stage fiducials on the wafer stages. Further, the wafer alignment system also includes an alignment detection unit above the first opening of the encoder plate. | 09-11-2014 |
20140253896 | EXPOSURE APPARATUS AND EXPOSURE METHOD THEREOF - An exposure apparatus is provided for performing an unidirectional scan-exposure. The exposure apparatus includes a base and a wafer stage group having a plurality of wafer stages on the base for holding wafers and successively moving from a first position to a second position of the base cyclically. The exposure apparatus also includes an alignment detection unit above the first position for detecting wafer stage fiducials at the first position and alignment marks on a wafer on the wafer stage to align the wafer. Further, the exposure apparatus includes a reticle stage on the second position for loading a cylindrical reticle and causing the cylindrical reticle to rotate around the center axis of the reticle stage and an optical projection unit between the reticle stage and the base for projecting light passing through the cylindrical reticle onto exposure regions on a wafer on the wafer stage. | 09-11-2014 |
20140253895 | CYLINDRICAL RETICLE SYSTEM, EXPOSURE APPARATUS AND EXPOSURE METHOD - A cylindrical reticle system is provided for performing a unidirectional scan-exposure. The cylindrical reticle system includes a base and a center shaft fixed a one side of the base. The cylindrical reticle system also includes a first bearing fixed at the end of the center shaft near to the base and a second bearing fixed at the other end of the center shaft far from the base. Further, the cylindrical reticle system includes a cylindrical reticle having an imaging region and two non-imaging regions at both end of the imaging region. | 09-11-2014 |
20140253893 | CYLINDRICAL RETICLE SYSTEM, EXPOSURE APPARATUS AND EXPOSURE METHOD - An exposure apparatus is provided for performing a unidirectional scan-exposure. The exposure apparatus includes a base and a plurality of wafer stages on the base for loading/unloading wafers and successively moving from a first position to a second position of the base cyclically. The exposure apparatus also includes alignment detection units above the first position of the base for detecting alignment marks on the wafer and aligning the wafers and a cylindrical reticle system above the second position of the base. Further, the exposure apparatus includes an optical projection unit between the cylindrical reticle system and the base for projecting light onto the wafers for an exposure. Further, the exposure apparatus also includes an illuminator box and a main control unit. | 09-11-2014 |
20140249656 | METHOD AND APPARATUS FOR ALARM MONITORING - A method for alarm monitoring abnormal conditions associated with a process operation includes collecting N sample data representing one or more parameters of a process, determining a distribution type of the sample data, obtaining an alarm monitoring strategy associated with the distribution type, and monitoring the process using the alarm monitoring strategy. The distribution type may be single-constant, multi-level discrete, normally distributed, continuous non-normally distributed, cyclical trend-up/down, and drifting away after a period maintenance. The alarm monitoring strategy includes a unilateral or bilateral control chart. The one-side control chart has either an upper control limit (UCL) of (100−p) or a lower control limit (LCL) of (p), and the two-sided control chart has a UCL of (100−p/2) and an LCL of (p/2), where p is a predetermined false alarm rate which determines the number N. The control limit may be a difference between two adjacent sample values of the sample data. | 09-04-2014 |
20140239361 | METHODS AND APPARATUS FOR SUPPRESSING CROSS TALK IN CMOS IMAGE SENSORS - A CMOS image sensor with reduced crosstalk includes a semiconductor substrate formed with a plurality of photodiodes formed therein, a dielectric layer formed on the semiconductor substrate, a reflective layer formed on the dielectric layer, and an insulating layer formed on the reflective layer. A plurality of grooves is formed in the dielectric layer, the reflective layer, and the insulating layer above a corresponding photodiode. Each groove is filled with a color filter material to form a color filter above the photodiode. The image sensor also includes a planarization layer formed on the insulating layer and color filter. A microlens is formed on the planarizing layer. The light reflecting layer prevents stray light diffraction line crosstalk into an adjacent photodiode. The color filter grooves confine the target image light only through the filters in the groove window to reach the photodiode. | 08-28-2014 |
20140213012 | METHOD AND SYSTEM FOR IMAGE SENSOR AND LENS ON A SILICON BACK PLANE WAFER - A method for forming image sensors includes providing a substrate and forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate. The method also includes forming an interlayer dielectric layer overlying the plurality of photo diode regions, forming a shielding layer formed overlying the interlayer dielectric layer, and applying a silicon dioxide bearing material overlying the shielding layer. The method further includes etching portions of the silicon dioxide bearing material to form a plurality of first lens structures, and continuing to form each of the plurality of first lens structures to provide a plurality of finished lens structures. | 07-31-2014 |
20140203243 | THREE-DIMENSIONAL QUANTUM WELL TRANSISTOR AND FABRICATION METHOD - Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part. The gate structure can be formed over the barrier layer and across the fin part. The QW layer and the barrier layer can form a hetero-junction of the transistor. A recess can be formed in the fin part on both sides of the gate structure to suspend a sidewall spacer. A source and a drain can be formed by growing an epitaxial material in the recess and the sidewall spacer formed on both sidewalls of the gate electrode can be positioned on surface of the source and the drain. | 07-24-2014 |
20140197492 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer. | 07-17-2014 |
20140197480 | SEMICONDUCTOR STRUCTURE HAVING COMMON GATE AND FABRICATION METHOD THEREOF - Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same. | 07-17-2014 |
20140193956 | TRANSISTOR AND FABRIATION METHOD - Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer. | 07-10-2014 |
20140191412 | INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad. | 07-10-2014 |
20140191411 | INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnection structure. The method includes providing a substrate having certain semiconductor devices, a metal layer electrically connecting with the semiconductor devices, and a barrier layer on the metal layer. The method also includes forming a dielectric layer on the substrate; and forming an antireflective coating on the dielectric layer. Further, the method includes forming a second mask having a first pattern corresponding to a through hole in the dielectric layer, wherein the antireflective coating significantly reduces lithographic light reflection to avoid photoresist residue in the first pattern; and forming a through hole by etching the dielectric layer and the antireflective coating covering the dielectric layer using the second mask as an etching mask. Further, the method also includes forming a via by filling the through hole with a conductive material. | 07-10-2014 |
20140191404 | LOCAL INTERCONNECT STRUCTURE AND FABRICATION METHOD - Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned surrounding the first film layer on an exposed surface portion of the dielectric layer. A second film layer can be formed on the exposed surface portion of the dielectric layer and can have a top surface substantially flushed with a top surface of the sidewall spacer. The patterned sidewall spacer can be removed to form a first opening. After forming the first opening, the dielectric layer can be etched to form a second opening through the dielectric layer. The second opening can be filled with a conductive material to form the local interconnect structure. | 07-10-2014 |
20140191314 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods are provided. A fin can be formed on a semiconductor substrate, a gate can be formed across the fin, and sidewall spacers can be formed across the fin on both sides of the gate. A dummy contact can be formed across the fin and on each of the both sides of the sidewall spacers. After forming an interlayer dielectric layer on the semiconductor substrate, the dummy contact can be removed to form a contact trench. The dummy contact is made of a material having an etch selectivity sufficiently higher than the fin such that the removing of the dummy contact generates substantially no damage to the fin. A conductive material can be filled in the contact trench to form a trench metal contact. | 07-10-2014 |
20140191301 | TRANSISTOR AND FABRICATION METHOD - Transistors and fabrication methods are provided. A first sidewall can be formed on each sidewall of a gate structure. A second sidewall can be formed on the first sidewall. The first sidewall can be made of a doped material. After forming a source and a drain, a metal silicide layer can be formed on the source and the drain. The second sidewall can be removed to expose a surface portion of the semiconductor substrate between the metal silicide layer and the first silicide layer. A stress layer can be formed on the exposed surface portion of the semiconductor substrate, on the metal silicide layer, on the first sidewall, and on the gate. | 07-10-2014 |
20140187006 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device comprises providing a substrate having a core oxide layer and an I/O oxide layer formed thereon. The I/O oxide layer has an I/O mask layer formed thereon. The method also includes forming an I/O dummy gate on the I/O mask layer and a core dummy gate on the core oxide layer, forming an etch barrier layer on the substrate covering the dummy gates, forming a dielectric layer on the etch barrier layer, and planarizing the etch barrier layer and the dielectric layer to expose the top surface of the dummy gates. The method further includes simultaneously removing the I/O and core dummy gates to form I/O and core gate grooves, removing the core oxide layer, removing the I/O mask layer, depositing a dielectric layer in the core gate groove, and forming a metal gate layer filling the I/O and core gate grooves. | 07-03-2014 |
20140176222 | SIGNAL RECEIVER AND SIGNAL TRANSMISSION APPARATUS - A signal receiver includes first and second bias circuits that receive an input signal and convert the input signal to respective first and second bias signals. The signal receiver also includes a first inverter comprising a PMOS device and an NMOS device, each device has a source, a drain, and a gate. When the voltage magnitude of the first bias signal is smaller than that of the input signal, the gate of the PMOS device is coupled to the first bias signal and the gate of the NMOS device is coupled to the input signal. When the voltage magnitude of the first bias signal is greater than that of the input signal, the gate of the NMOS device is coupled to the first bias signal and the gate of the PMOS device is coupled to the input signal. | 06-26-2014 |
20140175580 | MAGNETORESISTIVE MEMORY DEVICE AND FABRICTAION METHOD - A magnetoresistive memory device and a fabrication method are provided. A first dielectric layer disposed on a semiconductor substrate can include a groove formed therein. A cobalt metal layer can be formed over a bottom surface and a sidewall surface of the groove. A first metal layer can be formed over the cobalt metal layer. The first metal layer can fill the groove and be used as a first programming line of the magnetoresistive memory device. A second dielectric layer can be formed over the first dielectric layer and over the first metal layer. A magnetic tunnel junction can be formed over the second dielectric layer. The magnetic tunnel junction can be positioned corresponding to a position of the first metal layer. The magnetic tunnel junction can include an insulating layer sandwiched between a lower magnetic material layer and an upper magnetic material layer. | 06-26-2014 |
20140167285 | INTERCONNECT STRUCTURE AND FABRICATION METHOD - An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed in the substrate. At least two porous films can be formed over the substrate and can include a first porous film having a first pore size, and a second porous film having a second pore size formed on the first porous film. The first porous size and the second porous size are different. The interconnect can be formed through the plurality of porous films to provide electrical connection to the semiconductor device in the substrate. | 06-19-2014 |
20140167283 | INTERCONNECT STRUCTURE AND FABRICATION METHOD - A carbon-containing dielectric layer can be formed on a substrate. A protective layer can be formed on the carbon-containing dielectric layer to prevent carbon loss from the carbon-containing dielectric layer by performing a surface treatment to the carbon-containing dielectric layer using a gas at least containing silicon and hydrogen. A hard mask layer can be formed on the protective layer. A through hole can be formed in the carbon-containing dielectric layer using the hard mask layer as a mask to expose a surface of the substrate for forming a contact plug in the through hole. | 06-19-2014 |
20140167249 | INTERCONNECT STRUCTURE AND FABRICATION METHOD - An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate. | 06-19-2014 |
20140167166 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate. | 06-19-2014 |
20140167122 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure formed on a first portion of the active region, and at least one local interconnection layer formed on a portion of the substrate, wherein the at least one local interconnection layer is located on a side of the gate structure, and covers at least a second portion of the active region and a portion of the groove isolation region adjoining the active region. | 06-19-2014 |
20140151628 | PHASE CHANGE MEMORIES AND FABRICATION METHOD - A method is provided for fabricating a phase change memory. The method includes providing a semiconductor substrate having a bottom electrode connecting with one or more semiconductor devices, and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a loop-shape electrode in the first dielectric layer, and forming a second dielectric layer having a first opening exposing a portion of the first dielectric layer and a portion of the loop-shape electrode. Further, the method includes forming a phase change layer in the first opening of the second dielectric layer such that a contact area between the phase change layer and the loop-shape electrode may be controlled to achieve desired contact, and forming a top electrode. | 06-05-2014 |
20140145302 | MIM CAPACITOR AND FABRICATION METHOD - Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove. | 05-29-2014 |
20140145298 | ELECTRODE MANUFACTURING METHOD, FUSE DEVICE AND MANUFACTURING METHOD THEREFOR - The present disclosure relates to an electrode manufacturing method, and a fuse device and manufacturing method therefor. The fuse device includes a fuse element including a phase change material, and a first electrode formed in contact with the fuse element. The phase change material may include doped or undoped chalcogenide. The first electrode may have a sublithographic dimension at a portion where the first electrode contacts the fuse element. When the phase change material has a layer thickness less than or equal to about 30 nm, and a pulse current less than or equal to about 3 mA is applied to the fuse element via the first electrode, the fuse element may undergo a phase change, so as to convert the fuse device into a blow-out state. | 05-29-2014 |
20140131563 | METHOD FOR DETECTING ELECTRON BEAM OF SCANNING ELECTRON MICROSCOPE AND FOR DETECTING FINE PATTERNS - Methods for detecting an electron beam of a SEM and for detecting fine patterns are provided. Line patterns having a length in a first direction can be formed on a detection sample. A power spectral density (PSD) curve of a standardized model, formed under a same exposure process of the detection sample, can be obtained. An edge contour of each line pattern of the detection sample can be obtained by the SEM and can be sampled at a sampling frequency to obtain a variation range at a sampling point on the edge contour in a second direction that is perpendicular to the first direction. A PSD curve of the detection sample can be obtained according to the variation range and can be compared with the PSD curve of the standardized model to determine whether an electron beam of the SEM has a high quality in the second direction. | 05-15-2014 |
20140117496 | SEMICONDUCTOR DEVICE HAVING GROUND SHIELD STRUCTURE AND FABRICATION METHOD THEREOF - Semiconductor devices having a ground shield structure and methods for their formation are provided herein. An exemplary semiconductor device can include a substrate, a ground ring, a ground shield, an electronic device, and/or an insulation layer. The ground ring can be disposed over the substrate. The ground shield can be disposed over the substrate and surrounded by the ground ring. The ground shield can include a plurality of coaxial conductive wirings and a metal wire passing through the plurality of coaxial conductive wirings along a radial direction. The metal wire can be connected to the ground ring. The electronic device can be disposed over the ground shield. The insulation layer can be disposed between the ground shield and the electronic device. | 05-01-2014 |
20140117491 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - Various embodiments provide semiconductor structures and fabrication methods. In an exemplary method, a semiconductor substrate can contain a shallow trench isolation (STI) structure that includes a fuse region. A protective layer can be provided on the high-K dielectric layer, which is provided on the semiconductor substrate. A portion of each of the protective layer and the high-K dielectric layer can be removed from the fuse region to expose the STI structure. A fuse layer can be formed on the exposed surface of the STI structure. A portion of the fuse layer, the remaining portion of the protective layer, and a remaining portion of the high-K dielectric layer outside of the fuse region can be removed from the semiconductor substrate to form a fuse structure. | 05-01-2014 |
20140110769 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device fabrication method is provided in which recesses are formed at source/drain positions in the substrate, removable sidewalls are formed on side walls of the recess, and the recesses then are etched to form Sigma shaped recesses. Selective epitaxial growth of substantially un-doped SiGe in the Sigma shaped recesses is performed, and the Sigma shaped recesses close to the surface of the substrate can be protected from epitaxial growth by the removable sidewalls. Epitaxial growth of SiGe doped with a P-type impurity can be performed in the Sigma shaped recesses after removing the sidewalls. | 04-24-2014 |
20140110598 | ION SOURCE DEVICE AND METHOD FOR PROVIDING ION SOURCE - Various embodiments provide an ion source device and a method for providing the ion source. An exemplary ion source device can include an arc chamber, a filament, a reflector, a slit outlet, a source gas inlet, and/or a cleaning gas inlet. The filament can be configured to generate thermo-electrons in the arc chamber. The reflector can be configured to reflect the thermo-electrons back to the arc chamber. The slit outlet can be configured to exit a gaseous material out of the arc chamber. The source gas inlet and the cleaning gas inlet can be located on a same sidewall of the arc chamber configured to respectively introduce an ion source gas and an inert cleaning gas into the arc chamber. | 04-24-2014 |
20140077277 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate that has a surface. The semiconductor further includes a fin disposed on the surface and including a semiconductor member. The semiconductor further includes a spacer disposed on the surface, having a type of stress, and overlapping the semiconductor member in a direction parallel to the surface. A thickness of the spacer in a direction perpendicular to the surface is less than a height of the semiconductor member in the direction perpendicular to the surface. | 03-20-2014 |
20140048892 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers. | 02-20-2014 |
20130228847 | TFT Floating Gate Memory Cell Structures - A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 09-05-2013 |
20130207233 | METHOD AND DEVICE FOR A DRAM CAPACITOR HAVING LOW DEPLETION RATIO - A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided. | 08-15-2013 |
20130200384 | ATOMIC LAYER DEPOSITION EPITAXIAL SILICON GROWTH FOR TFT FLASH MEMORY CELL - A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH | 08-08-2013 |
20130193997 | SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER - System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit. | 08-01-2013 |
20130109173 | METHODS FOR REMOVING SILICON NITRIDE SPACER, FORMING TRANSISTOR AND FORMING SEMICONDUCTOR DEVICES | 05-02-2013 |
20130109145 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 05-02-2013 |
20130109142 | Strained-Induced Mobility Enhancement Nano-Device Structure and Integrated Process Architecture for CMOS Technologies | 05-02-2013 |
20130105919 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 05-02-2013 |
20130102116 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop. | 04-25-2013 |
20130029483 | METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION - A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material. | 01-31-2013 |
20120326328 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A method for manufacturing a semiconductor device includes providing a substrate having a first surface and a second surface, the second surface is on the opposite side of the substrate facing away from the first surface. The method further includes forming a first portion of an opening by etching a portion of the substrate from the first surface, forming a buffer layer on an inner surface of the first portion, etching a bottom of the buffer layer to expose an area of the underlying substrate, and etching the exposed area of the substrate to form a second portion of the opening. The method also includes performing an isotropic etching on the second portion of the opening to obtain a flask-shaped opening and filling the opening with a filling material. The method also includes partially removing a portion of the second surface and the filling material from the second portion of the opening. | 12-27-2012 |
20120309278 | METHOD FOR REMOVING POLISHING BYPRODUCTS AND POLISHING DEVICE - A method for removing polishing byproducts and a polishing device are provided. The method includes mounting a positive electrode on the center of a polishing platen and a negative electrode on an edge of the polishing platen, applying a voltage between the positive electrode and the negative electrode after a polishing process for metal is finished, and rotating the polishing platen and rinsing a polishing pad with deionized water or a chemical cleaning solution to remove polishing byproducts that are formed in the polishing process. The combination of the centrifugal force and the electromotive force increases the removal rate of the polishing byproducts. | 12-06-2012 |
20120302026 | METHOD FOR FORMING A TRANSISTOR - A method for forming a transistor includes providing a substrate, forming a well region in the substrate, and forming a gate structure on a surface of the well region. The gate structure includes a gate oxide layer on the surface of the well region and a gate on the gate oxide layer. The method further includes forming source/drain regions in the substrate at opposite sides of the gate structure and performing an ion doping to the substrate to adjust a threshold voltage. The ion doping is performed after the source/drain regions are formed to reduce the impact to the diffusion of the ions caused by heat treatments performed before the ion doping. The method further includes heating the substrate after the ion doping at a temperature from about 400° C. to about 500° C. | 11-29-2012 |
20120295412 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: providing a substrate having an active area and a gate structure on the active area and formed with a first interlayer dielectric layer thereon, wherein the first interlayer dielectric layer has a first open to expose a portion of a surface of the active area, and an upper surface of the first interlayer dielectric layer is substantially flush with an upper surface of the gate; filling the first open with a first conductive material to form a first portion of contact; forming a second interlayer dielectric layer over the first interlayer dielectric layer, the second interlayer dielectric layer having a second open to substantially expose an upper part of the first portion of the contact in the first open; and filling the second open with a second conductive material to form a second portion of the contact. | 11-22-2012 |
20120292699 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A semiconductor apparatus and a manufacturing method therefor is described. The semiconductor apparatus comprises a substrate and a gate structure for a N-channel semiconductor device above the substrate. A recess is formed at a lower end portion of at least one of two sides of the gate where it is adjacent to a source region and a drain region, of the N-channel semiconductor. The channel region of the N-channel semiconductor device has enhanced strain. The apparatus can further have a gate structure for a P-channel semiconductor device above the substrate. | 11-22-2012 |
20120292674 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and method for manufacturing the same are provided. A substrate with an active area and a first interlayer dielectric formed over the substrate is provided. The first interlayer dielectric has a first opening exposing a portion of a surface of the active area, the first opening being filled with a fill material. A second interlayer dielectric is formed over the first interlayer dielectric with a second opening substantially exposing an upper portion of the fill material in the corresponding first opening. The fill material is then removed and the first opening and the second opening are filled with a conductive material to form a contact. | 11-22-2012 |
20120292673 | Semiconductor Device and Manufacturing Method Thereof - A semiconductor device and manufacture method thereof is disclosed. The method includes: forming a gate on a substrate; forming a stack including a first material layer, a second material layer, and a third material layer from inner to outer in sequence; etching the stack to form sidewall spacers on opposite sidewalls of the gate; performing ion implantation to form a source region and a drain region; partially or completely removing the remaining portion of the third material layer; performing a pre-cleaning process, wherein all or a portion of the remaining portion of the second material layer is removed; forming silicide on top of the source region, the drain region, and the gate; depositing a stress film to cover the silicide and the remaining portion of the first material layer. According to the above method, the stress proximity technique (SPT) can be realized while avoiding silicide loss. | 11-22-2012 |
20120289017 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises placing a semiconductor substrate in an ashing chamber, the semiconductor substrate having a gate, a silicon nitride gate sidewall offset spacer or a silicon nitride gate sidewall pacer formed thereon, and a photo resist residue remaining on the semiconductor substrate, introducing a gas mixture including D | 11-15-2012 |
20120286370 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and method for manufacturing the same are disclosed. The method comprises: forming a gate insulating layer and a gate above a substrate; forming a spacer on both sides of the gate respectively; etching the substrate with the gate and spacers as mask to form indents; respectively forming a dummy sidewall on the side of the spacers opposite to the gate; etching substrate with the gate, spacers and dummy sidewalls as mask to form recesses which are deeper than the indents; removing the dummy sidewalls; and filling SiGe in the indents and recesses to form source/drain extent regions and source/drain regions of the semiconductor device; wherein before the step of filling SiGe, a step of heating the substrate to reflow the substrate material so as to at least change the shape of the side surface of the indent on the side close to the gate is implemented. | 11-15-2012 |