IMEC Patent applications |
Patent application number | Title | Published |
20150288894 | SPECTRAL CAMERA WITH MIRRORS FOR PROJECTING MULTIPLE ADJACENT IMAGE COPIES ONTO SENSOR ARRAY - A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, an array of mirrors, an array of filters for passing a different passband of the optical spectrum for different ones of the optical channels arranged so as to project multiple of the optical channels onto different parts of the same focal plane, and a sensor array at the focal plane to detect the filtered image copies simultaneously. By using mirrors, there may be less optical degradation and the trade off of cost with optical quality can be better. By projecting the optical channels onto different parts of the same focal plane a single sensor or coplanar multiple sensors can to be used to detect the different optical channels simultaneously which promotes simpler alignment and manufacturing. | 10-08-2015 |
20150276478 | SPECTRAL CAMERA WITH MOSAIC OF FILTERS FOR EACH IMAGE PIXEL - A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, a mosaic of filters for passing different bands of the optical spectrum, and a sensor array arranged to detect pixels of the image at the different bands passed by the filters, wherein for each of the pixels, the sensor array has a cluster of sensor elements for detecting the different bands, and the mosaic has a corresponding cluster of filters of different bands, integrated on the sensor element so that the image can be detected simultaneously at the different bands. Further, the filters are first order Fabry-Perot filters, which can give any desired passband to give high spectral definition. Cross talk can be reduced since there is no longer a parasitic cavity. | 10-01-2015 |
20150226766 | APPARATUS AND METHOD FOR ATOMIC FORCE MICROSCOPY - An apparatus ( | 08-13-2015 |
20150219584 | Biosensor Using Impedimetric Real-Time Monitoring - A method an system is disclosed for the detection and/or allocation of at least one point mutation in target DNA and/or RNA duplexes. The method comprises obtaining a functionalized surface which is coated with probe DNA and/or RNA whereto target DNA and/or RNA duplexes are attached, contacting said functionalized surface to an electrolytic solution having a neutral pH in a flow cell and measuring a first impedance value within said electrolytic solution, and then adding a chemical to the electrolytic solution which is able to achieve denaturation of the target DNA and/or RNA. The method further comprises measuring a second impedance value within the flow cell after completion of the denaturation of the DNA and/or RNA target, and then obtaining a value representative for the impact of the chemical on the impedance of the electrolytic solution. The amount and/or allocation of point mutation(s) within the target DNA and/or RNA is then determined by calculating the denaturation-time constant based on the difference between the first and second impedance value and taking into account the impact of the chemical by third impedance value. | 08-06-2015 |
20150214327 | Method for Producing a Semiconductor Device Comprising a Schottky Diode and a High Electron Mobility Transistor - A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device. | 07-30-2015 |
20150197742 | Plasma Membrane Isolation - The present invention relates to a population of monodisperse magnetic nanoparticles with a diameter between 1 and 100 nm which are coated with a layer with hydrophilic end groups. Herein the layer with hydrophilic end groups comprises an inner layer of monosaturated and/or monounsaturated fatty acids bound to said nanoparticles and bound to said fatty acids, an outer layer of a phospholipid conjugated to a monomethoxy polyethyleneglycol (PEG) comprising a hydrophilic end group, | 07-16-2015 |
20150130052 | METHOD FOR PRODUCING MICROBUMPS ON A SEMICONDUCTOR COMPONENT - The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings. | 05-14-2015 |
20150126010 | Band Engineered Semiconductor Device and Method for Manufacturing Thereof - The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device. | 05-07-2015 |
20140376816 | Analysis and Sorting of Objects in Flow | 12-25-2014 |
20140374919 | Method for Producing Contact Areas on a Semiconductor Substrate - Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components. | 12-25-2014 |
20140364076 | Method for Reducing Second Order Distortion in Harmonic Rejection Mixer - The present disclosure relates to a method for reducing second order intermodulation distortion in a harmonic rejection mixer arranged for down-converting a radio frequency signal to an in-phase and a quadrature baseband signal. The method includes adjusting an output current of a first mixer, to reduce the second order intermodulation distortion in the quadrature baseband signal to a first value, and adjusting an output current of a second mixer, to reduce the second order intermodulation distortion in the in-phase baseband signal to a second value. | 12-11-2014 |
20140363127 | Integrated Photonics Waveguide Grating Coupler - A photonic integrated device comprises a waveguide embedded in a photonic substrate. The waveguide has a waveguide radiation exit surface and the waveguide is optically connected to a two dimensional grating. The photonic integrated device also comprises a two dimensional grating having a plurality of curved elongate scattering elements. The two dimensional grating is adapted for diffracting radiation received from the waveguide toward a direction out of the photonic substrate and the curved elongate scattering elements are oriented with respect to the waveguide such that, for points of the scattering elements which can be irradiated by radiations stemming from the waveguide, normal lines to at least the curved elongate scattering element closest to the waveguide radiation exit surface do not substantially intersect with the waveguide radiation exit surface of the waveguide. | 12-11-2014 |
20140356892 | Optical Stimulation Device - In an aspect of the disclosure, a stimulation device includes a probe attached to a first support. The probe includes at least one grating coupler for coupling light into the probe. The device further includes at least one optical source for providing an optical stimulation signal mounted on a second support, and at least one means for detachably attaching the first support to the second support. The position of the at least one optical source is aligned with the position of the at least one grating coupler to allow light emitted from the at least one optical source to be received by the at least one grating coupler. | 12-04-2014 |
20140346568 | Low Temperature Ohmic Contacts for III-N Power Devices - The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess. | 11-27-2014 |
20140339680 | III-V Device and Method for Manufacturing Thereof - The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor. | 11-20-2014 |
20140339090 | Electric Controlled Micro-Fluidic Device - An example micro-fluidic device includes a micro-fluidic channel having an inner surface and a plurality of pillars positioned along the inner surface. The device further includes a plurality of power supplies connected to the pillars. Another example micro-fluidic device includes a micro-fluidic channel having an inner surface and a plurality of pillars positioned along the inner surface. The device further includes a power supply. The pillars are grouped into at least two groups of pillars, each group of pillars including at least two pillars, and all pillars of at least one group of pillars are connected to the power supply. In another example, a sensing system for detecting bioparticles includes a micro-fluidic device, wherein a surface of each pillar comprises functionalized plasmonic nanoparticles or functionalized SERS nanoparticles, a radiation source for radiating the micro-fluidic device, and a detector for detecting SERS signals or surface plasmon resonance. | 11-20-2014 |
20140335274 | Deposition of Nano-Diamond Particles - The present invention relates to a method ( | 11-13-2014 |
20140332864 | Method for Providing a Gate Metal Layer of a Transistor Device and Associated Transistor - A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the dummy gate electrode, and providing a final gate electrode layer in between the inner sidewalls of the set of spacers. Providing the final gate electrode layer further includes providing a diffusion layer that extends on top of the gate dielectric layer, on inner sidewalls of the spacers, and on a portion of a front surface of embedding layers for the dummy gate structure. Providing the final gate electrode also includes providing a metal on top of the diffusion layer, applying an anneal step, and filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer. The present disclosure also relates to an associated transistor. | 11-13-2014 |
20140319378 | OPTICAL FLUORESCENCE-BASED CHEMICAL AND BIOCHEMICAL SENSORS AND METHODS FOR FABRICATING SUCH SENSORS - An optical fluorescence-based sensor comprising at least one sensing element is disclosed. In one aspect, the at least one sensing element comprises a waveguide comprising a waveguide core, a light source optically coupled to an input part of the waveguide core, and a photodetector optically coupled to an output part of the waveguide core, the waveguide core being made of a material comprising a mixture of an optical material and a fluorescent dye. | 10-30-2014 |
20140306235 | Method for Producing a Semiconductor Device Comprising a Schottky Diode and a High Electron Mobility Transistor - A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device. | 10-16-2014 |
20140300379 | TWO-STEP INTERCONNECT TESTING OF SEMICONDUCTOR DIES - The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element. | 10-09-2014 |
20140292323 | Two Axes MEMS Resonant Magnetometer - A two-axes MEMS magnetometer includes, in one plane, a freestanding rectangular frame having inner walls and four torsion springs, wherein opposing inner walls of the frame are contacted by one end of only two torsion springs, each torsion spring being anchored by its other end, towards the centre of the frame, to a substrate. In operation, the magnetometer measures the magnetic field in two orthogonal sensing modes using differential capacitance measurements. | 10-02-2014 |
20140289457 | METHOD AND DEVICE TO REDUCE LEAKAGE AND DYNAMIC ENERGY CONSUMPTION IN HIGH-SPEED MEMORIES - A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit. | 09-25-2014 |
20140284221 | Method and Device for Identifying Cells - The present invention provides a method to analyze or identify a cell. The method comprises: providing a cell, stimulating the cell with a stimulant thereby modifying a cell membrane impedance of the cell, monitoring the cell membrane impedance of the cell and identifying the cell based on the monitored cell membrane impedance. A corresponding device is also provided. | 09-25-2014 |
20140267878 | SPECTRAL CAMERA WITH OVERLAPPING SEGMENTS OF IMAGE COPIES INTERLEAVED ONTO SENSOR ARRAY - A spectral camera having an objective lens, an array of lenses for producing optical copies of segments of the image, an array of filters for the different optical channels and having an interleaved spatial pattern, and a sensor array to detect the copies of the image segments is disclosed. Further, detected segment copies of spatially adjacent optical channels have different passbands and represent overlapping segments of the image, and detected segment copies of the same passband on spatially non-adjacent optical channels represent adjacent segments of the image which fit together. Having segments of the image copied can help enable better optical quality for a given cost. Having an interleaved pattern of the filter bands with overlapping segments enables each point of the image to be sensed at different bands to obtain the spectral output for many bands simultaneously to provide better temporal resolution. | 09-18-2014 |
20140267849 | SPECTRAL CAMERA WITH INTEGRATED FILTERS AND MULTIPLE ADJACENT IMAGE COPIES PROJECTED ONTO SENSOR ARRAY - A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, an optical duplicator, an array of filters, and a sensor array arranged to detect the filtered image copies simultaneously on different parts of the sensor array. Further, a field stop defines an outline of the image copies projected on the sensor array. The filters are integrated on the sensor array, which has a planar structure without perpendicular physical barriers for preventing cross talk between each of the adjacent optical channels. The field stop enables adjacent image copies to fit together without gaps for such barriers. The integrated filters mean there is no parasitic cavity causing crosstalk between the adjacent image copies. This means there is no longer a need for barriers between adjacent projected image copies, and thus sensor area can be better utilized. | 09-18-2014 |
20140252414 | Passivated III-V or Ge Fin-Shaped Field Effect Transistor - A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h′, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device. | 09-11-2014 |
20140242605 | Heat-Transfer Resistance Based Analysis of Bioparticles - A bio-sensing device suitable for the detection and/or characterization of target bioparticles and corresponding method is described. The bio-sensing technique is based on the impact on the heat transfer resistivity value of bioparticles binding in binding cavities of a structured substrate. By sensing temperatures and determining a heat transfer resistivity value based thereon, a characteristic of the target bioparticles can be derived. | 08-28-2014 |
20140239461 | Oxygen Monolayer on a Semiconductor - A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si | 08-28-2014 |
20140231968 | Conformal Anti-Reflective Coating - In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film. | 08-21-2014 |
20140187039 | Method for Tuning the Effective Work Function of a Gate Structure in a Semiconductor Device - A method for tuning the effective work function of a gate structure in a semiconductor device is described. The semiconductor device is part of an integrated circuit and the gate structure has a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor device. The method includes providing an interconnect structure of the integrated circuit on top of the gate structure, the interconnect structure comprising a layer stack comprising at least a pre-metal dielectric layer comprising a metal filled connecting via connected to the gate structure through the pre-metal dielectric layer, and the interconnect structure having an upper exposed metal portion; and, thereafter, exposing at least a portion of the upper exposed metal portion to a plasma under predetermined exposure conditions, to tune the effective work function of the gate structure. | 07-03-2014 |
20140186936 | DNA CHIP WITH MICRO-CHANNEL FOR DNA ANALYSIS - A DNA chip with micro-channel for DNA analysis of DNA included in an analyte according to a PCR method is a DNA chip with micro-channel for DNA analysis in which is silicon (first layer) and plastic (second layer) are laminated, wherein the second layer is formed on a partial area of the first layer, and the second layer includes: a reagent; a liquid transporting system; and a sensor, and the first layer includes a PCR reactor provided on an area on which the second layer is not formed. | 07-03-2014 |
20140186846 | DNA CHIP WITH MICRO-CHANNEL FOR DNA ANALYSIS - Provided is a DNA chip with micro-channel for DNA analysis, which has a structure in which a silicon layer (chip A) and a plastic layer (chip B) are laminated, wherein the chip A includes at least two PCR reactors connected in series in a micro-channel, and a filter between the PCR reactors, the chip B includes a reagent, a liquid delivery mechanism and a sensor in a micro-channel, and the reagent, liquid delivery mechanism and sensor can be changed according to a kind of an analyte and an object to be detected. | 07-03-2014 |
20140185042 | MOLECULAR ANALYSIS DEVICE - In the present invention, a molecular analysis device comprises a substrate, and a waveguide with a planar integrating element and filter or reflector element adjacent thereto is disposed on the substrate. The waveguide comprises a coupling means configured for coupling a predetermined frequency range of laser radiation into the waveguide. At least one metallic nanostructure is disposed on or adjacent to the planar integrating element, at least one metallic nanostructure is configured such that the field intensity and the gradient of the laser radiation, that is coupled into the waveguide, are enhanced over a sufficiently large volume around the nanostructure to simultaneously cause plasmonic based optical trapping of analyte(s) in a medium, and plasmonic based excitation of the particles to produce Raman scattered radiation. A Raman scattered radiation collection means is disposed on the substrate for collecting said Raman scattered radiation produced by the particles. | 07-03-2014 |
20140179054 | METHOD FOR FORMING PATTERNS OF DIFFERENTLY DOPED REGIONS - The disclosed technology generally relates to forming patterns of doped semiconductor regions, and more particularly to methods of forming such patterns in fabricating photovoltaic devices. In one aspect, a method of forming a pattern of different doped regions at the same side of a semiconductor substrate comprises providing a patterned doped layer on a surface of the semiconductor substrate at predetermined locations where at least one first doped region is to be formed. The method additionally includes selectively growing at least one second doped region epitaxially at the same side of the semiconductor substrate using the patterned doped layer as an epitaxial growth mask. Furthermore, selectively growing comprises driving dopants from the patterned doped layer into the semiconductor substrate to form the first doped region at the predetermined locations. | 06-26-2014 |
20140176957 | Integrated Optical Sensor Circuit - A photonics integrated system is disclosed, comprising a substrate, an integrated interferometer integrated in the substrate and being configured for receiving radiation from a radiation source, and an integrated spectral filter integrated in the substrate and being configured for receiving radiation from the interferometer. The integrated interferometer has a period and the integrated spectral filter has a bandwidth such that the period of the integrated interferometer is smaller than the bandwidth of the integrated spectral filter. The integrated spectral filter has a periodic transfer characteristic with a period and the system has a bandwidth such that the period of the periodic transfer characteristic of the integrated spectral filter is larger than the bandwidth of the system. | 06-26-2014 |
20140176388 | TUNABLE IMPEDANCE NETWORK - A tunable impedance network and a method for tuning the tunable impedance network are disclosed. In one aspect, the tunable impedance network comprises a plurality of transformers connected in series. Each transformer has a primary winding and a secondary winding. The transformers have a voltage transformation ratio of N:1 with N>1. An impedance structure, acting as a resonant circuit together with the inductance of the secondary winding, is connected at the secondary winding of each transformer. A control circuit or processor is configured to tune the imaginary part of at least one of the impedance structures so as to change its resonance frequency to mimic a reference impedance. The control circuit is further configured to tune the real part of at least one of the impedance structures so as to change its Q-factor to mimic the reference impedance. | 06-26-2014 |
20140175891 | Current Generator - A current generator is disclosed. An example current generator includes a plurality of current cells connected in parallel, each current cell being connected to a switch. The current generator further includes a first summer configured to sum the output of each current cell of a first subset of the plurality of current cells and a second summer configured to sum the output of each current cell of a second subset of the plurality of current cells. The current generator also includes a combiner configured to combine the outputs of the first and second summers. Further, each switch is switchable according to a sequence to generate a summed output of the current cells at a plurality of quantization levels to generate positive and/or negative alternations of a pseudo-sinusoidal, alternating current. | 06-26-2014 |
20140175676 | Method for Bonding of Group III-Nitride Device-on-Silicon and Devices Obtained Thereof - A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide. | 06-26-2014 |
20140175265 | Spectral Imaging Device and Method to Calibrate the Same - A solid-state spectral imaging device is described. The device includes an image sensor and a plurality of optical filters directly processed on top of the image sensor. Each optical filter includes a first mirror and a second mirror defining an optical filter cavity having a fixed height. Each optical filter also includes a first electrode and a second electrode having a fixed position located opposite to each other and positioned to measure the height of the optical filter cavity. Further, a method to calibrate spectral data of light and a computer program for calibrating light is described. | 06-26-2014 |
20140174994 | Micro-Fluidic Device for Sorting Particles, and Methods for Sorting Particles - A method and device for the sorting and focusing of suspended particles is disclosed. The device has a micro-fluidic channel, at least one inlet and a number of outlets for providing, sorting and receiving particles. A patterned array of grooves is present inside the micro-fluidic channel. The inlets and outlets are connected to the micro-fluidic channel. The particles are sorted by the array of grooves. The method consists of providing particles in a flow-focused manner to one end of the micro-fluidic channel using at least one inlet. The particles are sorted by the array of grooves present in the micro-fluidic channel. Particles are collected by a number of outlets which are connected to the other end of the micro-fluidic channel. | 06-26-2014 |
20140174526 | INTERDIGITATED ELECTRODE FORMATION - The disclosed technology generally relates to photovoltaic devices and methods of fabricating photovoltaic devices, and more particularly relates to interdigitated back contact photovoltaic cells and methods of fabricating the same. In one aspect, a method of forming first and second interdigitated electrodes on a semiconductor substrate comprises providing a dielectric layer on the rear surface of the semiconductor substrate. The method additionally comprises providing a metal seed layer on the dielectric layer. The method additionally comprises patterning the metal seed layer by laser ablation, thereby separating it into a first seed layer and a second seed layer with a separation region interposed therebetween, wherein the first seed layer and the second seed layer are interdigitated and electrically isolated from each other. The method further comprises thickening the first seed layer and the second seed layer by plating, thereby forming the first electrode and the second electrode. | 06-26-2014 |
20140170837 | Methods for Manufacturing Semiconductor Devices - A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface. | 06-19-2014 |
20140169724 | Thermally Stabilised Resonant Electro-Optic Modulator and Use Thereof - Thermally stabilised resonant electro-optic modulator ( | 06-19-2014 |
20140169237 | CIRCUIT FOR BASEBAND HARMONIC REJECTION - A circuit for reducing counter-intermodulation in a modulated signal caused by an oscillator frequency and harmonics of a baseband signal is disclosed. The circuit comprises a first and a second baseband section arranged for generating a first and a second version of a baseband signal, the second version being phase shifted with respect to the first version. The circuit further comprises three signal paths comprising mixers for multiplication of the first and second version of the baseband signal with a local oscillator signal, so that three upconverted signals with rotated phase with respect to each other are obtained, and arranged for applying a scaling with a scaling factor corresponding to the rotated phases. The circuit further comprises a combination unit arranged for combining the three upconverted signals. | 06-19-2014 |
20140161384 | Integrated Photonic Devices with Reduced Sensitivity to External Influences - One aspect of the invention relates to a photonic device having a wavelength-dependent transmission or filter characteristic, comprising: a Splitter Polarization Rotator receiving polarized light and providing a first resp. second wave; a first resp. second waveguide arm connected to the SPR for propagating a first resp. second polarization mode (TM, TE) of the first resp. second wave, the second polarization mode being different from the first polarization mode; and a Polarization Rotator and Combiner for combining the propagated first resp. second waves; wherein the dimensions of the first and second arm are selected to cancel the influence of an external effect on the wavelength-dependent characteristic. Another aspect of the invention relates to a method for reducing the sensitivity of said integrated photonic device, comprising splitting a polarized light beam, propagating light waves of different polarity through two waveguide arms of specific dimensions, and recombining them. | 06-12-2014 |
20140160835 | SPIN TRANSFER TORQUE MAGNETIC MEMORY DEVICE - A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material. | 06-12-2014 |
20140159118 | III-Nitride Transistor with Source-Connected Heat Spreading Plate - Disclosed are semiconductor devices and methods for manufacturing them. An example device may include a III-nitride stack having a front side surface and a back side surface. The III-nitride stack may be formed of at least a first layer and a second layer, between which a heterojunction may be formed, such that a two-dimensional electron gas layer is formed in the second layer. A source electrode, a drain electrode, and a gate electrode positioned between the source and drain electrodes may be formed on the front side surface, and an insulation layer may be formed over the electrodes on the front side surface. A carrier substrate may be attached to the insulation layer. An electrically conductive back plate may be formed on the back side surface. The back plate may directly face the source electrode and the gate electrode, but not the drain electrode. | 06-12-2014 |
20140151848 | MIMCAP STRUCTURE IN A SEMICONDUCTOR DEVICE PACKAGE - The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP is formed between a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures. | 06-05-2014 |
20140151766 | FinFET DEVICE WITH DUAL-STRAINED CHANNELS AND METHOD FOR MANUFACTURING THEREOF - A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed. | 06-05-2014 |
20140145554 | ELECTRET ELEMENT AND VIBRATION POWER GENERATING DEVICE USING THE SAME - In an electret element | 05-29-2014 |
20140138787 | Avalanche Photodetector Element - An avalanche photodetector element is disclosed for converting an optical signal to an electrical signal, comprising an input waveguide and a photodetector region, the photodetector region comprising at least one intrinsic region, at least one p-doped region and at least one n-doped region, the doped regions and the at least one intrinsic region forming at least one PIN-junction avalanche photodiode, the input waveguide and the photodetector region being arranged with respect to each other such that the optical signal conducted by the input waveguide is substantially conducted into the photodetector region to the PIN-junction avalanche photodiode, the PIN-junction avalanche photodiode converting the optical signal to an electrical signal, characterized in that the photodetector region comprises more than one p-doped region and/or n-doped region, whereby these p-doped regions and/or n-doped regions are physically arranged as an array. | 05-22-2014 |
20140137123 | MICROCOMPUTER FOR LOW POWER EFFICIENT BASEBAND PROCESSING - A microcomputer for executing an application is described. The microcomputer comprises a heterogeneous coarse grained reconfigurable array comprising a plurality of functional units, optionally register files, and memories, and at least one processing unit supporting multiple threads of control. The at least one processing unit is adapted for allowing each thread of control to reconfigure at run-time the claiming of one or more particular types of the functional units to work for that thread depending on requirements of the application, e.g. workload, and/or the environment, e.g. current usage of FU's. This way, multithreading with dynamic allocation of CGA resources is implemented. Based on the demand of the application and the current utilization of the CGRA, different resource combinations can be claimed. | 05-15-2014 |
20140131839 | Etching Method Using Block-Copolymers - A method for lithography is disclosed. The method includes obtaining a self-organizing block-copolymer layer on a neutral layer overlying a substrate, the self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, the self-organizing block-copolymer layer furthermore comprising a copolymer pattern structure formed by micro-phase separation of the at least two polymer components. Further, the method includes etching selectively a first polymer component of the self-organizing block-copolymer layer, thereby remaining a second polymer component. Still further, the method includes applying a plasma etching to the neutral layer using the second polymer component as a mask, wherein the plasma etching comprises an inert gas and H | 05-15-2014 |
20140124894 | SEMICONDUCTOR DEVICE COMPRISING A DIODE AND A METHOD FOR PRODUCING SUCH A DEVICE - The disclosed technology relates to a semiconductor device comprising a diode junction between two semiconductor regions of different doping types. In one aspect, the diode comprises a junction formed between an upper portion of an active area and a remainder of the active area, where the active area is defined in a substrate between two field dielectric regions. The upper portion is a portion of the active area that has a width smaller than a width of the active area itself. In another aspect, the semiconductor device is an electrostatic discharge protection device (ESD) comprising such a diode. In addition, the active area has a doping profile that exhibits a maximum value at the surface of the active area, and changes to a minimum value at a first depth, where the first depth can be greater in value than half of a depth of the upper portion. In another aspect, a method of fabrication the device does not require a separate ESD implant for lowering the holding voltage and can allow for a reduction in the number of processing steps as well as other devices comprising a diode junction. | 05-08-2014 |
20140111243 | TRANSITION DELAY DETECTOR FOR INTERCONNECT TEST - A test circuitry configured to test for transition delay defects in inter-die interconnects is disclosed. In one aspect, the test circuitry comprises an input port configured to receive a test data value and a data storage element configured to temporarily store the test data value. The test circuitry additionally comprises a second inter-die interconnect configured to be electrically connected to a first inter-die interconnect so as to form a feedback loop for transferring the test data value from the data storage element back to the data storage element. The test circuitry additionally comprises a data conditioner configured to condition the fed back test data value so as to make it distinguishable from the stored test data value. The test circuitry additionally comprises a clock pulse generator configured to generate a delayed clock pulse. The test circuitry additionally comprises a selection logic configured to apply the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. The test circuitry further comprises a readout unit for reading out a test data value stored in the data storage element. | 04-24-2014 |
20140107458 | Resilient Sensor for Biopotential Measurements - A sensor for biopotential measurement, comprising: an electrical contacting unit for establishing an electrical contact with an animal or human skin, the electrical contacting unit being resilient. The sensor comprises a housing comprising a cavity wherein the electrical contacting unit is partially secured, and means for maintaining said electrical contacting unit in a resiliently deformed state when in contact with said skin. | 04-17-2014 |
20140106556 | METHOD FOR MANUFACTURING A DUAL WORK FUNCTION SEMICONDUCTOR DEVICE - A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element. The method additionally includes annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer, and subsequently removing the first metal layer/stack and the second metal layer/stack. The method further includes forming a third metal layer/stack in the first and second predetermined areas. | 04-17-2014 |
20140103357 | SCHOTTKY DIODE STRUCTURE AND METHOD OF FABRICATION - The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material. The anode is configured such that the second portion is horizontally located between the anode and the cathode and the dielectric material is configured to pinch off the 2DEG layer in a reverse biased configuration of the device. The device further includes a passivation area formed between the anode and the cathode to horizontally separate the anode and the cathode from each other. | 04-17-2014 |
20140099796 | METHOD FOR DEVELOPING LOW DIELECTRIC CONSTANT FILM AND DEVICES OBTAINED THEREOF - A method for porogen removal of porous SiOCH film is provided, as well as devices obtained thereof. The devices and associated methods are in the field of advanced semiconductor interconnect technology, and more in particular in the development of dielectric films with low-k value. | 04-10-2014 |
20140099774 | Method for Producing Strained Ge Fin Structures - Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer. | 04-10-2014 |
20140092670 | NON-VOLATILE RESISTIVE MEMORY DEVICES AND METHODS FOR BIASING RESISTIVE MEMORY STRUCTURES THEREOF - The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor. | 04-03-2014 |
20140091435 | Etching of Block-Copolymers - The present disclosure relates to a method ( | 04-03-2014 |
20140079921 | Hierarchical Carbon Nano and Micro Structures - Disclosed are methods for fabricating pyrolysed carbon nanostructures. An example method includes providing a substrate, depositing a polymeric material, subjecting the polymeric material to a plasma etching process to form polymeric nanostructures, and pyrolysing the polymeric nanostructures to form carbon nanostructures. The polymeric material comprises either compounds with different plasma etch rates or compounds that can mask a plasma etching process. The plasma etching process may be an oxygen plasma etching process. | 03-20-2014 |
20140077332 | Band Engineered Semiconductor Device and Method for Manufacturing Thereof - The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device. | 03-20-2014 |
20140070972 | Circuit For Digitizing A Sum Of Signals - A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quanitzer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal. | 03-13-2014 |
20140068822 | Method for Determining Local Resistivity and Carrier Concentration Using Scanning Spreading Resistance Measurement Set-Up - The disclosure is related to an SSRM method for measuring the local resistivity and carrier concentration of a conductive sample. The method includes contacting the conductive sample at one side with an AFM probe and at another side with a contact electrode, modulating, at a modulation frequency, the force applied to maintain physical contact between the AFM probe and the sample while preserving the physical contact between the AFM probe and the sample, thereby modulating at the modulation frequency the spreading resistance of the sample; measuring the current flowing through the sample between the AFM probe and the contact electrode; and deriving from the measured current the modulated spreading resistance. Deriving the modulated spreading resistance includes measuring the spreading current using a current-to-voltage amplifier, converting the voltage signal into a resistance signal, and filtering out from the resistance signal, the resistance amplitude at the modulation frequency. | 03-06-2014 |
20140065794 | Method for Forming a Buried Dielectric Layer Underneath a Semiconductor Fin - Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin. | 03-06-2014 |
20140061735 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; depositing a metal layer on the capping layer; performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; selectively removing non-consumed metal from the substrate by means of the predetermined etchant; and providing a premetal dielectric layer. | 03-06-2014 |
20140054771 | Method for Self-Assembly of Substrates and Devices Obtained Thereof - A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic. | 02-27-2014 |
20140053864 | System for Delivering Ultrasonic Energy to a Liquid and Use for Cleaning of Solid Parts - This present application relates to a system for delivering megasonic energy to a liquid, involving one or more megasonic transducers, each transducer having a single operating frequency within an ultrasound bandwidth and comprising two or more groups of piezoelectric elements arranged in one or more rows, and a megasonic generator means for driving the one or more transducers at frequencies within the bandwidth, the generator means being adapted for changing the voltage applied to each group of piezoelectric elements so as to achieve substantially the same maximum acoustic pressure for each group of piezoelectric elements. The generator means and transducers being constructed and arranged so as to produce ultrasound within the liquid. Such a system may be part of an apparatus for cleaning a surface of an article such as a semiconductor wafer or a medical implant. | 02-27-2014 |
20140045315 | METHODS FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE - A method of fabricating a field-effect transistor is disclosed. In one aspect, the method includes forming a channel layer comprising germanium over a substrate. The method additionally includes forming a gate structure on the channel layer, where the gate structure comprises a gate layer comprising silicon, and the gate layer has sidewalls above a surface of the channel layer. The method additionally includes forming sidewall spacers comprising silicon dioxide on the sidewalls by subjecting the gate structure to a solution adapted for forming a chemical silicon oxide on materials comprising silicon. The method further includes forming elevated source/drain structures on the channel layer adjacent to the gate structure by selectively epitaxially growing a source/drain material on the channel layer. | 02-13-2014 |
20140040594 | PROGRAMMABLE DEVICE FOR SOFTWARE DEFINED RADIO TERMINAL - A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters. | 02-06-2014 |
20140038426 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES - A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface. | 02-06-2014 |
20140034894 | Insulator Material for Use in RRAM - The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including
| 02-06-2014 |
20140008730 | Complementary Metal-Oxide-Semiconductor Device Comprising Silicon and Germanium and Method for Manufacturing Thereof - Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si | 01-09-2014 |
20130341702 | Vertical Memory Device and Method for Making Thereof - Described herein is a method for forming a vertical memory device ( | 12-26-2013 |
20130341701 | Vertical Semiconductor Memory Device and Manufacturing Method Thereof - Disclosed are vertical semiconductor devices and methods of manufacturing vertical semiconductor devices. An example method includes providing a semiconductor substrate, and forming a stack of horizontal layers on the semiconductor substrate, where the horizontal layers are substantially parallel to a surface of the semiconductor substrate, and the horizontal layers comprise alternating conductive layers and dielectric layers. The method further includes forming a vertical channel region through the stack of horizontal layers, where the vertical channel region is substantially perpendicular to a surface of the semiconductor substrate, and the vertical channel region comprises sidewall surfaces. The method further includes forming a charge storage layer on regions of the sidewall surfaces of the vertical channel region that are in direct contact with conductive layers in the stack of horizontal layers and, at a distance from the vertical channel region, forming a vertical dielectric region through the stack of horizontal layers. | 12-26-2013 |
20130335744 | METHOD FOR DETERMINING THE DOPING PROFILE OF A PARTIALLY ACTIVATED DOPED SEMICONDUCTOR REGION - A method is disclosed for determining the inactive doping concentration of a semiconductor region using a PMOR method. In one aspect, the method includes providing two semiconductor regions having substantially the same known as-implanted concentration but known varying junction depths. The method includes determining on one of these semiconductor regions the as-implanted concentration. The semiconductor regions are then partially activated. PMOR measures are then performed on the partially activated semiconductor regions to measure (a) the signed amplitude of the reflected probe signal as function of junction depth and (b) the DC probe reflectivity as function of junction depth. The method includes extracting from these measurements the active doping concentration and then calculating the inactive doping concentration using the determined total as-implanted concentration and active doping concentration. The method may also include extracting thermal diffusivity, refraction index, absorption coefficient, and/or SRHF lifetime from these measurements. | 12-19-2013 |
20130334500 | TUNNEL FIELD EFFECT TRANSISTOR DEVICE AND METHOD FOR MAKING THE DEVICE - A Tunnel Field Effect Transistor device (TFET) made of at least following layers: a highly doped drain layer, a highly doped source layer, a channel layer, a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer, and a highly doped pocket layer extending in between and along the gate dielectric layer and the source layer, characterized in that the pocket layer extends to between and along the source layer and the channel layer. | 12-19-2013 |
20130333741 | LOW VOLTAGE DROP UNIDIRECTIONAL SMART BYPASS ELEMENTS - Described herein is a low-voltage unidirectional bypass element connected across a solar cell and operable to allow current to flow when the operation of the solar cell is suspended. The bypass element includes a single field effect transistor connected between first and second terminals as a switch, and a detection circuit for detecting suspension of the solar cell's operation and activating the switch to bypass the solar cell in the event of its operation suspension. Diodes are connected in parallel with the normally-open switch and receive current, when the solar cell's operation is suspended, to trigger operation of the detection circuit. The detection circuit includes a charge pump, a timer circuit, a control generation unit and a switch control circuit. The switch control circuit generates a control signal to close the switch and to allow current to bypass the solar cell. | 12-19-2013 |
20130327656 | Biosensor Using Impedimetric Real-Time Monitoring - A method an system is disclosed for the detection and/or allocation of at least one point mutation in target DNA and/or RNA duplexes. The method comprises obtaining a functionalized surface which is coated with probe DNA and/or RNA whereto target DNA and/or RNA duplexes are attached, contacting said functionalized surface to an electrolytic solution having a neutral pH in a flow cell and measuring a first impedance value within said electrolytic solution, and then adding a chemical to the electrolytic solution which is able to achieve denaturation of the target DNA and/or RNA. The method further comprises measuring a second impedance value within the flow cell after completion of the denaturation of the DNA and/or RNA target, and then obtaining a value representative for the impact of the chemical on the impedance of the electrolytic solution. The amount and/or allocation of point mutation(s) within the target DNA and/or RNA is then determined by calculating the denaturation-time constant based on the difference between the first and second impedance value and taking into account the impact of the chemical by third impedance value. | 12-12-2013 |
20130313522 | GRAPHENE-BASED SEMICONDUCTOR DEVICE - A semiconductor device is provided comprising a bilayer graphene comprising a first and a second adjacent graphene layer, and a first electrically insulating layer contacting the first graphene layer, the first electrically insulating layer comprising an electrically insulating material, and a substance suitable for creating free charge carriers of a first type in the first graphene layer, the semiconductor device further comprising an electrically insulating region contacting the second graphene layer and suitable for creating free charge carriers of a second type, opposite to the first type, in the second graphene layer. | 11-28-2013 |
20130308860 | Feature Detection in Numeric Data - A method for detecting features in digital numeric data comprises obtaining digital numeric data comprising values corresponding to a plurality of sampling points over a domain space having at least one dimension, computing a plurality of scale-space data comprising filtering said digital numeric data using a filter bank, determining a plurality of feature regions each corresponding to a local extremum in scale and location of the scale-space data; and determining a feature region descriptor for each of said plurality of feature regions. The filter bank is a Cosine Modulated Gaussian filter bank in which the standard deviation parameter of the Gaussian equals | 11-21-2013 |
20130305087 | METHOD AND SYSTEM FOR REAL-TIME ERROR MITIGATION - A method of organizing on-chip data memory in an embedded system-on-chip platform whereon a deterministic application needs to meet a guaranteed constraint on its functional system behavior is disclosed. In one aspect, the method includes: a) dividing the deterministic application into blocks one of which corresponds to a part of a subtask of the application, the block receiving input data and/or generating output data and including internal intermediate data for transforming the input data into the output data, b) splitting the internal intermediate data into state and non-state data, and c) putting the non-state data and a part of the state data in a protected buffering module being part of the data memory and being provided with an error detection and correction module, so that they are available for mitigating the effect of faults on the functional system behavior on-line while meeting the at least one guaranteed constraint. | 11-14-2013 |
20130296187 | Microfluidics System for Sequencing - A sensor chip ( | 11-07-2013 |
20130296174 | Microfluidics System for Sequencing - A microfluidic chip ( | 11-07-2013 |
20130278982 | Device and Method for Holographic Reflection Imaging - A holographic imaging device for imaging an object under study includes a partially reflective surface having a contact side for contacting the object under study and an imaging side for partially reflecting a radiation wave. The device also includes at least one radiation source for projecting the radiation wave onto the imaging side of the partially reflective surface and an image sensor arranged to receive the radiation wave when reflected by the partially reflective surface. The image sensor is adapted for determining an interference pattern between the radiation wave reflected by the imaging side of the partially reflective surface and the radiation wave reflected by the object under study when contacting the contact side of the partially reflective surface. | 10-24-2013 |
20130278981 | Device and Method for Holographic Reflection Imaging - Methods and devices for holographic imaging are disclosed. In some embodiments, a holographic imaging device is disclosed that includes at least one radiation source, a reflective surface, and an image sensor. The at least one radiation source may be configured to emit a radiation wave towards the reflective surface and an object positioned on or near the reflective surface, where the radiation wave is reflected by the reflective surface to produce a reference wave and is reflected directly toward the image sensor by the object to produce an object wave directed at the image sensor. Further, the image sensor may be configured to determine an interference pattern between the reference wave and the object wave. A holographic image representing the object may be reconstructed based on the interference pattern. | 10-24-2013 |
20130251978 | Method for Pore Sealing of Porous Materials Using Polyimide Langmuir-Blodgett Film - Method for pore sealing a porous substrate, comprising: forming a continuous monolayer of a polyimide precursor on a liquid surface, transferring said polyimide precursor monolayer onto the porous substrate with the Langmuir-Blodgett technique, and imidization of the transferred polyimide precursor monolayers, thereby forming a polyimide sealing layer on the porous substrate. Porous substrate having at least one surface on which a sealing layer is provided to seal pores of the substrate, wherein the sealing layer is a polyimide having a thickness of a few monolayers and wherein there is no penetration of the polyimide into the pores. | 09-26-2013 |
20130240030 | METHOD FOR FABRICATING THIN PHOTOVOLTAIC CELLS - A method for fabricating thin crystalline photovoltaic cells is disclosed. In one aspect, the method includes: forming a weakening layer in a surface portion of a semiconductor substrate; epitaxially growing a stack of semiconductor layers on the substrate for forming an active layer of the photovoltaic cell, the stack having a first thermal coefficient of expansion; providing on the stack patterned contact layer for forming electrical contacts of the photovoltaic cell, the patterned contact layer having a second thermal coefficient of expansion different from the first thermal coefficient of expansion. The process of providing a patterned contact layer simultaneously induces a tensile stress in the weakening layer, resulting in a lift-off from the substrate of a structure including the stack of semiconductor layers and the patterned contact layer. | 09-19-2013 |
20130237055 | METHOD OF REDISTRIBUTING FUNCTIONAL ELEMENT - According to a method of redistributing a functional element of the present invention, an insulating resin layer is supplied onto a functional element wafer such as an LSI. A portion to be a via hole on an electrode pad of the functional element is filled with a sacrificial layer. The top of the sacrificial layer filled in the via hole is exposed from the insulating layer by grinding or polishing. Therefore, it is possible to prevent breakage of a brittle material such as a low-k material in the functional element, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. The reliability, the yield, and the level of flatness can be improved by forming an interconnection conductive layer after the flattening process of grinding or polishing. Accordingly, a fine conductive interconnection can be formed. | 09-12-2013 |
20130237021 | ENHANCEMENT MODE FIELD EFFECT DEVICE AND THE METHOD OF PRODUCTION THEREOF - A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed. | 09-12-2013 |
20130233238 | Methods and Mask Structures for Substantially Defect-Free Epitaxial Growth - Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening. | 09-12-2013 |
20130214947 | Device, System and Method for Analogue-to-Digital Conversion Using a Current Integrating Circuit - A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal. | 08-22-2013 |
20130214946 | A/D Converter and Method for Calibrating the Same - An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analogue non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal. | 08-22-2013 |
20130214870 | Robust Injection-Locked Local Oscillator - The present disclosure relates to an injection-locked local oscillator and a method for calibrating the same. The local oscillator includes an active circuit having at least one first resonator connected to the output of the active circuit, and at least one second resonator coupled to the at least one first resonator, thereby forming at least one coupled resonator. In another aspect, the present disclosure relates to a method for calibrating a local oscillator, the calibration being a two-step calibration based mainly on power measurement. | 08-22-2013 |
20130214863 | Front-End System for Radio Devices - The present disclosure relates to a front-end system for a radio device, the front-end system comprising a low-noise amplifier (LNA), arranged for receiving a radio frequency input signal (RF | 08-22-2013 |
20130200320 | Self-Isolated Conductive Bridge Memory Device - A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator. | 08-08-2013 |
20130198594 | Methods for Viterbi Decoder Implementation - Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget. | 08-01-2013 |
20130194577 | METHOD FOR DETERMINING AN ACTIVE DOPANT PROFILE - A method for determining an active dopant concentration profile of a semiconductor substrate based on optical measurements is disclosed. The active dopant concentration profile includes a concentration level and a junction depth. In one aspect, the method includes obtaining a photomodulated reflectance (PMOR) amplitude offset curve and a PMOR phase offset curve for the semiconductor substrate based on PMOR measurements, determining a decay length parameter based on a first derivative of the amplitude offset curve, determining a wavelength parameter based on a first derivative of the phase offset curve, and determining, from the decay length parameter and the wavelength parameter, the concentration level and the junction depth of the active dopant concentration profile. | 08-01-2013 |
20130187669 | Calibration of Micro-Mirror Arrays - A built-in self-calibration system and method for a micro-mirror array device, for example, operating as a variable focal length lens is described. The calibration method comprises determining a capacitance value for each micro-mirror element in the array device at a number of predetermined reference angles to provide a capacitance-reference angle relationship. From the capacitance values, an interpolation step is carried to determine intermediate tilt angles for each micro-mirror element in the array. A voltage sweep is applied to the micro-mirror array and capacitance values, for each micro-mirror element in the array, are measured. For a capacitance value that matches one of the values in the capacitance-reference angle relationship, the corresponding voltage is linked to the associated tilt angle to provide a voltage-tilt angle characteristic which then stored in a memory for subsequent use. | 07-25-2013 |
20130187113 | Nonvolatile Memory Device Comprising a Metal-to-Insulator Transition Material - A nonvolatile memory device is disclosed comprising a metal-to-insulator transition material thermally coupled to a Peltier element. During programming, a selected current is flowing through the Peltier element, the level thereof determining whether the temperature of the Peltier element and hence of the thermally coupled metal-to-insulator transition material decreases or increases. In response to this temperature change, the metal-to-insulator transition material will change from one electrical conduction phase to another. The memory device is read by applying current through the metal-to-insulator transition material, the current level being selected to maintain the phase of the metal-to-insulator transition material. | 07-25-2013 |
20130181301 | METHOD FOR MANUFACTURING A FIELD-EFFECT SEMICONDUCTOR DEVICE FOLLOWING A REPLACEMENT GATE PROCESS - A method of manufacturing a semiconductor device is disclosed. In one aspect, the method includes: forming a dummy gate over a substrate layer; forming first gate insulating spacers adjacent to sidewalls of the dummy gate and over the substrate layer, the first spacers having two sidewalls and two surface profiles where the sidewalls meet the substrate layer; forming a source and drain region using the surface profiles; forming second gate insulating spacers adjacent to the sidewalls of the first spacers and over the source and drain regions; removing the dummy gate and the first spacers, thereby forming a first recess; depositing a dielectric layer in the first recess along the side walls of the second spacers and over the substrate layer, thereby forming a second recess; and depositing a gate electrode in the second recess. | 07-18-2013 |
20130177856 | METHOD FOR PRODUCING A LED DEVICE - A method is provided for producing a LED device, comprising a stack of layers comprising a light producing layer the light producing layer not being the top or bottom layer of the stack, wherein a layer at the top or bottom of the stack is subjected to a texturization aimed at enhancing the light extraction efficiency of the LED, wherein the texturization comprises the step of producing on the top or bottom surface a plurality of surface features, the surface features being arranged according to a pattern defined by starting from a regular pattern of features and subjecting each feature of the regular pattern to a deviation from the location in the regular pattern, the deviation being in a random direction and/or having a random amplitude. According to another embodiment, a random deviation is applied to one or more dimensions of the features in the regular pattern. | 07-11-2013 |
20130176562 | METHOD AND APPARATUS FOR MEASURING CONCENTRATION OF BIOGENIC SUBSTANCE - A method for measuring a concentration of a biogenic substance in a living body includes steps of: preparing an apparatus including a light source, a substrate which has periodic metal structures and generates surface enhanced Raman scattering light by being irradiated with light from the light source, and spectroscopic means which disperses and detects the light, wherein the periodic metal structure is arranged with first and second distances in first and second direction respectively, the first distance is set to generate surface plasmon by matching a phase of the light from the light source, and the second distance is smaller than the first distance and is set between 300 nm and 350 nm; irradiating the substrate with the light from the light source to generate the surface enhanced Raman scattering; detecting the scattering with the spectroscopic means; and calculating the concentration of the biogenic substance based on the scattering. | 07-11-2013 |
20130173884 | PROGRAMMABLE DEVICE FOR SOFTWARE DEFINED RADIO TERMINAL - A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters. | 07-04-2013 |
20130166616 | System and Method for Implementing a Multiplication - The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction. | 06-27-2013 |
20130164657 | EUV Photoresist Encapsulation - A method and system are described for performing extreme ultraviolet photolithographic processing. The method comprises obtaining a substrate comprising a hard mask and a patterned layer of extreme ultraviolet (EUV) photoresist formed above the hard mask, encapsulating the patterned layer of EUV photoresist by forming an encapsulating layer being one of a silicon-oxide, silicon-nitride, silicon-oxynitride, germanium-oxide, germanium-nitride, germanium-oxynitride, silicongermanium-oxide, silicongermanium-nitride, silicongermanium-oxynitride layer on the photoresist and dry etching of the substrate for patterning the hard mask. The encapsulation layer thereby is formed at a temperature below the weakening temperature Tg of the EUV photoresist by using a first precursor being one of the group of silicon-tetrahalogenide, silicon tetrahydride, germanium-tetrahalogenide, germanium tetrahydride, silicongermanium-tetrahalogenide or silicongermanium tetrahydride precursor and an oxygen precursor. | 06-27-2013 |
20130161750 | N-Channel Laterally Diffused Metal-Oxide-Semiconductor Device - The disclosure relates to an n-channel laterally diffused metal-oxide-semiconductor device comprising an n+ source ( | 06-27-2013 |
20130161696 | TUNNEL FIELD-EFFECT TRANSISTOR AND METHODS FOR MANUFACTURING THEREOF - A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel. | 06-27-2013 |
20130161588 | Implant Free Quantum Well Transistor, Method for Making Such an Implant Free Quantum Well Transistor and Use of Such an Implant Free Quantum Well Transistor - An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region. | 06-27-2013 |
20130161583 | Stacked RRAM Array With Integrated Transistor Selector - The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack. | 06-27-2013 |
20130155572 | Metal-Insulator-Metal Stack and Method for Manufacturing the Same - A method for manufacturing a metal-insulator-metal (MIM) stack is described. The method includes forming a temporary stack by depositing a bottom electrode comprising at least one metal layer; depositing a dielectric comprising at least one layer of a dielectric material having a first dielectric constant value; and depositing a top electrode comprising at least one metal layer. The step of depositing the bottom and/or top electrode includes depositing a non-conductive metal oxide layer directly in contact with the dielectric; and after the step of depositing the bottom and/or top electrode's non-conductive metal oxide layer and the dielectric, subjecting the temporary stack to a stimulus, which transforms the non-conductive metal oxide into a thermodynamically stable oxide having conductive properties or into a metal, and the dielectric material into a crystalline form having a second dielectric constant value higher than the first dielectric constant value, thereby creating the final MIM stack. | 06-20-2013 |
20130155409 | METHOD FOR DETERMINING THE ACTIVE DOPING CONCENTRATION OF A DOPED SEMICONDUCTOR REGION - A method and system for optically determining a substantially fully activated doping profile are disclosed. The substantially fully activated doping profile is characterized by a set of physical parameters. In one aspect, the method includes obtaining a sample comprising a fully activated doping profile and a reference, and obtaining photomodulated reflectance (PMOR) offset curve measurement data and DC reflectance measurement data for the sample including the fully activated doping profile and for the reference. The method also includes determining values for the set of physical parameters of the doping profile based on both the photomodulated reflectance offset curve measurements and the DC reflectance measurements. | 06-20-2013 |
20130154112 | Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof - The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates. | 06-20-2013 |
20130153923 | ENHANCEMENT MODE III-NITRIDE DEVICE AND METHOD FOR MANUFACTURING THEREOF - Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts. | 06-20-2013 |
20130134436 | METHOD FOR BONDING SEMICONDUCTOR SUBSTRATES - A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate. | 05-30-2013 |
20130134382 | Selector Device for Memory Applications - The present disclosure is related to a selector device for memory applications. The selector device for selecting a memory element in a memory array comprises an MIT element and a decoupled heater, thermally linked to the MIT element. The MIT element comprises a MIT material component and a barrier component and is switchable from a high to a low resistance state by heating the MIT element above a transition temperature with the decoupled heater. The barrier component is provided to increase the resistance of the MIT element in the high resistance state. | 05-30-2013 |
20130130180 | Method for Producing a GaNLED Device - A method for producing a GaNLED device, wherein a stack of layers comprising at least a GaN layer is texturized, is disclosed. The method involves (i) providing a substrate comprising on its surface said stack of layers, (ii) depositing a resist layer directly on said stack, (iii) positioning a mask above said resist layer, said mask covering one or more first portions of said resist layer and not covering one or more second portions of said resist layer, (iv) exposing said second portions of said resist layer to a light source, (v) removing the mask, and (vi) bringing the resist layer in contact with a developer comprising potassium, wherein said developer removes said resist portions that have been exposed and texturizes the surface of at least the top layer of said stack by wet etching said surface, in the areas situated underneath said resist portions that have been exposed. | 05-23-2013 |
20130127552 | Ovenized System Containing Micro-Electromechanical Resonator - Disclosed an electronic device comprising an ovenized system containing a micro-electromechanical (MEM) resonator and a method for controlling such an MEM resonator. In one embodiment, the MEM resonator comprises a resonator body suspended above a substrate by means of at least a first and a second mechanical support forming a first and a second heating resistance, respectively, configured to heat the resonator body through Joules heating, biasing means configured to apply a bias voltage to the resonator body to enable vibration at a predetermined operating frequency, a temperature control system configured to control the temperature of the micro-electromechanical resonator, and an internal voltage monitoring system configured to monitor a voltage level of the resonator body. | 05-23-2013 |
20130119014 | PROTECTIVE TREATMENT FOR POROUS MATERIALS - A method for treating a surface of a porous material in an environment is provided, comprising setting the temperature of the surface to a value T | 05-16-2013 |
20130116588 | System and Method for the Analysis of Electrocardiogram Signals - A microprocessor configured to receive and process digitized signals derived from an analogue ECG signal is provided. An example microprocessor comprises a beat detection unit configured to receive the in-phase and quadrature phase band power signals, calculate a band power value and an adaptive threshold value, and compare said band power value with said adaptive threshold value to detect a QRS complex of the ECG signal indicative of a detected valid beat; and an R peak detection unit configured to receive the digital ECG signal and information about the detected valid beat, select a portion of the received ECG signal as a first time window around the detected valid beat; determine the location of a first R peak position; and perform a time domain search in a second time window around said first R peak position in order to refine the location of an R peak position. | 05-09-2013 |
20130116577 | Biomedical Acquisition System With Motion Artifact Reduction - A system for the analysis of ECG signals is disclosed. The system may comprise (i) at least one readout channel, configured to receive an analogue ECG signal acquired from at least one electrode attached to a body, and to extract an analogue measured ECG signal and analogue electrode-skin impedance signals; (ii) at least one ADC, configured to convert those extracted analogue signals at the readout channel into digital signals; (iii) a digital adaptive filter unit, configured to calculate a digital motion artifact estimate based on said digital versions of the measured ECG signal and the electrode-skin impedance signals; (iv) at least one DAC, configured to convert said digital motion artifact estimate into an analogue signal; and (v) a feedback loop for sending said analogue motion artifact estimate signal back to the readout channel configured to deduct said analogue motion artifact estimate signal from said analogue measured ECG signal. | 05-09-2013 |
20130113549 | Variable Capacitor Circuit and Method - A variable capacitor circuit is disclosed. The variable capacitor circuit includes a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which the equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal. | 05-09-2013 |
20130102140 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode. | 04-25-2013 |
20130102121 | Oxygen Diffusion Barrier Comprising Ru - A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer. | 04-25-2013 |
20130100577 | Method for Forming a MIMCAP Structure and the MIMCAP Structure Thereof - A method for forming a Metal-Insulator-Metal Capacitor (MIMCAP) structure and the MIMCAP structure thereof are described. An example electronic device includes a first electrode, and a layer of a dielectric material including titanium oxide and a first dopant ion. The layer of the dielectric material is formed on the first electrode. The first dopant ion has a size mismatch of 10% or lower compared to the Ti | 04-25-2013 |
20130093624 | Hybrid Beamforming for a Wireless Communication Device - The present disclosure relates a method for performing hybrid beamforming in a wireless communication device or any device that uses signal phase shifting for transmission and/or reception. The method comprises performing phase shifting in at least two different domains (or paths), each characterized by an operational frequency, in the communication device. More in particular, the disclosure relates in a first aspect to a method for performing at a receiver beamforming on a beam of incoming signals received via plurality of antenna paths. In another aspect, the present disclosure relates a method for performing hybrid beamforming at a transmitter device, wherein also phase shifting in at least two different domains is performed. More in particular, the disclosure also relates to a method for performing at a transmitter device beamforming on a beam of outgoing signals via a plurality of antenna paths. | 04-18-2013 |
20130084700 | Method for Selectively Depositing Noble Metals on Metal/Metal Nitride Substrates - A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber. | 04-04-2013 |
20130078155 | Method and Device for Thermal Insulation of Micro-Reactors - A micro-fluidic device is described. The micro-fluidic device includes a semiconductor substrate; at least one micro-reactor in the semiconductor substrate; one or more micro-fluidic channels in the semiconductor substrate, connected to the at least one micro-reactor; a cover layer bonded to the semiconductor substrate for sealing the one or more micro-fluidic channels; and at least one through-substrate trench surrounding the at least one micro-reactor and the one or more micro-fluidic channels. | 03-28-2013 |
20130075876 | SEALED POROUS MATERIALS, METHODS FOR MAKING THEM, AND SEMICONDUCTOR DEVICES COMPRISING THEM - A method for at least partially sealing a porous material is provided, comprising forming a sealing layer onto the porous material by applying a sealing compound comprising oligomers wherein the oligomers are formed by ageing a precursor solution comprising cyclic carbon bridged organosilica and/or bridged organosilanes. The method is especially designed for low k dielectric porous materials to be incorporated into semiconductor devices. | 03-28-2013 |
20130072808 | STRUCTURED PROBES FOR NEURAL APPLICATIONS - A probe for recording and/or stimulating brain activity includes a connecting portion and at least one shank extending from the connecting portion. The at least one shank includes a first side, a second side opposed to the first side, and a fin protruding substantially perpendicularly from the second side and running on at least a part of a length of the at least one shank. The first side includes at least one recording and/or stimulating site. | 03-21-2013 |
20130072124 | METHOD AND SYSTEM FOR ANALOG BEAMFORMING IN WIRELESS COMMUNICATION SYSTEMS - A method of analog beamforming in a wireless communication system is disclosed. The system has a plurality of transmit antennas and receive antennas. In one aspect, the method includes determining information representative of communication channels formed between a transmit antenna and a receive antenna of the plurality of antennas, defining a set of coefficients representing jointly the transmit and the receive beamforming coefficients, determining a beamforming cost function using the information and the set of coefficients, determining an optimized set of coefficients by exploiting the beamforming cost function, and separating the optimized set of coefficients into optimized transmit beamforming coefficients and optimized receive beamforming coefficients. | 03-21-2013 |
20130064005 | TUNNEL TRANSISTOR, LOGICAL GATE COMPRISING THE TRANSISTOR, STATIC RANDOM-ACCESS MEMORY USING THE LOGICAL GATE AND METHOD FOR MAKING SUCH A TUNNEL TRANSISTOR - A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part. | 03-14-2013 |
20130052815 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function. | 02-28-2013 |
20130045528 | Microneedle - The electronic device for sensing and/or actuating comprises a device surface to which an biological cell ( | 02-21-2013 |
20130036829 | OPTICAL SHEAR SENSOR AND METHOD OF PRODUCING SUCH AN OPTICAL SHEAR SENSOR - An optical shear sensor that includes a first and second outer surface at opposing sides and a sensing element is disclosed. In one aspect, the sensing element has an optoelectronic source for emitting light of a predetermined wavelength and having a source front surface where light exits the optoelectronic source, and a photodetector for detecting light of the predetermined wavelength and having a detector front surface where light of the optoelectronic source is received. The optoelectronic source is positioned along the first outer surface and emits light towards the second outer surface. A flexible sensing layer transparent to the predetermined wavelength covers the front surface of the optoelectronic source and the front surface of the photodetector. Upon application of a shear stress, the sensing layer deforms elastically and the outer surfaces are displaced along directions parallel to each other and the source front surface so the intensity of light detected by the photodetector changes. | 02-14-2013 |
20130028840 | FABRICATION OF CONDUCTING OPEN NANOSHELLS - A method involving ion milling is demonstrated to fabricate open-nanoshell suspensions and open-nanoshell monolayer structures. Ion milling technology allows the open-nanoshell geometry and upward orientation on substrates to be controlled. Substrates can be fabricated covered with stable and dense open-nanoshell monolayer structures, showing nanoaperture and nanotip geometry with upward orientation, that can be used as substrates for SERS-based biomolecule detection. | 01-31-2013 |
20130024737 | TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS - A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit. | 01-24-2013 |
20130023067 | Methods for Improving Integrated Photonic Device Uniformity - A method is described for improving the uniformity over a predetermined substrate area of a spectral response of photonic devices fabricated in a thin device layer. The method includes (i) establishing an initial device layer thickness map for the predetermined area, (ii) establishing a linewidth map for the predetermined area, and (iii) establishing an etch depth map for the predetermined area. The method further includes, based on the initial device layer thickness map, the linewidth map and the etch depth map, calculating an optimal device layer thickness map and a corresponding thickness correction map for the predetermined substrate area taking into account photonic device design data. Still further, the method includes performing a location specific corrective etch process in accordance with the thickness correction map. | 01-24-2013 |
20130022312 | Deep-Shallow Optical Radiation Filters - An optical coupler for processing radiation is described. The optical coupler comprises a first deep-shallow waveguide and a second deep-shallow waveguide for guiding radiation in a propagation direction. Each of the deep-shallow waveguides is a waveguide comprising a shallow etched portion and an unetched portion having a width substantially constant along the propagation direction. The width of the shallow etched portion is substantially larger than the width of the unetched portion. The shallow etched portion of the first deep-shallow waveguide and the shallow etched portion of the second deep-shallow waveguide are arranged sufficiently close for coupling radiation from the first deep-shallow waveguide to the second deep-shallow waveguide. | 01-24-2013 |
20130022157 | DIGITAL FRONT-END CIRCUIT AND METHOD FOR USING THE SAME - A digital front-end circuit is disclosed. In one aspect, the circuit includes a filtering block for filtering received data. The filtering block has a first filter branch for filtering the received data in a first frequency band and a second filter branch for filtering the received data in a selected second frequency band. The second filter branch is in parallel with the first filter branch, is programmable and includes a block for resampling the received data. The front-end circuit also includes a circuit for performing synchronization and spectrum sensing on the received data, which is in connection with the output of the filtering block. The front-end circuit also includes a controller block for controlling the filtering block and the synchronization circuit. | 01-24-2013 |
20130016097 | Virtual Camera System - A virtual camera system comprises a plurality of physical cameras and a hardware setup miming software to create virtual viewpoints for the virtual camera system. The position of the physical cameras is constrained, where the main constraint is the overlap between the physical cameras. The present invention provides a method for creating a virtual viewpoint of a plurality of images captured by the plurality of cameras, the images comprising current frames and previous frames. The method comprises creating background frames by combining a set of previous frames; creating a plurality of foreground masks by performing segmentation on the plurality of current frames, the segmentation comprising separating foreground objects from background objects using the created background frames; extracting the foreground objects by AND-ing the plurality of current frames with the created plurality of foreground masks; rendering the foreground objects by using a three dimensional depth-box constrained viewpoint interpolation algorithm on the plurality of current frames, the three dimensional depth box being constructed for each foreground object by exploiting information from the created foreground masks and positioning information of the foreground objects; rendering a view-dependent background image by performing homographic transformations on the created background frames; and creating the virtual viewpoint by superimposing the rendered foreground objects on the rendered background frame. | 01-17-2013 |
20130015988 | Stochastic Analog-to-Digital (A/D) Converter And Method For Using The SameAANM Verbruggen; BobAACI Kessel-LoAACO BEAAGP Verbruggen; Bob Kessel-Lo BEAANM Craninckx; JanAACI BoutersemAACO BEAAGP Craninckx; Jan Boutersem BE - An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described. The A/D converter circuit includes:
| 01-17-2013 |
20130015857 | MAGNETIC RESONANCE IMAGING OF SINGLE DOMAIN NANOPARTICLES - A method and system are disclosed for gathering information about an object including single domain particles which have a diameter in the range of about 5 to 80 nm. In one aspect, a method includes generating a static magnetic field of less than about 0.1 Tesla on the object and generating an RF energy, pulsed or continuous wave, so as to generate electron paramagnetic resonance of the single domain particles. The method also includes detecting the electron paramagnetic resonance of the single domain particles in the form of an image of the object. The single domain particles may have a predetermined diameter and a predetermined saturation magnetization and the applied magnetic field may be such that the single domain particles reach a magnetization being at least about 10% of the saturation magnetization. The method may be used for detecting tags in an object and for activating tags. | 01-17-2013 |
20130003881 | Radio Frequency Modulators - A radio frequency modulator is disclosed that includes a finite impulse response filter including a first modulator element having a first gain and configured to receive a first input signal and produce a first output signal, a second modulator element having a second gain and configured to receive a second input signal delayed with respect to the first input signal and produce a second output signal, a third modulator element having a third gain and configured to receive a third input signal delayed with respect to the second input signal and produce a third output signal, and a fourth modulator element having a fourth gain and configured to receive a fourth input signal delayed with respect to the third input signal and produce a fourth output signal. The first, second, third, and fourth gains are each different and are based on coefficients of the finite impulse response filter. | 01-03-2013 |
20130002272 | FAULT MODE CIRCUITS - A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test. | 01-03-2013 |
20130001507 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50. | 01-03-2013 |
20120327248 | INTEGRATED CIRCUIT FOR SPECTRAL IMAGING SYSTEM - An integrated circuit for an imaging system is disclosed. In one aspect, an integrated circuit has an array of optical sensors, an array of optical filters integrated with the sensors and configured to pass a band of wavelengths onto one or more of the sensors, and read out circuitry to read out pixel values from the sensors to represent an image. Different ones of the optical filters are configured to have a different thickness, to pass different bands of wavelengths by means of interference, and to allow detection of a spectrum of wavelengths. The read out circuitry can enable multiple pixels under one optical filter to be read out in parallel. The thicknesses may vary non monotonically across the array. The read out, or later image processing, may involve selection or interpolation between wavelengths, to carry out spectral sampling or shifting, to compensate for thickness errors. | 12-27-2012 |
20120326215 | METHOD FOR FABRICATION OF III-NITRIDE DEVICE AND THE III-NITRIDE DEVICE THEREOF - A III-nitride device is provided comprising a semiconductor substrate; a stack of active layers on the substrate, each layer comprising a III-nitride material; a gate, a source and a drain contact on the stack, wherein a gate, a source and a drain region of the substrate are projections of respectively the gate, the source and the drain contact in the substrate; and a trench in the substrate extending from a backside of the substrate (side opposite to the one in contact with the stack of active layers) to an underlayer of the stack of active layers in contact with the substrate, the trench completely surrounding the drain region, being positioned in between an edge of the gate region towards the drain and an edge of the drain region towards the gate and having a width such that the drain region of the substrate is substantially made of the semiconductor material. | 12-27-2012 |
20120319169 | CMOS COMPATIBLE METHOD FOR MANUFACTURING A HEMT DEVICE AND THE HEMT DEVICE THEREOF - A method for manufacturing a III-nitride HEMT having a gate electrode and source and drain ohmic contacts is provided, comprising providing a substrate; forming a stack of III-nitride layers on the substrate; forming a first passivation layer comprising silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the first passivation layer is deposited in-situ with the stack of III-nitride layers; forming a dielectric layer overlying and in contact with the first passivation layer; forming a second passivation layer comprising silicon nitride overlying and in contact with the dielectric layer wherein the second passivation layer is deposited at a temperature higher than 450° C. by LPCVD or MOCVD or any equivalent technique; and thereafter forming the source and drain ohmic contacts and the gate electrode. | 12-20-2012 |
20120315712 | Method for Detecting Embedded Voids in a Semiconductor Substrate - A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P | 12-13-2012 |
20120306058 | METHOD FOR BLISTER-FREE PASSIVATION OF A SILICON SURFACE - A method of forming a surface passivation layer on a surface of a crystalline silicon substrate is disclosed. In one aspect, the method includes depositing an Al | 12-06-2012 |
20120305542 | Oven Controlled MEMS Oscillator Device - A system is disclosed that includes an oven and a micromechanical oscillator inside the oven configured to oscillate at a predetermined frequency at a predetermined temperature, where the predetermined frequency is based on a temperature dependency and at least one predetermined property. The system further includes an excitation mechanism configured to excite the micromechanical oscillator to oscillate at the predetermined frequency and a temperature control loop configured to detect a temperature of the micromechanical oscillator using resistive sensing, determine whether the temperature of the micromechanical oscillator is within a predetermined range of the predetermined temperature based on the temperature dependency and the at least one predetermined property in order to minimize frequency drift, and adapt the temperature of the micromechanical oscillator to remain within the predetermined range. The system further includes a frequency output configured to output the predetermined frequency of the micromechanical oscillator. | 12-06-2012 |
20120298961 | CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current. | 11-29-2012 |
20120298959 | LINE-TUNNELING TUNNEL FIELD-EFFECT TRANSISTOR (TFET) AND MANUFACTURING METHOD - A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gat electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions. | 11-29-2012 |
20120298172 | METHOD FOR MANUFACTURING PHOTOVOLTAIC MODULES COMPRISING BACK-CONTACT CELLS - A method for fabricating a photovoltaic module is disclosed. In one aspect, the method includes: providing a plurality of photovoltaic substrates having a front side; attaching the plurality of photovoltaic substrates to a transparent carrier with the front side of the photovoltaic substrates facing the carrier; and rear side processing of the plurality of photovoltaic substrates for forming photovoltaic cells, wherein rear side processing includes a single metallization process for forming electrical contacts to n-type regions and to p-type regions at the rear side of the plurality of photovoltaic cells and for interconnecting the photovoltaic cells within the photovoltaic module. | 11-29-2012 |
20120295520 | Method for Sharpening Microprobe Tips - The present disclosure is related to a method for sharpening the tip of a microprobe, in particular a neural probe or an array of neuroprobes having a common base portion. | 11-22-2012 |
20120295446 | METHOD FOR SINGLE SIDE TEXTURING - A method for single side texturing of a crystalline semiconductor substrate ( | 11-22-2012 |
20120288971 | Co-Integration of Photonic Devices on a Silicon Photonics Platform - Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer. | 11-15-2012 |
20120287429 | Waveguide-Integrated Plasmonic Resonator for Integrated SERS Measurements - A resonator structure is disclosed. In some embodiments, the resonator structure may include a metal-insulator-metal waveguide comprising a first metal layer, a second metal layer, and an insulating layer between the first metal layer and the second metal layer, wherein the insulating layer comprises a resonating cavity. The resonator structure may further include a mirror formed in the resonating cavity, wherein the mirror comprises at least one nanoscale metallic reflector positioned at least partly in the insulating layer. | 11-15-2012 |
20120285010 | METHOD AND APPARATUS FOR FLUID GUIDED SELF-ASSEMBLY OF MICROCOMPONENTS - A method and apparatus is provided for self-assembly of micro-components such as microchips onto a carrier substrate, provided with assembly locations for the components. The components are supplied to the carrier by a liquid flow, while a template substrate is arranged facing the carrier. The template is a substrate provided with openings aligned to the assembly locations. The carrier and template are submerged into a tank filled with the liquid, while the liquid flow is supplied to the template side together with the components, so that the components are guided towards the openings by the flow of liquid. Once a component is trapped into an opening of the template, substantially no further liquid flow through the opening is possible, so that following components are guided towards the remaining openings, thereby establishing a fast and reliable self-assembly process. | 11-15-2012 |
20120283973 | PLASMA PROBE AND METHOD FOR PLASMA DIAGNOSTICS - Device and method for monitoring a plasma in a chamber of a plasma reactor is are disclosed. In one aspect, the method includes measuring plasma parameter data at a surface of a single planar Langmuir probe in contact with the plasma. A biasing capacitor is connected between the single planar Langmuir probe and a DC-bias source. Subsequently a discharge current of the biasing capacitor as a result of the DC-bias is measured, and a probe potential at the single probe during the discharge is measured. The measurements can be used to detect presence and/or thickness of a dielectric film on the probe surface. | 11-08-2012 |
20120280381 | Window Interposed Die Packaging - A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device. | 11-08-2012 |
20120280326 | Method for Manufacturing a Hybrid MOSFET Device and Hybrid MOSFET Obtainable Thereby - Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region. | 11-08-2012 |
20120269060 | METHOD FOR OPERATING A MULTI-MEDIA WIRELESS SYSTEM IN A MULTI-USER ENVIRONMENT - In one aspect, a method of operating a wireless system is disclosed. The method comprises allocating each video packet to a plurality of user specific priority queues. The method further comprises assigning each of the queues to a video quality layer. The method further comprises selectively dropping of one or more of video packets in cases of network congestion based on the video quality layer information. | 10-25-2012 |
20120268216 | Dual-Sensor Temperature Stabilization for Integrated Electrical Component - Method and system ( | 10-25-2012 |
20120266912 | Method and Apparatus for Cleaning Semiconductor Substrates - The present invention is related to a method and apparatus for cleaning a substrate, in particular a semiconductor substrate such as a silicon wafer. The substrate is placed in a tank containing a cleaning liquid, at an angle with respect to acoustic waves produced in said liquid. The angle corresponds to the angle of transmission, i.e. the angle at which waves are not reflected off the substrate surface. A damping material is provided in the tank, arranged to absorb substantially all waves thus transmitted through the substrate. A significant improvement in terms of cleaning efficiency is obtained by the method of the invention. | 10-25-2012 |
20120265917 | DATA TRANSFERRING DEVICE - A data transfer device for transferring data on a platform, in particular for transferring simultaneous data between different components of the platform, is disclosed. In one aspect, the data transfer device is adapted for simultaneous transfer of data between at least 3 ports of which at least one is an input port and at least one is an output port. The data transfer device has at least two controllers for executing instructions that transfer data between an input port and an output port. The controllers are adapted for receiving a synchronization instruction for synchronizing between the controllers and/or a synchronization instruction for synchronizing input ports and output ports. | 10-18-2012 |
20120258544 | Plasmonic Force Manipulation in Nanostructures | 10-11-2012 |
20120256308 | Method for Sealing a Micro-Cavity - A method for sealing a cavity is disclosed. The method includes depositing a membrane layer on top of a sacrificial layer, etching release holes into the membrane layer, and removing at least a portion of the sacrificial layer through the release holes to form a cavity. Prior to removing the sacrificial layer portion, the method includes producing a narrowing layer on the side walls of the release holes. The narrowing layer can be a sealing layer that seals off the release holes after a reflow step. Alternatively, the narrowing layer can be a layer that does not have a sealing function and is used to narrow the holes, allowing the holes to be sealed without a sealing or other material entering the cavity. The narrowing layer may be deposited by conformal deposition followed by an anisotropic etch or by direct deposition on the side walls of the release holes. | 10-11-2012 |
20120255869 | SYSTEM AND METHOD FOR ELECTROCHEMICAL PROCESSING OF NON-FLAT SAMPLES - A system and method for electrochemically processing non-flat samples and/or samples that can change shape during the electrochemical processing is disclosed. In one aspect, a system includes a sample holder for providing an electrical contact to the sample during electrochemical processing. The sample holder has a carrying element and a fixing element for clamping of the sample in between the fixing element and the carrying element, thus providing electrical contact to the sample while allowing the sample to change shape without interrupting the electrical contact. | 10-11-2012 |
20120248455 | PROCESS FOR MANUFACTURING A CRYSTALLINE SILICON LAYER - A method of forming a crystalline silicon layer on a substrate is disclosed. In one aspect, the method includes performing a metal induced crystallization process. The process includes depositing a metal (e.g. aluminum) on the substrate at a first temperature, the metal having an external surface. The method may also include oxidizing the external surface of the metal at a second temperature, and depositing amorphous silicon on the oxidized external surface of the metal at a third temperature. The method may also include annealing the metal and the silicon at a fourth temperature, whereby a crystalline silicon layer is obtained on the substrate covered by an external layer comprising the metal, and removing the external layer comprising the metal thereby exposing the crystalline silicon layer, wherein at least the first temperature and the fourth temperature (crystallization temperature) are not lower than 200° C. | 10-04-2012 |
20120248417 | DOUBLE GATE NANOSTRUCTURE FET - A Field Effect Transistor (FET) semiconductor device comprising at least one nanostructure, comprises at least a uniformly doped beam-shaped nanostructure having two major surfaces, a gate electrode provided at either major surface of the nanostructure, and an insulating layer between each of the major surfaces of the nanostructure and the gate electrodes to form a double gate nanostructure pinch-off FET. It is an advantage of such FET that pinch-off voltage and current of the FET can be independently tuned. | 10-04-2012 |
20120243645 | DIGITAL RECEIVER FOR REACTIVE RADIO - A digital receiver is disclosed. In one aspect, the receiver includes a receiving module for receiving packetized data. The receive may further include a first processing module for packet detection having a first programmable processor. The receiver may further include a second processing module for demodulation and packet decoding having a second programmable processor. The receiver may further include a first digital receive controller having a third processor arranged for being notified of detection of data by the first processing module and for activating the second processing module. | 09-27-2012 |
20120236926 | FREQUENCY-DOMAIN ADAPTIVE FEEDBACK EQUALIZER - A circuit for adaptive feedback equalization is disclosed. In one aspect, the circuit includes a frequency-domain feedforward filtering section and a feedback filtering section, a slicer to slice a block of equalized symbols, a summing module for summing outputs of the filtering sections thereby yielding the block of equalized symbols. First and second updating modules provide coefficient updates to the filtering sections. The updating modules are fed with a frequency-domain converted block of error signals indicating the difference between the block of equalized symbols at the slicer input and the block of sliced symbols at the slicer output and for computing updates using the frequency-domain converted block of error signals. A time-domain compensation module receives a time-domain version of the updated filter coefficients of the feedback filtering section and symbols of the block of sliced symbols. It adds a feedback error compensation signal to the block of equalized symbols. | 09-20-2012 |
20120228578 | Resistive Memory Element and Related Control Method - Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane. | 09-13-2012 |
20120227778 | Thermoelectric Textile - Disclosed are thermoelectric systems and methods for manufacturing thermoelectric systems. In one embodiment, a thermoelectric system include a flexible structure and at least one thermocouple unit integrated in or attached to the flexible structure, where each thermocouple unit comprises at least one thermocouple and at least one flexible radiator element thermally connected to a first end of the at least one thermocouple. In another embodiment, a method includes providing a flexible structure, forming at least one thermocouple unit comprising at least one thermocouple and at least one flexible radiator element thermally connected to a first end of the at least one thermocouple, and integrating the at least one thermocouple unit in or attaching the at least one thermocouple unit to the flexible structure. | 09-13-2012 |
20120227775 | Method and Apparatus for Controlling Optimal Operation of Acoustic Cleaning - Methods and apparatuses for cleaning a surface of a substrate are presented. The method comprises positioning a substrate at a controllable distance from a piezoelectric transducer, supplying a cleaning liquid between the substrate and the transducer, applying an oscillating acoustic force to the cleaning liquid by actuating the transducer, and moving the transducer relative to the substrate. The method further comprises, while moving the transducer relative to the substrate, measuring a value that indicates a distance between a surface of the substrate and the transducer, comparing the measured value to a desired value, and adjusting the distance between the surface and the transducer so that the measured value is maintained substantially equal to the desired value. The measured value may be the distance between the surface of the substrate and the transducer or a phase shift between an alternating current and voltage applied to the transducer. | 09-13-2012 |
20120223378 | Floating Gate Semiconductor Memory Device and Method for Producing Such a Device - Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device. | 09-06-2012 |
20120211740 | Method for Fabricating Organic Devices - The present invention relates to a method for fabricating an organic device, said method comprising: (i) Providing a substrate ( | 08-23-2012 |
20120210286 | ADDING FINE GRAIN TUNING CIRCUITRY TO INTEGRATED CIRCUIT DESIGN - A method for adding fine grain tuning circuitry to an integrated circuit design is disclosed. In one aspect, the method includes providing a design elaborated to have representations of generic logic components and interconnections between the generic logic components, automatically selecting those of the generic logic components which are in critical timing paths, and amending the design to add the fine grain tuning circuitry automatically to the selected generic logic components in the elaborated design for use in maintaining the critical timing paths during operation of the integrated circuit. By adding the circuitry at this lower level of design while it is still generic, before the synthesis stage, the additions can be made more quickly and with less disruption to the design process. | 08-16-2012 |
20120209100 | BIOCOMPATIBLE PACKAGING - A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques. | 08-16-2012 |
20120207947 | ELECTRON TRANSPORTING TITANIUM OXIDE LAYER - A method for making a solution for forming a titanium oxide sol-gel layer. Is provided. The method comprises the steps of: mixing an acid with water thereby obtaining a first mixture, mixing the first mixture with a water miscible alcohol, thereby obtaining a second mixture, mixing an amine compound, e.g., ethanolamine, to the second mixture, thereby obtaining a third mixture, waiting enough time for the third mixture to reach room temperature, e.g. from 10 to 15 minutes, and adding a titanium oxide precursor to the third mixture, thereby obtaining the solution. | 08-16-2012 |
20120199202 | METHOD FOR FABRICATING PHOTOVOLTAIC CELLS - A method for fabricating a crystalline silicon photovoltaic cell is disclosed. In one aspect, the method includes a) providing a crystalline silicon substrate of a first dopant type, b) performing an implantation, thereby introducing dopants of a second type opposite to the first type at a front side of the crystalline silicon substrate, c) after the implantation, depositing a hydrogen containing layer on the front surface of the substrate, and d) after depositing the hydrogen containing layer, performing a thermal treatment, thereby electrically activating the dopant of the second type. | 08-09-2012 |
20120192943 | FABRICATION METHOD FOR LOCAL BACK CONTACT PHOTOVOLTAIC CELLS - A method is disclosed for fabricating a photovoltaic cell comprising local back contacts. In one aspect, the method includes providing a silicon substrate, depositing a surface passivation layer at a rear side of the silicon substrate, forming delaminated regions or bubbles at an interface between the surface passivation layer and the silicon substrate, depositing a metal layer on the surface passivation layer, and performing a metal firing. | 08-02-2012 |
20120188023 | Optimal Leg Design for MEMS Resonator - A microelectromechanical (MEMS) resonator is disclosed that comprises a substrate and a resonator body suspended above the substrate by means of clamped-clamped beams, where each beam comprises two support legs with a common connection to the resonator body, and the resonator body is configured to resonate at an operating frequency. The MEMS resonator further comprises an excitation component configured to excite the resonator body to resonate at the operating frequency, where each beam is further configured to oscillate in a flexural mode at a flexural wavelength as a result of resonating at the operating frequency, and each leg is acoustically long with respect to the flexural wavelength. | 07-26-2012 |
20120184088 | Method for Selective Deposition of a Semiconductor Material - A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl | 07-19-2012 |
20120175741 | Method for Direct Deposition of a Germanium Layer - The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH | 07-12-2012 |
20120171836 | Method for Forming MEMS Variable Capacitors - A method for fabricating an out-of-plane variable overlap MEMS capacitor comprises: providing a substrate ( | 07-05-2012 |
20120170034 | SPECTROSCOPY USING NANOPORE CAVITIES - A system for assisting in spectrally characterizing or detecting a sample using radiation at a predetermined wavelength or in a predetermined wavelength range is disclosed. In one aspect, the system includes a substrate having a nanopore for excitation of plasmons. The nanopore provides a window through the substrate, wherein a smallest window opening of the window has an average length (L) and an average width (W) both being substantially smaller than 2 μm. The nanopore supports highly confined surface plasmon polaritons and at specific wavelengths resonances are observed, when the conditions for a standing wave are fulfilled. This leads to strong field enhancements and enables single molecule spectroscopy. | 07-05-2012 |
20120160031 | OPTICAL TACTILE SENSORS - A sensor for sensing pressure is disclosed. The sensor may be a pressure sensor for sensing pressure, or a tactile sensor for sensing tactile events through pressure measurement. In one aspect, the sensor includes at least one pressure sensor having at least one VCSEL on a substrate. It further includes a compressible sensor layer covering a top surface of the at least one VCSEL, and a reflecting element covering a top surface of the sensor layer. A method of manufacturing such a sensor is also disclosed. | 06-28-2012 |
20120156453 | CRACK REDUCTION AT METAL/ORGANIC DIELECTRIC INTERFACE - A method of providing a metal interconnect to second structures embedded in organic dielectric material is disclosed. In one aspect, the method includes obtaining a first structure with second structures, e.g., metal pillars, embedded in organic dielectric material. The method further includes, at least at some locations of the first structure, providing a stiffening layer on top of the organic dielectric material, the stiffening layer having a stiffness higher than the stiffness of the organic dielectric material. The method provides an interconnect structure free from cracks at the interface between the second structures and the organic dielectric material. | 06-21-2012 |
20120139127 | METHOD FOR FORMING ISOLATION TRENCHES - A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided. | 06-07-2012 |
20120138928 | Method of Manufacturing Low Resistivity Contacts on n-Type Germanium - Disclosed are methods for manufacturing semiconductor devices and the devices thus obtained. In one embodiment, the method comprises obtaining a semiconductor substrate comprising a germanium region doped with n-type dopants at a first doping level and forming an interfacial silicon layer overlying the germanium region, where the interfacial silicon layer is doped with n-type dopants at a second doping level and has a thickness higher than a critical thickness of silicon on germanium, such that the interfacial layer is at least partially relaxed. The method further includes forming over the interfacial silicon layer a layer of material having an electrical resistivity smaller than 1×10 | 06-07-2012 |
20120133535 | Interleaved Pipelined Binary Search A/D Converter - The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed. | 05-31-2012 |
20120132529 | METHOD FOR PRECISELY CONTROLLED MASKED ANODIZATION - The present invention is related to a method for masked anodization of an anodizable layer on a substrate, for example an aluminum layer present on a sacrificial layer, wherein the sacrificial layer needs to be removed from a cavity comprising a Micro or Nano Electromechanical System (MEMS or NEMS). Anodization of an Al layer leads to the formation of elongate pores, through which the sacrificial layer can be removed. According to the method of the invention, the anodization of the Al layer is done with the help of a first mask which defines the area to be anodized, and a second mask which defines a second area to be anodized, said second area surrounding the first area. Anodization of the areas defined by the first and second mask leads to the formation of an anodized structure in the form of a closed ring around the first area, which forms a barrier against unwanted lateral anodization in the first area. | 05-31-2012 |
20120129296 | METHOD FOR FORMING AN ORGANIC MATERIAL LAYER ON A SUBSTRATE - A method for forming an organic material layer on a substrate in an in-line deposition system is disclosed. In one aspect, the organic material is deposited with a predetermined non-constant deposition rate profile, which includes a first predetermined deposition rate range provided to deposit at least a first monolayer of the organic material layer with a first predetermined average deposition rate and a second predetermined deposition rate range provided to deposit at least a second monolayer of the organic material layer with a second predetermined average deposition rate. The injection of organic material through the openings of the injector is controlled for realizing the predetermined deposition rate profile. | 05-24-2012 |
20120127559 | HOLOGRAPHIC VISUALIZATION SYSTEM COMPRISING A HIGH DATA REFRESH RATE DND DRIVER ARRAY - A DND chip is disclosed. In one aspect, the chip includes a 2D DND array of DND elements logically arranged in rows and columns, and a DND driver architecture for actuating the DND elements. The DND driver has a set of first drive lines along the rows and a set of second drive lines along the columns, a set of first line drivers for each biasing one line from the set of first drive lines and a set of second line drivers for each biasing a line from the set of second drive lines. A plurality of second line drivers are spatially grouped together to serve a block of DND elements, and that plurality of second line drivers are spatially covered substantially completely by at least some DND elements of the block of DND elements. A holographic visualization system including the DND chip is provided. | 05-24-2012 |