STMICROELECTRONICS Pvt. Ltd. Patent applications |
Patent application number | Title | Published |
20140340133 | RADIATION HARDENED CIRCUIT - A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal. | 11-20-2014 |
20140184912 | Video window detection - A video window detector includes a region characteristic determiner to generate at least one characteristic value for at least one region of a display output; a characteristic map generator to generate an image map from the at least one characteristic value for at least one region of the display output; and a window detector to detect at least one video window dependent on the image map. | 07-03-2014 |
20140036564 | NON-VOLATILE MEMORY DEVICE WITH CLUSTERED MEMORY CELLS - An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row. | 02-06-2014 |
20140015577 | PHASE LOCKED LOOP CIRCUIT WITH REDUCED JITTER - A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various electronic components may cause unwanted jitter is a PLL. The size of various components in the filter are typically set to specific sizes to realize a transfer function suited for loop stability and reduction in phase jitter. In one embodiment, the jitter due to thermal noise in the resistor may be reduced by reducing the size of the gain affecting the signal through this resistor. By adjusting the size of the resistor by a scaling factor as well as other components in the PLL, one may then control a voltage controlled oscillator (VCO) using two or more control signals through the LPF. | 01-16-2014 |
20140013177 | ON-CHIP FUNCTIONAL DEBUGGER AND A METHOD OF PROVIDING ON-CHIP FUNCTIONAL DEBUGGING - An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node. | 01-09-2014 |
20140009633 | CONFIGURABLE LANE ARCHITECTURE IN SOURCE SYNCHRONOUS SYSTEMS - A system and method for utilizing multiple configurable lanes for clock and data transfer in source synchronous systems that may utilize a clock signal from another source for interpreting data received from the source. In an embodiment, a system may include a transmitter configured to transmit at least one clock signal and at least one data signal to a receiver device. The receiver device may have at least one clock lane and at least one data lane for receiving signals from the transmitter device. The clock lane(s) and data lane(s) can be arranged in any order as per requirement of system design. In the receiver, after manufacture, each data lane may be configured to be clocked by any clock lane. | 01-09-2014 |
20130308399 | WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY - A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell. | 11-21-2013 |
20130308397 | READ SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY - A self-timed memory includes a plurality of timer cells each including an access transistor coupled to a true node and having a gate coupled to a reference wordline actuated by a reference wordline driver. Self-timing is effectuated by detecting completion of reference true bitline discharge in the timer cells resulting in enabling a sense amplifier. To better align detected completion of the discharge by the timer cells to a read from actual memory cells at any voltage in the operating voltage range of the memory, the gate to source voltage of the timer cells' access transistors is lowered by decreasing the logic high voltage level applied by the reference wordline. The timer cells may also, or alternatively, have pulldown transistors coupled to the internal true node, wherein a gate terminal of the pulldown is coupled to the reference wordline node and activated with the lowered gate to source voltage. | 11-21-2013 |
20130205587 | AREA-EFFICIENT DISTRIBUTED DEVICE STRUCTURE FOR INTEGRATED VOLTAGE REGULATORS - An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization. | 08-15-2013 |
20130202031 | GOP-INDEPENDENT DYNAMIC BIT-RATE CONTROLLER - A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module. | 08-08-2013 |
20130181754 | HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY - In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period. | 07-18-2013 |
20130170306 | MEMORY ARCHITECTURE AND DESIGN METHODOLOGY WITH ADAPTIVE READ - An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal. | 07-04-2013 |
20130170289 | LOW VOLTAGE WRITE TIME ENHANCED SRAM CELL AND CIRCUIT EXTENSIONS - A memory cell is formed by storage latch coupled between a true bit line node and a complement bit line node. The latch has an internal true node and an internal complement node. The cell additionally includes a first transistor that is source-drain coupled between the internal true node and a word line node. A control terminal of the first transistor is coupled to receive a signal from the complement bit line node and functions to source current into the true node during write mode. The cell further includes a second transistor that is source-drain coupled between the internal complement node and the word line node. A control terminal of the second transistor is coupled to receive a signal from the true bit line node and functions to source current into the complement node during write mode. | 07-04-2013 |
20130170288 | DUAL PORT REGISTER FILE MEMORY CELL WITH REDUCED SUSCEPTIBILITY TO NOISE DURING SAME ROW ACCESS - A memory cell is formed by storage latch having a true node and a complement node. The cell includes a write port operable in response to a write signal on a write word line to write data from write bit lines into the latch, and a separate read port operable in response to a read signal on a read word line to read data from the latch to a read bit line. The circuitry of the memory cell is configured to address voltage bounce at the complement node during reading of the memory (where the voltage bounce arises from a simultaneous write to another memory cell in a same row). | 07-04-2013 |
20130170275 | DUAL PORT SRAM HAVING REDUCED CELL SIZE AND RECTANGULAR SHAPE - A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell. | 07-04-2013 |
20130170081 | TRIGGER CIRCUIT AND METHOD OF USING SAME - A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state. | 07-04-2013 |
20130169360 | APPARATUS - According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node. | 07-04-2013 |
20130166851 | INCOMING BUS TRAFFIC STORAGE SYSTEM - In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM. | 06-27-2013 |
20130142003 | DUAL CLOCK EDGE TRIGGERED MEMORY - A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock. | 06-06-2013 |
20130141263 | CALIBRATION METHOD AND CIRCUIT - An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values. | 06-06-2013 |
20130141140 | STRESS REDUCED CASCODED CMOS OUTPUT DRIVER CIRCUIT - An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors. | 06-06-2013 |
20130135914 | XY TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) CELL AND ARRAY - A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell. | 05-30-2013 |
20130128656 | SRAM MEMORY DEVICE AND TESTING METHOD THEREOF - A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item. | 05-23-2013 |
20130127646 | MULTIPLYING DIGITAL-TO-ANALOG CONVERTER (DAC) - An embodiment of a multiplying digital-to-analog converter (MDAC), an embodiment of a method for converting a digital signal to an analog signal, an embodiment of a pipelined analog-to-digital converter (ADC), and a method of converting an analog signal to a digital signal in a plurality of cascading stages. | 05-23-2013 |
20130127514 | LEVEL TRANSLATOR - A circuit has an input configured to receive a periodic signal having a first value. First circuitry is provided to generate a pulse when said periodic signal has a rising edge and a pulse when said periodic signal has a falling edge. Second circuitry is configured to receive said pulses and responsive thereto to provide an output signal, said output signal having a same duty cycle as said input signal and having a second value. | 05-23-2013 |
20130124121 | BATTERY PACK MANAGEMENT - A battery pack management system provides information such as remaining capacity and/or run time to empty for a battery. A time taken for a battery voltage to drop a threshold amount is measured and used to determine a remaining capacity of the battery. The time may be associated with a temperature and current of the battery. The remaining capacity of a battery is calculated by monitoring a discharge of the battery. For example, current drawn from the battery is monitored over a period of time and an initial amount by which the battery has been discharged is calculated. Compensation of this initial amount is carried out in order to take into account factors such as temperature, self-discharge rate and age of the battery. | 05-16-2013 |
20130120650 | ADAPTIVE PAL FIELD COMBER - A video decoder includes an adaptive comber to generate a combed video image, and the adaptive comber selectively combs using 2D combing, frame combing, and field combing. | 05-16-2013 |
20130120588 | VIDEO WINDOW DETECTION - A video window detector includes a region characteristic determiner to generate at least one characteristic value for at least one region of a display output; a characteristic map generator to generate an image map from the at least one characteristic value for at least one region of the display output; and a window detector to detect at least one video window dependent on the image map. | 05-16-2013 |
20130083247 | VIDEO DECODER - A video decoder that separates and analyzes analog video signals includes a hue and saturation separator and a video signal determiner. The hue and saturation separator demodulates from a component video signal chroma signal, which includes a hue signal and a saturation signal. The video signal determiner determines at least one video signal characteristic of the component video signal dependent on the hue and saturation signal. The video signal determiner may include a mode determiner that determines the encoding standard of the video signal, and a color burst determiner that determines a location of a color burst signal with the video signal. The mode determiner may include a signal lock detector, a sequence matcher, and an encoding mode selector. The color burst determiner may include an absolute value determiner and a burst position determiner. | 04-04-2013 |
20130083245 | COMPRESSION ERROR HANDLING FOR TEMPORAL NOISE REDUCTION - A video processor includes a spatio-temporal noise reduction controller to determine current and previous image edge slopes and adaptively control a spatio-temporal noise reduction processor to blend current and previous images dependent on the current and previous image edge slope values. | 04-04-2013 |
20130082778 | DIFFERENTIAL AMPLIFIER - In an embodiment are provided are a differential amplifier, a method of amplifying a differential input signal, a device including a differential amplifier, and a low voltage differential signaling receiver. | 04-04-2013 |
20130058155 | SRAM DIMENSIONED TO PROVIDE BETA RATIO SUPPORTING READ STABILITY AND REDUCED WRITE TIME - A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the access transistor gate width multiplied by a ratio of the access transistor gate length to the pulldown transistor gate length is smaller than one. Furthermore, the pullup transistor gate width is greater than or equal to the pulldown transistor gate width. | 03-07-2013 |
20130033289 | INPUT AND OUTPUT BUFFER INCLUDING A DYNAMIC DRIVER REFERENCE GENERATOR - A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad. | 02-07-2013 |
20130021077 | AUTOMATIC CLOCK-ACTIVITY BASED CHIP/IO RING DESIGN - A NOVEL ARCHITECTURE TO REDUCE STANDBY CONSUMPTION - A circuit including an input configured to receive a clock signal. Detection circuitry may be configured to detect if the clock signal is present on the input. An output is configured to provide a control signal having a first level if the clock signal is present on the input and a second level if the clock signal is absent from the input. | 01-24-2013 |
20130007548 | AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING - An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode. | 01-03-2013 |
20130003905 | TRANSITION DETECTOR - An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window. | 01-03-2013 |
20130003882 | PRE-EMPHASIS CIRCUIT - An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system. | 01-03-2013 |
20130003442 | CANARY BASED SRAM ADAPTIVE VOLTAGE SCALING (AVS) ARCHITECTURE AND CANARY CELLS FOR THE SAME - A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank. | 01-03-2013 |
20130002213 | VOLTAGE REGULATOR STRUCTURE - A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor. | 01-03-2013 |
20120326517 | SYSTEM AND METHOD FOR SWITCHING BETWEEN A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY VOLTAGE OF A LOAD - A system switches between application of a first supply voltage and a second supply voltage to a load. The second supply voltage is a regulated voltage that is generated from the first supply voltage, or is alternatively generated from a reference voltage, such as bandgap. When the load is supplied from the first supply voltage, the regulated voltage is also generated from the first supply voltage. At or after switching the load to the second supply voltage, the regulated voltage is generated instead from the reference voltage. The load is a clock circuit, such as an oscillator. The controlled switching of the supply voltage for the load in the manner described addresses concerns over introducing errors in the output clock signal when the clock circuit's supply voltage is changed. | 12-27-2012 |
20120304000 | RESTORING STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded. | 11-29-2012 |
20120223735 | DETECTION OF SINGLE BIT UPSET AT DYNAMIC LOGIC DUE TO SOFT ERROR IN REAL TIME - A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground. | 09-06-2012 |
20120218002 | SYSTEM AND METHOD FOR ON-CHIP JITTER AND DUTY CYCLE MEASUREMENT - An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval. | 08-30-2012 |
20120198291 | LOCALLY SYNCHRONOUS SHARED BIST ARCHITECTURE FOR TESTING EMBEDDED MEMORIES WITH ASYNCHRONOUS INTERFACES - A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface. | 08-02-2012 |
20120182060 | NEGATIVE VOLTAGE LEVEL SHIFTER CIRCUIT - A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits. | 07-19-2012 |
20120177121 | ADVANCE VIDEO CODING WITH PERCEPTUAL QUALITY SCALABILITY FOR REGIONS OF INTEREST - A video compression framework based on parametric object and background compression is proposed. At the encoder, an object is detected and frames are segmented into regions corresponding to the foreground object and the background. The encoder generates object motion and appearance parameters. The motion or warping parameters may include at least two parameters for object translation; two parameters for object scaling in two primary axes and one object orientation parameter indicating a rotation of the object. Particle filtering may be employed to generate the object motion parameters. The proposed methodology is the formalization of the concept and usability for perceptual quality scalability layer for Region(s) of Interest. A coded video sequence format is proposed which aims at “network friendly” video representation supporting appearance and generalized motion of object(s). | 07-12-2012 |
20120176173 | ADAPTIVE MULTI-STAGE SLACK BORROWING FOR HIGH PERFORMANCE ERROR RESILIENT COMPUTING - Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput. | 07-12-2012 |
20120174052 | ROUTING - A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation; de-routing the determined net-routing and re-routing the determined net-routing dependent on at least the routing blockage. | 07-05-2012 |
20120170659 | ADVANCE VIDEO CODING WITH PERCEPTUAL QUALITY SCALABILITY FOR REGIONS OF INTEREST - A video compression framework based on parametric object and background compression is proposed. At the encoder, an object is detected and frames are segmented into regions corresponding to the foreground object and the background. The encoder generates object motion and appearance parameters. The motion or warping parameters may include at least two parameters for object translation; two parameters for object scaling in two primary axes and one object orientation parameter indicating a rotation of the object. Particle filtering may be employed to generate the object motion parameters. The proposed methodology is the formalization of the concept and usability for perceptual quality scalability layer for Region(s) of Interest. A coded video sequence format is proposed which aims at “network friendly” video representation supporting appearance and generalized motion of object(s). | 07-05-2012 |
20120170587 | GENERIC BUS DE-MULTIPLEXER/PORT EXPANDER WITH INHERENT BUS SIGNALS AS SELECTORS - A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal. | 07-05-2012 |
20120170391 | MEMORY DEVICE WITH BOOST COMPENSATION - A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit. | 07-05-2012 |
20120169438 | HDMI RECEIVER - An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another. | 07-05-2012 |
20120169410 | TECHNIQUE TO MINIMIZE VDS MISMATCH DRIVEN VOLTAGE SWING VARIATION IN OPEN DRAIN TRANSMITTER - A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage. | 07-05-2012 |
20120169403 | POWER HARVESTING IN OPEN DRAIN TRANSMITTERS - A transmitter having at least one channel comprising a first differential circuit driven by a differential data signal, the first differential circuit configured to output the differential data at a first and second output and a first control circuit coupled between the first differential circuit and the first and second output, the first control circuit driven by a drive voltage. | 07-05-2012 |
20120169393 | PROCESSING CLOCK SIGNALS - A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal. | 07-05-2012 |
20120169378 | DIFFERENTIAL DATA SENSING - A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line. | 07-05-2012 |
20120168934 | FLIP CHIP DEVICE HAVING SIMPLIFIED ROUTING - The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads. | 07-05-2012 |
20120166900 | TESTING CIRCUITS - A first circuit has a reset input. A second circuit is configured to be reset and provide an output. A test circuit is configured to test the first circuit and second circuit. The test circuit is configured such that a fault with the first circuit and said second circuit is determined in dependence on an output of the first circuit. | 06-28-2012 |
20120166860 | SEQUENTIAL ON-CHIP CLOCK CONTROLLER WITH DYNAMIC BYPASS FOR MULTI-CLOCK DOMAIN TESTING - A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output. | 06-28-2012 |
20120166856 | SIGNAL SYNCHRONIZING SYSTEMS AND METHODS - Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. | 06-28-2012 |
20120166131 | INTEGRATED DEVICE TEST CIRCUITS AND METHODS - Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults. | 06-28-2012 |
20120163110 | MEMORY DEVICE WITH ROBUST WRITE ASSIST - A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal. | 06-28-2012 |
20120163064 | MEMORY DEVICE - A read only memory cell circuit is provided. The memory cell circuit includes at least one memory cell. A pair of bit lines associated with each memory cell is provided which form a complementary output. The at least one memory cell is configured to be coupled to first or second of the bit line pair. | 06-28-2012 |
20120163063 | COMPLEMENTARY READ-ONLY MEMORY (ROM) CELL AND METHOD FOR MANUFACTURING THE SAME - A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell. | 06-28-2012 |
20120161888 | CRYSTAL OSCILLATOR CIRCUIT - An embodiment of a crystal oscillator circuit includes leakage-current compensation, transconductance enhancement, or both leakage-current compensation and transconductance enhancement. Such an oscillator circuit may draw a reduced operating current relative to a conventional oscillator circuit, and thus may be suitable for battery or other low-power applications. | 06-28-2012 |
20120161883 | COUPLED RING OSCILLATOR - A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator. | 06-28-2012 |
20120161848 | AREA EFFICIENT EMI REDUCTION TECHNIQUE FOR H-BRIDGE CURRENT MODE TRANSMITTER - The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals. | 06-28-2012 |
20120161823 | FREQUENCY DIVISION OF AN INPUT CLOCK SIGNAL - Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop. In a first mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop so that each first type of edge causes the signal provided to the data input of the flip flop to toggle such that the output of the flip flop has a frequency which is substantially half of the frequency of the input clock signal, and wherein in a second mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop with the exception that toggling of the signal provided to the data input of the flip flop is selectively prevented despite toggling of the output of the flip flop on an edge of the first type such that the output of the flip flop has a frequency which is at most a third of the frequency of the input clock signal. The feedback circuitry is arranged to operate independently from a second type of edge of the input clock signal in providing the signal to the data input of the flip flop, such that the output of the flip flop is independent from the duty cycle of the input clock signal. | 06-28-2012 |
20120158339 | CALIBRATION ARRANGEMENT - An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information. | 06-21-2012 |
20120140582 | WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURES - A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry. | 06-07-2012 |
20120139771 | DIFFERENTIAL SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase. | 06-07-2012 |
20120137188 | METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS - A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode. | 05-31-2012 |
20120102538 | METHODS AND APPARATUS FOR DECODING MULTIPLE INDEPENDENT AUDIO STREAMS USING A SINGLE AUDIO DECODER - An embodiment of the present invention discloses a system and method for decoding multiple independent encoded audio streams using a single decoder. The system includes one or more parsers, a preprocessor, an audio decoder, and a renderer. The parser extracts individual audio frames from each input audio stream. The preprocessor combines the outputs of all parsers into a single audio frame stream and enables sharing of the audio decoder among multiple independent encoded audio streams. The audio decoder decodes the single audio frame stream and provides a single decoded audio stream. And the renderer renders the individual reconstructed audio streams from the single decoded audio stream. | 04-26-2012 |
20120099832 | PORTABLE VIDEO PLAYER - A portable video player includes: a data input coupled to a memory module to store at least one video file, a video decoder coupled to the memory module via a memory interface to decode the video file, and a video interface connector to output to a display the decoded video file. | 04-26-2012 |
20120086469 | REDUCTION OF SIGNAL SKEW - Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced. | 04-12-2012 |
20120062268 | METHOD AND DEVICE FOR MEASURING THE RELIABILITY OF AN INTEGRATED CIRCUIT - Electromigration may cause a fault to appear in an integrated circuit located on a semiconductor chip. To detect such a fault, at least one resistive test structure is provided separated from the integrated circuit and located on at least one metallization level of the integrated circuit. During operation of the integrated circuit, the resistive test structure is sensed. Detection of a voltage difference between two points of the resistive test structure is indicative of a fault. | 03-15-2012 |
20120060058 | TESTING OF NON STUCK-AT FAULTS IN MEMORY - A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell. | 03-08-2012 |
20120044226 | IMAGE PROCESSING ARRANGEMENT - An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic. | 02-23-2012 |
20120044005 | FAIL SAFE ADAPTIVE VOLTAGE/FREQUENCY SYSTEM - A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation. | 02-23-2012 |
20120017130 | CIRCUIT FOR TESTING INTEGRATED CIRCUITS - An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode. | 01-19-2012 |
20120013386 | LEVEL SHIFTER - A level shifter includes an output stage transistor and a level controller. The level controller receives a selection signal and provides a reference voltage at a gate terminal of the output stage transistor based on the selection signal. The output stage transistor, on being enabled by the reference voltage, provides a first level shifted output based on a first output reference voltage. | 01-19-2012 |
20110316587 | Bistable CML Circuit - A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch. | 12-29-2011 |
20110310958 | SYSTEM FOR ENTROPY DECODING OF H.264 VIDEO FOR REAL TIME HDTV APPLICATIONS - An embodiment relates to a decoder for decoding CABAC encoded video data in real time for HDTV applications. The decoder comprises a binary arithmetic decoder block for converting an input bit stream into a bin string, a context memory for storing a plurality of context values, and a plurality of finite state machines. Each of the finite state machines is adapted for decoding a particular one of the H.264 syntax elements by providing the binary arithmetic decoder block with an index of the relevant context value within the context memory and by converting the resulting bin stream into a value of the current syntax element. In this manner, a performance of one bin per cycle may be achieved. | 12-22-2011 |
20110299355 | WORD LINE DRIVER FOR MEMORY - A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line. | 12-08-2011 |
20110291642 | POWER MEASUREMENT CIRCUIT - A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device. | 12-01-2011 |
20110289266 | GARBAGE COLLECTION IN STORAGE DEVICES BASED ON FLASH MEMORIES - A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space. | 11-24-2011 |
20110279292 | GLITCH FREE DYNAMIC ELEMENT MATCHING SCHEME - A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2 | 11-17-2011 |
20110273922 | SENSE AMPLIFIER USING REFERENCE SIGNAL THROUGH STANDARD MOS AND DRAM CAPACITOR - A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor. | 11-10-2011 |
20110273215 | HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY - In a method for recovery of a clock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted clock signals are generated from a receiver's clock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period. | 11-10-2011 |
20110271156 | APPARATUS AND METHOD FOR TESTING SHADOW LOGIC - A system for testing faults in shadow logic includes a sequential block coupled to a shadow logic block and a delaying block to receive test patterns for testing the shadow logic block. The delaying block delays the test patterns by an access time of the sequential block to generate delayed test patterns. The delayed test patterns are passed to the shadow logic block for testing faults. | 11-03-2011 |
20110267125 | MULTI-THRESHOLD COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR MASTER SLAVE FLIP-FLOP - A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) master slave flip-flop with a single clock signal includes a master storage element configured to store an input data in response to a clock signal transition and a slave storage element configured to receive data from the master storage element and to output the received data in response to an opposite clock signal transition. The master storage element includes low threshold voltage transistors, the slave storage element includes high threshold voltage transistors, and the master and the slave storage elements are provided with a single clock signal. | 11-03-2011 |
20110264971 | TESTING OF MULTI-CLOCK DOMAINS - A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains. | 10-27-2011 |
20110221620 | CURRENT STEERING DAC WITH SWITCHED CASCODE OUTPUT CURRENT SOURCE/SINK - A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element. | 09-15-2011 |
20110202782 | ARCHITECTURE INCORPORATING CONFIGURABLE CONTROLLER FOR REDUCING ON CHIP POWER LEAKAGE - The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power. | 08-18-2011 |
20110176653 | LOW CONSUMPTION FLIP-FLOP CIRCUIT WITH DATA RETENTION AND METHOD THEREOF - The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated. | 07-21-2011 |
20110167629 | AREA-EFFICIENT DISTRIBUTED DEVICE STRUCTURE FOR INTEGRATED VOLTAGE REGULATORS - An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization. | 07-14-2011 |
20110153934 | MEMORY CARD AND COMMUNICATION METHOD BETWEEN A MEMORY CARD AND A HOST UNIT - A memory card and a communication method between a memory card and a host unit are disclosed. High throughput of data between the memory card and the host unit is guaranteed by providing a communication interface between the memory card and the host unit including a first communication interface between a memory unit of the memory card and a control unit of the memory card and a second communication interface between the control unit of the memory card and the host unit. | 06-23-2011 |
20110150351 | PARALLELIZATION OF VARIABLE LENGTH DECODING - Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel. | 06-23-2011 |
20110149668 | MEMORY DEVICE AND METHOD OF OPERATION THEREOF - Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell. | 06-23-2011 |
20110149662 | MEMORY DEVICE AND METHOD OF WRITING DATA TO A MEMORY DEVICE - A memory device includes bitlines, wordlines and a matrix of memory cells arranged in rows and columns. Each of the bitlines is electrically connected to memory cells in one of the columns. Each of the wordlines is electrically connected to memory cells in one of the rows. A bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline. | 06-23-2011 |
20110145644 | PROTOCOL SEQUENCE GENERATOR - A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells. | 06-16-2011 |
20110142254 | NOISE REMOVAL SYSTEM - A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal. | 06-16-2011 |
20110142155 | QUADRATURE SIGNAL DECODING USING A DRIVER - A system and method for decoding quadrature signals includes a quadrature signal generator, a quadrature signal decoder, a key matrix and a driver. The quadrature signal generator generates quadrature signals on rotation. The quadrature signal decoder is configured to convert the quadrature signals into non-overlapping signals. The key matrix is configured to receive the non-overlapping signals. The driver is configured to scan the key matrix to decode the non-overlapping signals to generate an event update corresponding to a direction of rotation of the quadrature signal generator. | 06-16-2011 |
20110142125 | GOP-INDEPENDENT DYNAMIC BIT-RATE CONTROLLER - A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module. | 06-16-2011 |
20110140789 | ON-THE-FLY FREQUENCY SWITCHING WHILE MAINTAINING PHASE AND FREQUENCY LOCK - A difference between a reference clock and feedback clock is detected to generate a difference signal that is filtered to generate a voltage controlled oscillator control signal and produce an oscillation signal having an oscillation frequency. A first frequency dividing circuit divides the oscillation signal by a selected one of a number of first frequency divisors to generate an output signal at a selected frequency. A second frequency dividing circuit divides the output signal by a selected one of a number of second frequency divisors to generate the feedback clock. The frequency divisors are selected by a frequency selection signal. The first frequency dividing circuit samples the frequency selection signal at the rate of the oscillation signal divided by a least common multiple of the plurality of first frequency divisors. The second frequency dividing circuit samples the sampled frequency selection signal at the rate of the feedback clock. | 06-16-2011 |
20110140748 | SYNTHESIZABLE DLL ON SYSTEM-ON-CHIP - The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time. | 06-16-2011 |
20110140739 | FREQUENCY MODULATED SIGNAL DECODING USING A DRIVER - A system for decoding frequency modulated signals includes a glue logic module, a key matrix, and a driver coupled to the key matrix. The glue logic module provides a pre-scaled frequency signal, while the key matrix receives the pre-scaled frequency signal. The driver decodes the pre-scaled frequency signal to generate at least one event update corresponding to a frequency of the pre-scaled frequency signal. | 06-16-2011 |
20110122944 | PARALLEL DECODING FOR SCALABLE VIDEO CODING - A method for decoding a stream encoded using a scalable video coding and including a plurality of layers of frames divided into a plurality of blocks, decodes block-wise in parallel the layers of the stream. A target block in an enhancement layer is decoded as soon as the block data required for its decoding are available from the reference layer. | 05-26-2011 |
20110115561 | OUTPUT COMMON MODE VOLTAGE STABILIZER OVER LARGE COMMON MODE INPUT RANGE IN A HIGH SPEED DIFFERENTIAL AMPLIFIER - A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage. | 05-19-2011 |
20110113171 | ACKNOWLEDGEMENT MANAGEMENT TECHNIQUE FOR SUPPORTED COMMAND SET OF SMBUS/PMBUS SLAVE APPLICATIONS - A slave device has an input/output adapted for connection to a serial data line of an I | 05-12-2011 |
20110102062 | MULTI-SUPPLY VOLTAGE COMPATIBLE I/O RING - Systems and methods for achieving multiple supply voltage compatibility of an input/output (I/O) ring of an integrated circuit (IC) chip. The IC chip includes a core surrounded by the I/O ring which includes a voltage detector circuit. An I/O supply voltage of the IC chip is sensed by the voltage detector circuit to generate a control signal. The control signal is used to configure the I/O ring to operate at the I/O supply voltage of the I/O ring, thus enabling the IC to operate at multiple supply voltage levels. | 05-05-2011 |
20110090002 | HIGH VOLTAGE TOLERANCE OF EXTERNAL PAD CONNECTED MOS IN POWER-OFF MODE - An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads. | 04-21-2011 |
20110087832 | WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 04-14-2011 |
20110068858 | FAIL SAFE ADAPTIVE VOLTAGE/FREQUENCY SYSTEM - A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation. | 03-24-2011 |
20110062983 | REDUCING SWITCHING NOISE - Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a way that switching occurs at or above a bit rate of transmission, such that at least one switch changes state at least for every bit. Operating the circuit in such a way leads to a switching rate that is above a resonant frequency of the circuit and prevents large oscillations and noise from being inserted into the signal and causing communication problems. | 03-17-2011 |
20110058609 | SYSTEM AND METHOD FOR OBJECT BASED PARAMETRIC VIDEO CODING - A video compression framework based on parametric object and background compression is proposed. At the encoder, an embodiment detects objects and segments frames into regions corresponding to the foreground object and the background. The object and the background are individually encoded using separate parametric coding techniques. While the object is encoded using the projection of coefficients to the orthonormal basis of the learnt subspace (used for appearance based object tracking), the background is characterized using an auto-regressive (AR) process model. An advantage of the proposed schemes is that the decoder structure allows for simultaneous reconstruction of object and background, thus making it amenable to the new multi-thread/multi-processor architectures. | 03-10-2011 |
20110043265 | REDUCED AREA SCHMITT TRIGGER CIRCUIT - A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter. | 02-24-2011 |
20110032136 | REDUCTION IN KICKBACK EFFECT IN COMPARATORS - The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator. | 02-10-2011 |
20110026309 | SELF-TIMED WRITE BOOST FOR SRAM CELL WITH SELF MODE CONTROL - A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods. | 02-03-2011 |
20110004647 | OFFSET-FREE SINC INTERPOLATOR AND RELATED METHODS - An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins. | 01-06-2011 |
20110001518 | OPERATING A SWITCHED-CAPACITOR CIRCUIT WITH REDUCED NOISE - Techniques for operating a switched-capacitor circuit to reduce input and feedback dependence and/or reduce reference modulation. A switched-capacitor circuit can be operated in four phases. In a first phase at a start of a cycle, the capacitor is charged/discharged by a common mode signal to mask any residual charge stored in the capacitor from a previous cycle. In a second phase, the capacitor is charged with an input signal. During a third phase, the capacitor is charged with a wide-bandwidth auxiliary reference signal, and during a fourth phase the capacitor is charged with a reference signal. During the third and fourth phases, the capacitor may be coupled to an integrating to circuit to integrate a difference between the input signal and the reference signal. | 01-06-2011 |
20110001458 | VOLTAGE REGULATOR - Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state. | 01-06-2011 |
20100322016 | RETENTION OF DATA DURING STAND-BY MODE - An embodiment of the present disclosure refers to retention of data in a storage array in a stand-by mode. A storage device comprises one or more storage array nodes, and a Rail to Rail voltage adjustor operatively coupled to the storage array nodes. The Rail to Rail voltage adjustor is configured to selectively alter the voltage provided at each said storage array node during stand-by mode. The storage device may further comprise a storage array operatively coupled to said Rail to Rail voltage adjustor and a Rail to Rail voltage monitor operatively coupled to said storage array nodes and configured to control said Rail to Rail voltage adjustor to provide sufficient voltage to retain data during stand-by mode. | 12-23-2010 |
20100318843 | SHARED FUSE WRAPPER ARCHITECTURE FOR MEMORY REPAIR - A memory repair mechanism for the memories clustered across the multiple power domains and can be switched on and off independent of each other, thereby enabling low power operation. Enhancements in the shared Fuse Wrapper Architecture enable sharing of a plurality of parallel links connecting the memory blocks of each power domains to the Shared Fuse Wrapper architecture. | 12-16-2010 |
20100246736 | CLOCK RECOVERY FROM DATA STREAMS CONTAINING EMBEDDED REFERENCE CLOCK VALUES - A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means. | 09-30-2010 |
20100213980 | ARCHITECTURE FOR EFFICIENT USAGE OF IO - An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level. | 08-26-2010 |
20100207957 | OVERLAYING VIDEOS ON A DISPLAY DEVICE - The embodiments of the present disclosure teach overlaying videos on a display device. The technique involves one or more buffers at input such as a first buffer (Primary Buffer) and an overlay buffer, a blitting module, a second buffer(Frame Buffer), and a display screen. The first buffer provides a first image data to the blitting module and the overlay buffer provides a second image data to the blitting module. The embodiments of the present disclosure demonstrate overlaying the second image on the first image with enhanced configurable functionality (like stretching, clipping, color keying, Alpha Blending and Raster Operation) if required, without modifying the Primary Buffer without the need of any overlay support in hardware. | 08-19-2010 |
20100172199 | BALANCED SENSE AMPLIFIER FOR SINGLE ENDED BITLINE MEMORY ARCHITECTURE - A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell. | 07-08-2010 |
20100172198 | DATA STORAGE ELEMENT SENSING DEVICE - A sensing device for a data storage system may include a sensing circuit, a pull-down circuit, and a pull-up circuit. The sensing circuit may sense discharging of a desired bit line or a complementary bit line and may generate a desired output. The pull-down circuit may be coupled to the bit line and the complementary bit line for enhancing the discharging rate and may increase the sensing speed of the storage system. The pull-up circuit may control the discharging of an undesired bit line or complementary bit line. | 07-08-2010 |
20100171529 | SYSTEM AND METHOD FOR ON-CHIP JITTER AND DUTY CYCLE - An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval. | 07-08-2010 |
20100165755 | SINGLE-ENDED BIT LINE BASED STORAGE SYSTEM - A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal. | 07-01-2010 |
20100165754 | SIGNAL SYNCHRONIZATION IN MULTI-VOLTAGE DOMAINS - A system and a method to improve signal synchronization in a plurality of signal paths traversing multiple voltage domains. According to an embodiment of the present disclosure a memory arrangement is preferred for signal synchronization. All read/write and clocks signals and other control signals are driven to periphery supply (Vp) levels, except wordline (WL[i]) signals which are driven at core supply (Vc) level. By doing so, lower average and peak current consumption associated with core supply (Vc) is achieved with constant delays and maintaining required signal synchronization in the signal paths traversing multiple voltage domains. | 07-01-2010 |
20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
20100164469 | On-chip power management - The present disclosure teaches a power management device for providing one or more voltages and prohibiting the operation until the IC is initialized and voltage stability is achieved. The power management device includes a power regulator block and a masking block. The power regulator block includes one or more of the following elements: -a regulator, a bandgap reference generator, a low voltage detector LVDD, a low voltage detector LVDM, and a plurality of logic gates. In one embodiment, the masking block includes one or more level shifters, a plurality of logic gates, a D flip-flop, and a power on reset circuit (PoR). | 07-01-2010 |
20100162018 | SYSTEM AND METHOD FOR OPTIMIZING ELECTRICAL POWER CONSUMPTION - A system and a method for optimizing power in an electronic device are described. The system may be used to implement low power techniques to achieve maximum performance with low battery utilization. A processing load level monitor monitors load(s) on processors. Processor frequencies are updated through the driver until the load is close to 100%, which means that the core frequency is changed to the load processor around 100% at the minimum possible frequency. | 06-24-2010 |
20100158108 | SYSTEM AND METHOD FOR VIDEO ENCODING - An embodiment of the present disclosure relates to system comprises an encoding device. Said encoding device comprises a compression unit, a quantizer, a bit estimator, a bit rate encoder and a variable length encoder. An embodiment also is a method of encoding. Said method estimates a number of bits to encode a macroblock after compressing the data stream. Then the estimated bit encoded by a bit rate encoder and further quantized by the quantizer to get the final encoded bit stream. The number of bits required to encode a macroblock is estimated after the quantization process and before the encoding process. The macroblock bit estimator estimates the number of bits required to encode a particular macroblock depending on the quantized AC coefficients of that macroblock and the quantized AC coefficients of the neighboring frames normalized at a macroblock level. | 06-24-2010 |
20100157708 | NOISE TOLERANT SENSE CIRCUIT - A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation. | 06-24-2010 |
20100157699 | WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURE - A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry. | 06-24-2010 |
20100156543 | MATRIX STRUCTURE OSCILLATOR - An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance | 06-24-2010 |
20100156524 | PULSE FILTERING MODULE CIRCUIT, SYSTEM, AND METHOD - A filtering module filters out high frequency signals, primarily noise, from an input data stream. The filtering module includes an input module, a phase detecting module, and a threshold module. The input module performs either a charging or a discharging across a capacitor on a basis of an RC time constant. The phase detecting module is coupled to the input module to keep identical phase at a first node and an output node. The threshold module is coupled to the phase detecting module for providing an output signal based on a threshold voltage and the charging or the discharging across the capacitor. | 06-24-2010 |
20100156496 | HIGH VOLTAGE SWITCH WITH REDUCED VOLTAGE STRESS AT OUTPUT STAGE - The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level. The module further comprises a switching circuit that is operatively coupled to the driver output for controlling the passing of a high voltage with high current requirements. | 06-24-2010 |
20100149884 | REDUCTION OF POWER CONSUMPTION IN A MEMORY DEVICE DURING SLEEP MODE OF OPERATION - The present disclosure relates to a system comprising memory device with a power switch where the system comprises a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core; a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core; a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and a second reference voltage coupled to the substrate terminal of said second voltage controlled switch. This helps maintain a sufficient RNM for efficient performance by the system. | 06-17-2010 |
20100146473 | ROUTING SYSTEM - A process for shortest path routing in computer-aided designs (CAD) is performed using an incremental graph traversal technique. This technique searches the shortest path routing trees in a graph by path exploration limited only to an incremented search region thereby reducing run time complexity. Graph traversal begins in the incremented search region, and propagates successive changes thereafter. | 06-10-2010 |
20100146472 | ROUTING SYSTEM - A routing system is improved by performing three steps sequentially to complete an execution process. The first step estimates a normalized criticality score for each design net. The second step arranges the scores for each design net in descending order. Third step rips up and reroutes the design so as to make it more feasible. | 06-10-2010 |
20100135095 | ASSISTANCE IN RESET OF DATA STORAGE ARRAY - A system is capable of assisting in reset of a data storage array including data storage array including one or more data storage array nodes. The system includes a control unit coupled to the data storage array configured to produce a control signal to reset the data storage array, and a reset unit communicatively coupled to the data storage array and the control unit configured to reset the data storage array by charge injection to the one or more data storage array nodes. | 06-03-2010 |
20100128837 | SYSTEM AND A METHOD FOR GENERATING TIME BASES IN LOW POWER DOMAIN - A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter. | 05-27-2010 |
20100117710 | SWITCHED CHARGE STORAGE ELEMENT NETWORK - A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal. | 05-13-2010 |
20100115385 | DETECTING DATA-ACCESS-ELEMENT-SELECTION ERRORS DURING DATA ACCESS IN DATA-STORAGE ARRAYS - An embodiment of the present disclosure relates to detection of data access element selection errors during data access in data storage arrays. An embodiment of the disclosure describes a system including a data storage array comprising a first and a second error identifier. The error identifiers generate an error signal in case multiple data access elements are selected or no data access element is selected, respectively. A system for detection of data-access-element-selection errors further comprises a common error-signal generator which provides an output when an error signal is generated by either of said error identifiers. | 05-06-2010 |
20100095339 | Method and apparatus for designing a communication mechanism between embedded cable modem and embedded set-top box - The present disclosure discloses a digital communication between the between embedded cable modem (eCM) and embedded set-top box (eSTB) via a shared memory. The communication is carried out by packet transfer mechanism as per the protocol without adding any extra header overhead. The communication link is established between the eSTB and eCM mainly in layer 2 and partly in layer 1 according to an implementation of the OSI model. Further, eSTB is used as an eSAFE device coupled to eCM where the eCM and eSTB are considered to be placed on two SoCs with a separate CPU to each SoC (System-On-Chip) with a shared memory (via high speed data bus protocol). DMA (Direct Memory Access) engines are used to accelerate data transfer and to reduce load. DMA of only eCM, SoC is used to minimize hardware resources. | 04-15-2010 |
20100091188 | SYNCHRONIZATION OF SECONDARY DECODED MEDIA STREAMS WITH A PRIMARY MEDIA STREAM - System and method for synchronizing one or more secondary decoded media streams to a primary decoded media stream. The system includes a media stream processor and a mixer. The media stream processor receives a primary decoded media stream and secondary decoded media streams. The media stream processor synchronizes the secondary decoded media streams with the primary decoded media stream. The output of the media stream processor is coupled to the mixer. The mixer receives its second input from the primary decoded media stream. The mixer mixes the received streams and generates a PTS value for its output media stream by extrapolating the PTS of the primary decoded media stream. | 04-15-2010 |
20100067580 | NON-SCALABLE TO SCALABLE VIDEO CONVERTER - Systems and methods are for implementing a NSV2SV converter that converts a non-scalable video signal to a scalable video signal. In an implementation, a non-scalable video signal encoded in H.264/AVC standard is decoded and segmented into spatial data and motion data. The spatial data is resized into a desired resolution by down-sampling the spatial data. The motion data is also resized in every layer, except in the top layer, of a scalable video coding (SVC) encoder by using an appropriate measure. Further, the motion data is refined based on the resized spatial data in every layer of the SVC encoder. The refined motion data and the down-sampled spatial data are then transformed and entropy encoded in the SVC standard in every layer. The SVC encoded output from every layer is multiplexed to produce a scalable video signal. | 03-18-2010 |
20100061164 | FAIL-SAFE HIGH SPEED LEVEL SHIFTER FOR WIDE SUPPLY VOLTAGE RANGE - The present invention discloses a fail-safe level shifter switching with high speed and operational for a wide range of voltage supply. The level shifter includes a cascode module, and one or more speed enhancer modules. The cascode module is receiving one or more input logic signal for generating a plurality of output signals with a reduced switching time. The speed enhancer modules are coupled to the cascode module for facilitating faster charging and discharging of nodes of the cascode module and improving the robustness and operating voltage range of cascode module. | 03-11-2010 |
20100019757 | SYSTEM AND METHOD FOR ON-CHIP DUTY CYCLE MEASUREMENT - An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle. | 01-28-2010 |
20100017651 | SYSTEM AND METHOD FOR EFFICIENT DETECTION AND RESTORATION OF DATA STORAGE ARRAY DEFECTS - The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array. | 01-21-2010 |
20090265739 | METHOD AND SYSTEM FOR CHANNEL SELECTION IN A DIGITAL BROADCAST RECEPTION TERMINAL - The present invention discloses a system and method for channel selection in a digital broadcast reception terminal. The system tunes to different frequencies and generates visual clips corresponding to a plurality of channels in a frequency band. Visual clips of multiple channels are simultaneously displayed on a display screen which provides the user an easy way to select a desired program. | 10-22-2009 |
20090167363 | REDUCTION OF SIGNAL SKEW - Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced. | 07-02-2009 |
20090128104 | FULLY INTEGRATED ON-CHIP LOW DROPOUT VOLTAGE REGULATOR - A low dropout voltage regulator (LDO) includes a bias voltage generator, a differential error amplifier, an output driver, a controlled active load, a Double Ended Cascode Miller compensation block. The bias voltage generator produces a plurality of bias voltages. The differential error amplifier produces a differential output voltage based on the difference between a reference voltage and a function of the output voltage. The input terminal of the output driver is coupled to one output of the differential error amplifier. The substrate terminal of the output driver is capacitively coupled to the output node and resistively coupled to the input supply node. The controlled active load is coupled to the output of the output driver, and its control terminal is coupled to a function of the second output of the differential error amplifier. The inputs of the Double Ended Cascode Miller compensation block are capacitively coupled to the output node and its output is coupled to the input terminal of the output driver. | 05-21-2009 |
20090113099 | ARBITER MODULE PROVIDING LOW METASTABILITY FAILURE PROBABILITY - An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units. | 04-30-2009 |
20090103622 | METHOD AND SYSTEM FOR DETERMINING A MACROBLOCK PARTITION FOR DATA TRANSCODING - A system and corresponding method determines a macroblock partition to transcode digital data from a first video standard to a second video standard with any spatial resolution. The system includes a processing module and an encoding module. The processing module processes digital data to determine a macroblock partition. The encoding module is coupled to the processing module for encoding the digital data based on the macroblock partition. The system is further coupled to a decoding module for receiving the digital data. The method determines the partition of a macroblock for transcoding digital data with any spatial resolution and without any motion estimation. | 04-23-2009 |
20090091358 | Compensated output buffer for improving slew control rate - The present invention provides a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions. The slew rate control circuit consists of two separate slew rate control circuits called a pull-up PMOS driver and a pull-down NMOS driver. To minimize the variations in the slew rate, the rising and falling time of the pre-driver nodes are controlled by means of two current control networks, which are compensated against PVT variations by using separate NMOS and PMOS digital compensation codes. The compensation codes are provided by a compensation circuit, which sense the variation in PVT conditions and reflect these variations in the compensation codes. | 04-09-2009 |
20090076753 | FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION - The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules. | 03-19-2009 |
20090027126 | METHOD FOR ADAPTIVE BIASING OF FULLY DIFFERENTIAL GAIN BOOSTED OPERATIONAL AMPLIFIERS - An adaptive biasing technique improves fully differential gain boosted operational amplifiers transient characteristics and reduces power consumption. An adaptive biasing module includes a bias generation module and a bias replication module. The bias generation module generates a first control signal (VCMNB) and the first control signal is applied as an output common mode of a differential booster (inside the bias replication module). The bias replication module is coupled to the bias generation module for equalizing a common mode of the differential booster with the first control signal (VCMNB). | 01-29-2009 |
20080313480 | ARCHITECTURE INCORPORATING CONFIGURABLE CONTROLLER FOR REDUCING ON CHIP POWER LEAKAGE - The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power. | 12-18-2008 |
20080290915 | SYSTEM AND METHOD FOR FAST RE-LOCKING OF A PHASE LOCKED LOOP CIRCUIT - A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles. | 11-27-2008 |
20080282025 | Wear leveling in storage devices based on flash memories and related circuit, system, and method - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 11-13-2008 |
20080282023 | Restoring storage devices based on flash memories and related circuit, system, and method - A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded. | 11-13-2008 |
20080270622 | METHOD AND SYSTEM FOR OPTIMIZING POWER CONSUMPTION AND REDUCING MIPS REQUIREMENTS FOR WIRELESS COMMUNICATION - The present invention discloses a system and a methodology for enhancing performance during wireless communications by reducing system latency, MIPS requirements and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller retrieves certain information required for data transmission and stores the same locally, the data source provides data directly to the controller without routing the data through the host. The host is relieved of the data processing that needs to be done while the data is being transferred. Hence, the overall latency of the system is improved because of the optimal routing of data traffic. The host can even go to lower power modes while the controller is performing the data operations on behalf of the upper layer stack thereby saving power consumption of the overall system. | 10-30-2008 |
20080238505 | System and method for an automatic coarse tuning of a voltage controlled oscillator in a phase-locked loop (PLL) - Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop. | 10-02-2008 |
20080231310 | FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION - The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules. | 09-25-2008 |
20080219356 | SYSTEM AND METHOD FOR TRANSCODING DATA FROM ONE VIDEO STANDARD TO ANOTHER VIDEO STANDARD - A system and method transcodes an input video bit stream having a first encoding profile into an output video bit stream having a second encoding profile. The system includes a first module ( | 09-11-2008 |
20080218234 | LOW POWER FLIP-FLOP CIRCUIT - A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal and an output signal of the flip-flop. The clock generating circuit generates a pseudo clock signal with a sharp rise and fall based upon an external clock signal. | 09-11-2008 |
20080218151 | ON CHIP DUTY CYCLE MEASUREMENT MODULE - A method and a circuit for measuring an on chip duty cycle. The circuit includes a capacitor, a switching circuit, a current source, a comparator circuit and a counter. The circuit receives a first clock signal and a second clock signal. The first clock signal has a 50% duty cycle and the second signal has an unknown duty cycle signal. The switching circuit first receives the first clock signal and then the second clock signal for measuring the duty cycle. The comparator circuit compares a comparator voltage with a reference voltage for the first clock signal to measure a first elapsed cycle using the counter. The comparator circuit again compares a comparator voltage with a reference voltage for the second clock signal to measure a second elapsed cycle using the counter. The counter measures the first elapsed cycle and the second elapsed cycle corresponding to the first clock signal and the second clock signal for a duration in which the comparator voltage equals the reference voltage. The duty cycle for the second clock signal is then calculated using the first elapsed cycle and the second elapsed cycle. | 09-11-2008 |
20080212354 | BIASED SENSING MODULE - A circuit includes a first pre-charge module, a first multiplexer module, a second pre-charge module, a second multiplexer module, a sense amplifier circuit, a third pre-charge module, an output module. The circuit is operatively coupled to a first core block and a second core block to provide the desired matching characteristics. The first core block and the second core block are memory blocks used for storing data bits for read-write operations. The circuit utilizes a unique operational coupling with one of the core blocks to provide the matching characteristics. | 09-04-2008 |