ELPIDA MEMORY,INC. Patent applications |
Patent application number | Title | Published |
20120043642 | Semiconductor device - A semiconductor device includes a first signal wiring, a first dummy wiring, and a second dummy wiring. The first signal wiring is configured to be supplied with a first signal potential. The first dummy wiring is insulated from the first wiring. The first dummy wiring is configured to be supplied with a fixed potential. The second dummy wiring is disposed between the first signal wiring and the first dummy wiring. The second dummy wiring is insulated from the first dummy wiring. The second dummy wiring is configured to be supplied with substantially the same potential as the first signal potential. | 02-23-2012 |
20110175644 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low. | 07-21-2011 |
20100085824 | Semiconductor device having delay control circuit - A first delay circuit and a second delay circuit having different operation conditions from each other, a detection circuit that detects a difference in propagation speed of a pulse signal, which is simultaneously input to the first and second delay circuits, and a setting circuit that generates a selection signal based on a detection result from the detection circuit are provided. The selection signal is supplied to a delay control circuit that generates an operation timing signal by delaying a reference signal, of which a delay amount is controlled by the selection signal. With this arrangement, a necessity to set the delay amount of the delay control circuit with a large design margin can be eliminated considering PVT variation, and as a result, performance degradation can be prevented. | 04-08-2010 |
20100072552 | FIELD EFFECT TRANSISTOR FOR PREVENTING COLLAPSE OR DEFORMATION OF ACTIVE REGIONS - A field effect transistor includes an active region provided in a projecting part on a surface of a semiconductor substrate, the projecting part extending in a fixed direction parallel to the surface, and a gate electrode provided on a sidewall of the projecting part along the fixed direction with a gate insulating films interposed. | 03-25-2010 |
20090230464 | SEMICONDUCTOR DEVICE INCLUDING TRENCH GATE TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor device may include at least one active region that has at least one trench groove. A fin channel region is deposed in the active region and between the at least one trench groove and an isolation region of the semiconductor substrate. The gate insulating film is disposed on inside walls of the at least one trench groove. The gate electrode is disposed on the gate insulating film and in the at least one trench groove. The gate electrode is separated by the gate insulating film from the fin channel region. The source and drain regions are disposed in the active region, and are connected to the fin channel region. The junction of each of the source and drain regions with the semiconductor substrate is deeper than the bottom of the fin channel region. | 09-17-2009 |
20090196009 | Semiconductor module, wiring board , and wiring method - A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other. | 08-06-2009 |
20090170272 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and top electrodes and a capacitive insulating film. The capacitive insulating film is sandwiched between the bottom and top electrodes. The adhesive layer contacts with the bottom electrode. The adhesive layer has adhesiveness to the bottom electrode. The intermediate layer is interposed between the adhesive layer and the first insulating film. The intermediate layer contacts with the adhesive layer and with the first insulating film. The intermediate layer has adhesiveness to the adhesive layer and to the first insulating film. | 07-02-2009 |