Verigy (Singapore) Pte. Ltd. Patent applications |
Patent application number | Title | Published |
20140189430 | SYSTEM, METHODS AND APPARATUS USING VIRTUAL APPLIANCES IN A SEMICONDUCTOR TEST ENVIRONMENT - In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of the hardware resources. Each virtual set of the hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance. | 07-03-2014 |
20110276302 | RE-CONFIGURABLE TEST CIRCUIT, METHOD FOR OPERATING AN AUTOMATED TEST EQUIPMENT, APPARATUS, METHOD AND COMPUTER PROGRAM FOR SETTING UP AN AUTOMATED TEST EQUIPMENT - A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device. | 11-10-2011 |
20110254719 | DECORRELATION OF DATA BY USING THIS DATA - A device for processing data adapted for being converted between an analog format and a digital format, the device having a scrambling unit adapted for scrambling the data based on at least a part of the data to thereby decorrelate the data in the analog format with respect to the data in the digital format. | 10-20-2011 |
20110238345 | SYSTEM, METHOD AND COMPUTER PROGRAM FOR DETECTING AN ELECTROSTATIC DISCHARGE EVENT | 09-29-2011 |
20110231464 | STATE MACHINE AND GENERATOR FOR GENERATING A DESCRIPTION OF A STATE MACHINE FEEDBACK FUNCTION - An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream. | 09-22-2011 |
20110197086 | DATA PROCESSING UNIT AND A METHOD OF PROCESSING DATA - A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information. | 08-11-2011 |
20110191398 | METHOD AND APPARATUS FOR DETERMINING A MINIMUM/MAXIMUM OF A PLURALITY OF BINARY VALUES - For determining a minimum/maximum of a plurality of binary values a bit position in the plurality of binary values is determined subsequent to which all bit values are the same. From the plurality of binary values those binary values are selected the bit values of which at the bit position determined in the preceding step and all subsequent positions, if any, has a predetermined value. The preceding steps are then repeated until only one binary value remains which is provided as the minimum or maximum. | 08-04-2011 |
20110187399 | SIGNAL DISTRIBUTION STRUCTURE AND METHOD FOR DISTRIBUTING A SIGNAL - A signal distribution structure for distributing a signal to a plurality of devices includes a first signal guiding structure including a first characteristic impedance. The signal distribution structure also includes a node, wherein the first signal guiding structure is coupled to the node. The signal distribution structure includes a second signal guiding structure including one or more transmission lines. The one or more transmission lines of the second signal guiding structure are coupled between the node and a plurality of device connections. The second signal guiding structure includes, side-viewed from the node, a second characteristic impedance which is lower than the first characteristic impedance. The signal guiding structure also includes a matching element connected to the node. | 08-04-2011 |
20110145654 | METHOD AND APPARATUS FOR THE DETERMINATION OF A REPETITIVE BIT VALUE PATTERN - A repetitive bit value pattern associated to a predetermined bit position of a sequence of data words, the data words having two or more bits in a bit order, a bit position describing a position within the bit order being indicative of a value represented by the bit at the bit position, can be determined from program loop information, the program loop information having a program expression for determining an updated data word of the sequence of data words. Using the predetermined bit position, a sequence length value associated to the predetermined bit position is determined. The program expression is evaluated for a number of loop iterations indicated by the sequence length value, to obtain updated bit values associated to the predetermined bit position. The repetitive bit value pattern is determined using the updated bit values of the number of loop iterations. | 06-16-2011 |
20110145645 | TEST SYSTEM AND METHOD FOR TESTING ELECTRONIC DEVICES USING A PIPELINED TESTING ARCHITECTURE - A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction. | 06-16-2011 |
20110140737 | APPARATUS AND METHOD FOR ESTIMATING DATA RELATING TO A TIME DIFFERENCE AND APPARATUS AND METHOD FOR CALIBRATING A DELAY LINE - An apparatus for estimating data relating to a time difference between two events includes a delay line having a plurality of stages. Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device is provided for summing over the indication signals of the plurality of stages to obtain a sum value. The sum value indicates a time difference estimate. | 06-16-2011 |
20110131000 | CHIP TESTER, METHOD FOR PROVIDING TIMING INFORMATION, TEST FIXTURE SET, APPARATUS FOR POST-PROCESSING PROPAGATION DELAY INFORMATION, METHOD FOR POST-PROCESSING DELAY INFORMATION, CHIP TEST SET UP AND METHOD FOR TESTING DEVICES UNDER TEST - A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information. | 06-02-2011 |
20110089966 | APPARATUS AND SYSTEMS FOR PROCESSING SIGNALS BETWEEN A TESTER AND A PLURALITY OF DEVICES UNDER TEST - Apparatus is for processing signals between a tester and devices under test. In one embodiment, the apparatus includes at least one multichip module. Each multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to devices under test. At least one driver is provided to operate each of the micro-electromechanical switches. Other embodiments are also disclosed. | 04-21-2011 |
20110041012 | METHOD OF SHARING A TEST RESOURCE AT A PLURALITY OF TEST SITES, AUTOMATED TEST EQUIPMENT, HANDLER FOR LOADING AND UNLOADING DEVICES TO BE TESTED AND TEST SYSTEM - A method of sharing a test resource at a plurality of test sites executes respective test flows at the plurality of test sites with an offset in time, the respective test flows accessing the test resource at a predetermined position in the test flow. | 02-17-2011 |
20110032829 | METHOD AND APPARATUS FOR DETERMINING RELEVANCE VALUES FOR A DETECTION OF A FAULT ON A CHIP AND FOR DETERMINING A FAULT PROBABILITY OF A LOCATION ON A CHIP - A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination. | 02-10-2011 |
20100301885 | HIGH IMPEDANCE, HIGH PARALLELISM, HIGH TEMPERATURE MEMORY TEST SYSTEM ARCHITECTURE - An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 μm exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head. | 12-02-2010 |
20100269336 | METHODS FOR FABRICATING CIRCUIT BOARDS - A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes. | 10-28-2010 |
20100176815 | Apparatus, Method, and Computer Program for Obtaining a Time-Domain-Reflection Response-Information - An apparatus for obtaining a time-domain-reflection response-information has a signal driver adapted to apply two pulses of different pulse lengths to a TDR port in order to excite a first TDR response signal corresponding to a first pulse and a second TDR response signal corresponding to a second pulse. The apparatus has a timing determinator adapted to provide a timing information on the basis of a first instance in time when the first TDR response signal crosses a threshold value and on the basis of a second instance in time when the second TDR response signal crosses the threshold value. The apparatus has a TDR response information calculator adapted to calculate an information about a TDR response on the basis of the timing information. | 07-15-2010 |
20100164527 | TEST MODULE WITH BLOCKS OF UNIVERSAL AND SPECIFIC RESOURCES - A test module for a test apparatus for testing a device under test, the test module being adapted for performing a specific test function and having a universal section adapted to provide test resources being unspecific with regard to the test function of the test module, the universal section having a control interface adapted to be connected to a central control device of the test apparatus, and having a specific section to be coupled to the universal section and adapted to provide test resources being specific with regard to the test function of the test module, the specific section having a device under test interface adapted to be connected to the device under test. | 07-01-2010 |
20100045499 | ASYNCHRONOUS SIGMA-DELTA DIGITAL-ANALOG CONVERTER - An asynchronous sigma delta digital to analog converter for converting a digital input signal into an analog output signal, the digital to analog converter having an asynchronous sigma delta modulator having a low pass filter and a comparator and being supplied with the digital input signal, and a clock sample unit adapted to sample a signal processed by the comparator based on a clock signal, thereby generating the analog output signal. | 02-25-2010 |
20100011252 | FORMAT TRANSFORMATION OF TEST DATA - A device for processing test data, the device having a data input interface adapted for receiving primary test data indicative of a test carried out for testing a device under test, the primary test data being provided in a primary format, a processing unit adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units. | 01-14-2010 |
20090322574 | TIME-TO-DIGITAL CONVERSION WITH DELAY CONTRIBUTION DETERMINATION OF DELAY ELEMENTS - A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal. | 12-31-2009 |
20090303091 | Time-to-Digital Conversion With Calibration Pulse Injection - A time-to-digital converter having at least one chain of delay elements, wherein a status of the chain of delay elements represents a digital signal relating to a time interval to be converted, wherein the time-to-digital converter having an injector for injecting a calibration pulse of known position and/or known duration in time into the chain of delay elements, wherein a first status of the chain of delay elements being expected in response to the calibration pulse, the time-to-digital converter further having a capturer for capturing the actual status of the chain of delay elements in response to the calibration pulse, a calculator for calculating a deviation between the expected first status and the actual status, and a combination unit for taking into account the deviation when converting the time interval to the digital signal. | 12-10-2009 |
20090219010 | CALIBRATING SIGNALS BY TIME ADJUSTMENT - A signal processing device having an adjustment unit for adjusting a time duration of each of a plurality of signals individually in accordance with an amplitude of the respective signal to thereby generate calibrated signals, and a combining unit for combining the calibrated signals. | 09-03-2009 |
20090212882 | TRANSMIT/RECEIVE UNIT, AND METHODS AND APPARATUS FOR TRANSMITTING SIGNALS BETWEEN TRANSMIT/RECEIVE UNITS - In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed. | 08-27-2009 |
20090212799 | METHODS AND APPARATUS THAT SELECTIVELY USE OR BYPASS A REMOTE PIN ELECTRONICS BLOCK TO TEST AT LEAST ONE DEVICE UNDER TEST - In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed. | 08-27-2009 |
20090055690 | Error catch RAM support using fan-out/fan-in matrix - In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device. | 02-26-2009 |
20090053837 | Wafer boat for semiconductor testing - In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield. | 02-26-2009 |